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Accurate negative bias temperature instability lifetime prediction based on hole injection
Microelectronics Reliability 48 (2008) 1649–1654
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Accurate negative bias temperature instability lifetime prediction based on hole injection Akinobu Teramoto a,*, Rihito Kuroda b,c, Shigetoshi Sugawa b, Tadahiro Ohmi a a
New Industry Creation Hatchery Center, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan Graduate School of Engineering, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan c Japan Society for the Promotion of Science Research Fellowship, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan b
a r t i c l e
i n f o
Article history: Received 18 March 2008 Received in revised form 7 July 2008 Available online 22 August 2008
a b s t r a c t Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO2 film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (=Qhole/Jinj0), accurate lifetime prediction in terms of the Vth shift is realized, and by analyzing of relationship between ID reduction and Vth shift, accurate lifetime prediction in terms of the ID reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction
DV FB ;
DV th / t0:20:25
ð1Þ b
Gate insulator films become thinner with the metal-oxidesemiconductor (MOS) device shrinking and reach around 1 nm. Thin gate insulators have severe problems such as very high leakage current and reliability issues. Negative bias temperature instability (NBTI) is one of the most crucial issues for the LSI reliability. For the prediction of long time reliability, the electrical stress acceleration is often employed. NBT stress induces the fixed charge in the gate insulator films and surface state at Si/gate insulator interface, as a result, causes the threshold voltage (Vth) shift and degradation of drain current [1–9]. For an accurate lifetime prediction, an accurate understanding of the degradation mechanism and an appropriate acceleration method are essentially required. Several models for NBTI induced degradation have been proposed [10–26]. It has been experimentally reported that the Vth and the flat-band voltage (VFB) shift in capacitance–voltage (C–V) characteristics of MOS diode and the fixed charge in the gate insulator films increase as follows [5–7,10,13,20–25]:
* Corresponding author. Tel.: +81 22 795 3977; fax: +81 22 795 3986. E-mail address: [email protected] (A. Teramoto). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.062
DV th / 1 expððt=sÞ Þ
ð2Þ
It has also been reported that the Si–H bond is broken at the Si/ gate insulator interface and H+ ion is diffused away from its interface to the gate electrode by NBT stress [10–14,16–24]. Following this model, the Vth shift increases as Eq. (1). Considering the trap sites created by Si–H decomposition, the Vth shift increase as Eq. (2) [26]. Recently, it has been reported that the stress time dependency of Vth shift is less than 0.25, when the on-the-fly measurement is employed [27,28]. However, these models are based on the conventional NBTI measurement performed under high electric field (>8 MV/cm) and high temperature (>398 K). Compared to the operation condition of 4–8 MV/cm and <398 K, measurement bias and temperature acceleration induces much larger degradation to p-MOSFETs’ electrical characteristics than that occurs in the LSI operation condition and makes the lifetime-prediction difficult. We have reported that the degradation mechanism is different between the operation condition and the high stress conditions which are often used for NBTI lifetime measurement [29–33]. The high gate voltage not only increases the hole density in the inversion layer but also causes an excessive band bending, as a result, the band bending enhances the hole energy. It means the degradation mechanism
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A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
might be deferent between the evaluation condition and operation condition. In this paper, we describe the NBTI lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration and lifetime comparison between SiO2 film and SiON film based on the method. 2. Experimental Sample devices are fabricated in a 130 nm CMOS process technology, and are fabricated on a p(epitaxial layer)/p+ substrate. Geometry of the devices is W/L = 10.0/10.0 lm. The gate insulator materials are thermally oxidized pure SiO2 and SiON formed by thermally oxidation and N2O oxynitridation [34,35]. Their equivalent oxide thicknesses from capacitance–voltage measurement are 2.0 nm. The operation voltage (VDD) is 1.2 V and then measurement voltages are 1.2 V and 2.0 V which is conventional NBTI stress condition. Temperature is 398 K. Stress gate voltage and temperature are applied while source, drain and n-well are grounded. Current of each terminal is monitored by ampere meters. In our evaluation method, the backside pn junction that consists of n-well and p/p+ substrate is used as a hole injection source. Vth is measured in-between the stress within 10 s to minimize a recovery effect. In this experiment, on the fly measurement [27,28] was not employed. However, the circuit simulation results of frequency degradation in the ring oscillator using Vth shift and ID degradation from this measurement technology have agreed with experimental results, and its oscillation frequency is as high as 80 MHz. (shown in Fig.
Output Voltage [V]
1.60
1) [30,32,33]. Vth is measured by conventional gm-max method. The resolution of Vth shift is 0.1 mV using the gm-max method. Fig. 2a and b shows the schematic view and the energy band diagram during the stressing period of the hole injection method [29–33,36], respectively. The acceleration parameter is defined by the gate current density (Jinj) which is proportional to the amount of the non-energetic cold holes injected into the inversion layer during the stress [31]. And it is controlled by bias level of the backside pn junction. Additionally, the grounded n-well guarantees that the injected holes are not given any energy while diffusing from backside p+ substrate to the end of the depletion layer of the stressed device, thus only the rate of the degradation is accelerated by increased number of holes, but not energy of holes. Hole injection method has its limit in allowable injection amount [29– 33]. With the appropriate region, we can obtain the quantitative NBTI degradation behavior with no acceleration of the gate voltage and the temperature. In this acceleration method, the degradation mechanism is same as the operation condition, however, acceleration factor is about one order of magnitude which is still small [31]. Furthermore improvement is necessary for quality assurance about reliability. The current flows during the stress are taken into account to define the acceleration parameter in our system. Almost all the generated holes in pn junction recombine with electrons in the n-well region. A part of the injected holes reach the depletion layer. A small numbers of these holes are injected into the inversion layer. Summation of the injected hole density (Ninj) and the static inversion hole density (Ninv) is the effective inversion hole density. A
199-stage ring oscillaor NMOS: W/L=10.0/0.13[μm], PMOS:W/L=20.0/0.13[μm] measured initial waveform lines: Simulation measured waveform after 650 hours stress (stress VDD=2.0V @398K)
1.20
0.80
0.40
0.00 0.0
10.0
20.0
30.0
40.0
50.0
Time [nsec] Fig. 1. Circuit simulation results of frequency degradation in the ring oscillator using Vth shift and ID degradation from this measurement technology [30,32,33]. These have agreed with experimental results, and its oscillation frequency is as high as 80 MHz.
For monitoring Gate Current
A -VG
Hole Source N-Well
ID/S
ID/S
Isub
(grounded)
P-Sub st ra te
N+ n-Well
Hole Injection
pn junction
p+ IPN
hole injection
Forward bias ( VP N )
a
b
Fig. 2. Schematic view (a) and the energy band diagram (b) during the stressing period of the hole injection method.
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
principal acceleration parameter (A) is determined as follows in our system:
A¼
ðNinj þ Ninv Þ Ninv
ð3Þ
However, we cannot directly observe Ninj. Fortunately, the tunneling current (gate current) has a physical relationship with the hole density in the inversion layer since then we can estimate Ninj from the gate current via some mathematical calculation. We take the gate current density as the unique acceleration parameter in our system. The gate currents with and without the hole injection are required to calculate Ninj. The gate current is measured by a conventional carrier separation technique [37,38]. The carrier separation measurement is executed while the drain/source and well are biased at common. The backside pn junction is also biased at common. Fig. 3 displays the measured currents. The dominant component of the gate current is the hole current at the operation condition. Here, we define the physical parameter Qhole for degradation analysis. The definition of Qhole is as follows:
Q hole ¼ J inj tstress
ð4Þ
where Jinj and tstress are the gate current with the hole injection and stress time, respectively. 3. Results and discussion Fig. 4 shows the Vth shift of PMOSFETs with gate insulator of SiO2 and SiON as a function of a stress time in conventional NBTI
-6
10
abs( IG , IDS , I well ) [A]
I DS (hole current) IG I well
SiO 2
-7
10
-8
10
-9
10
-10
10
SiON
-11
10
-12
10
-13
10
Temp.=398[K]
-14
10
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Gate Voltage [V] Fig. 3. Charge separation results for p-MOSFETs having SiO2 and SiON gate insulator.
3
10
Vth Shift [mV]
SiON SiO2
EOT = 2.0 [nm] Stress VG=-2.0 [V] Temp. = 398 [K]
2
10
1
10
0
10 0 10
1
10
2
10
3
10
4
10
5
10
Stress Time [sec] Fig. 4. Vth shift of PMOSFETs with gate insulator of SiO2 and SiON as a function of a stress time in conventional NBTI stress. VG = 2.0 V and Temperature = 398 K.
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stress condition of VG = 2.0 V and temperature = 398 K. The slopes in Fig. 4 are 0.25 for both SiON and SiO2 films and the Vth shift for SiON is one order of magnitude larger than that for SiO2. It has been reported the NBTI in SiON films is much larger that in SiO2 films [8,18,21–23,26]. This result agrees with these previous results. Fig. 5 shows the Vth shift as functions of Jinj (a) and Qhole (b) which is calculated by Eq. (4). Stress time is 1000 s for all devices. The Vth shifts clearly consist of two regions, which are named as the low and the high injection region. In the low injection region, the Vth shift at a certain Jinj increases as the stress gate voltage is increased. However, this behavior is not observed in the high injection region, i.e. the Vth shifts in the high injection region do not show the stress gate voltage dependence. Fig. 5b contains the results of the samples stressed by the operation voltage and temperature condition with and without the hole injection, accompanied by the results of samples stressed by conventional high gate voltage. Firstly, the Vth shifts of samples stressed by low Jinj with the operation voltage (VG = 1.2 V) are same as the Vth shifts of samples stressed in the operation condition without the hole injection. This result confirms that the holes injection method, when low injection region is used, accelerates the degradation by mean of the stress time, but does not change the degradation mechanism or magnitude from that of the operation condition without injections. However, the Vth shifts of devices stressed by high stress voltage or by the high Jinj show the completely different behavior, i.e. the exponential slope is around 0.25 throughout the measurement and the shifts are independent on the stress voltage, like previously reported [7,10,13,20–25]. This result indicates that the dominant degradation mechanism is changed in these acceleration conditions from that of the operation condition. Thus, to develop the degradation model for the lifetime prediction and the circuit performance prediction, we must only use the degradation behavior of devices stressed by hole injection method in the low Jinj regime with operation bias and temperature condition among the experimented degradation acceleration methods [29–33]. Then, the hole acceleration method is applied to these PMOSFETs with SiO2 and SiON films instead of the conventional stress condition such as high gate voltage stress. Stress conditions are VG of 1.2 V, temperature of 398 K, and Jinj of 9.2 104 A/cm2 for SiON and 3.9 102 A/cm2 for SiO2, respectively. Fig. 6 shows the Vth shift as a function of a stress time in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection. The Vth shifts for SiON is about one order of magnitude larger than that for SiO2 for each stress. Fig. 7 shows the Vth shift as a function of Qhole, which is calculated from the stress time and Jinj using Eq. (4), in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection. The Vth shift differences between SiO2 and SiON for same stress conditions increase compared to VG shift-stress time characteristics shown in Fig. 6. The increase of the difference between Figs. 6 and 7 is caused by the Jinj difference for SiO2 and SiON in stress conditions, i.e. Jinj for SiON and SiO2 are 9.2 104 and 3.9 102 A/cm2, respectively. Then, the differences between SiO2 and SiON in Fig. 7 are larger than that in Fig. 6. This indicates that the Jinj in stress condition and operation condition is very important parameter for comparing of NBTI lifetime in different devices such as PMOSFET with different gate insulators. Fig. 3 also shows the measured currents of the gate (IG), drain/source (ID/S) and the substrate (ISUB) electrodes of the MOSFETs with the gate insulators of SiO2 and SiON as a function of the gate voltage. The gate currents with and without the hole injection are required to calculate Jinj. The gate current is measured by a conventional carrier separation technique [29–33,37,38]. The carrier separation measurement is executed while the drain/source and well are biased at common. At the operation bias point of 1.2 V, the Jinj0 which is hole current without additional hole injection and is measured as ID/S for SiO2 and SiON are 3.32 102 and 8.30 104 A/
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
101 Stresdssed @300K for 10 [sec]
Vth Shift [mV]
Vth Shift [mV]
101
100
10-1
VG=0.7V VG=1.2V VG=2.0V
10-2 10-2
10-1
100
101
100
10-1 VG=0.7V VG=1.2V VG=2.0V
10-2 10-2
102
102
Stresdssed @300K for 100 [sec]
Vth Shift [mV]
1652
10-1
100
101
Stresdssed @300K f or 1000 [sec]
101
100
VG=0.7V VG=1.2V VG=2.0V
10-1 10-2
102
10-1
100
101
102
Injection Current Density (Jinj) [A/cm 2]
Injection Current Density (Jinj) [A/cm 2]
Injection Current Density (Jinj) [A/cm 2]
(a) 10 sec
(b) 100sec
(c) 1000sec
Fig. 5. Vth shift as functions of Jinj for stress time of (a) 10, (b) 100, and (c) 1000 s.
Fig. 8. Fig. 8 shows the Vth shift as a function of the effective stress time. Although Jinj is different in stress time, the Vth shifts for same gate insulator and same gate voltage are the almost same. This means that the NBTI lifetime measurement can be accelerated by hole injection without changing the degradation mechanism and an accurate lifetime prediction can be realized. In this experiment, the NBTI lifetime of SiON is much less than that of SiO2. The lifetime can be predicted applying of the previously reported charge trapping induced Vth shift model [26,29–33] shown as Eq. (6) to Fig. 8:
2
Vth Shift [mV]
Temperature=398 [K]
10
10
1
Tox=2.0 [nm], SiO2
~1/4
L/W=10/10 [μm]
0
VG=-1.2 V, No Injection VG=-1.2 V, Low Jinj.=3.8x10 -2[A/cm2 ] VG=-1.2 V, High Jinj.=1.9x100[A/cm 2 ] VG=-1.8 V, NO Injection
-1
10 -1 10
10
0
10
1
10
2
10
3
10
4
10
5
DV th ¼
2
Qhole[C/cm ] Fig. 6. Vth shift as functions of Qhole. Stress time.
10 3
Vth Shift [mV]
10 2
SiON -1.2V , Jinj .=9.2x 10 -4 [A/c m 2 ] SiON -2V, No injection SiO 2 -1.2V , Jinj .=3.9x 10 -2 [A/c m 2 ] SiO 2 -2 .0 V, No injection
101
10 0 Temp. = 398 [K] EOT = 2.0 [nm] -1
10 0 10
1
10
10
2
10
3
10 4
10 5
10 6
Stress Time [sec] Fig. 7. Vth shift as a function of a stress time in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection.
cm2, respectively. The Jinj at operation condition of SiO2 is about 40 times larger than that of SiON and this means that the NBTI lifetime for SiON is 40 times larger than that for SiO2 when the Vth shift–Qhole characteristics of both SiO2 and SiON are the same. However, the Vth shift–Qhole characteristics of different gate insulator films are actually different for almost all cases. Then, an effective stress time which is shown as Eq. (5) is introduced:
Effective Stress time ¼ Q hole =J inj0 ð@V G ¼ 1:2 V without hole injection from the backside pn junctionÞ
ð5Þ
It is possible to predict the NBTI lifetime by comparing between the actual Vth shift and criteria of the Vth shift at the device guaranteed time in Vth shift – Effective stress time characteristics as shown in
( ) q c Q hole b Dtrap-max 1 exp r C ox q
ð6Þ
where Dtrap-max, is the maximum trap density effectively active for a stress bias condition. r and b are the capture cross-section and the dispersion constant of trap sites, respectively. When the criterion of Vth shift is 100 mV, the lifetime of SiON are 6.55 106 s for hole injection method and 104 sec for conventional high gate voltage condition. On the other hand, the lifetimes of SiO2 are about 7 106 s (or the less) for conventional method and infinity compared to the 10 years because the Vth shift saturates in Fig. 8 and cannot reach 100 mV. It is noticed that the lifetimes measured by the hole injection stress for both gate insulators are larger than those measured by the conventional stress. Especially in SiO2, the lifetime measured by the conventional method cannot be guaranteed for 10 years, however, that measured by the hole injection method can be guaranteed. This fact is very important for device performance and reliability. We have already reported the ID reduction model and a circuit degradation using the Vth shift and ID reduction caused by NBT stress [30,32,33]. The following equation that shows the total ID reduction including the effect of both voltage overdrive and mobility reduction has been reported [30,32,33]:
Vth Shift [mV]
10
10
3
10
2
SiON-1.2V, Jinj.=9.2x10-4[A/cm 2 ] SiON-2.0V, No injection SiO2-1.2V, Jinj.=3.9x10 -2[A/cm 2 ] SiO2 -2.0V, No injection
1
10
10 0
Temp. = 398 [K] EOT = 2.0 [nm]
-1
10
10
-3
10
-2
10
-1
10
0
Q hole
1
10
10
2
10 3
10 4
10 5
[C/cm 2]
Fig. 8. Vth shift as a function of Qhole, which is calculated from the stress time and Jinj using Eq. (5).
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
101
and by analyzing of relationship between ID reduction and Vth shift, accurate lifetime prediction for the ID reduction and the degradation prediction in circuit level are realized. These results are essential for accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.
100
Acknowledgements
Temp. = 398 [K] EOT = 2.0 [nm]
102
th
V shift [mV]
103
10-1 0 10
1
10
10
2
6.55x1 0 6[sec ]
10
3
10
4
10
5
10
6
10
7
10
8
EffectiveStress Time [sec] Fig. 9. Vth shift as a function of the effective stress time. Effective stress time = Qhole/ Jinj (@ VG = 1.2 V without hole injection from the backside pn junction).
10
The authors gratefully acknowledge Dr. Kazufumi Watanabe, Mr. Michihiko Mifuji and Mr. Takahisa Yamaha for their technical advices and useful discussions. This work was supported in part by the New Intelligence for IC Differentiation project (DIIN project) in Tohoku University. R. Kuroda would like to acknowledge Japan Society for the Promotion of Science Research Fellowship Program (No. 19 1356).
2
References
measured at VG=VD=-1.2 [V] Id sat degradation [%]
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1
10
θ=4.50x10-12 [cm2] 10
0
VGstress SiON, -2.0 V SiON, -1.32 V SiON, -1.2V No injection SiON, -1.2V hole injection
-1
10
10
0
1
10
10
2
10
3
Vth Shift [mV] Fig. 10. Relationship of ID reduction and Vth shift for SiON.
DIDsat a h C i =q DV th ½% ¼ 100 þ IDsat V G V th ð1 þ aDi Þ
ð7Þ
where l is carrier mobility and Ci is gate capacitance, a is the parameter that accounts for the carrier velocity saturation effect and is 2 for the long channel device and less for short channel device and h is the mobility reduction parameter indicating carrier screening cross section of the stress induced positive charge at and near the interface. Fig. 9 shows the relationship of ID reduction and Vth shift for SiON. The ID reduction is proportional to the Vth shift. This indicates that h can be defined one value for this PMOSFET, and the h value in this experiment is 4.50 1012 cm2, and this value is a little larger than the h value for SiO2 of 3.72 1012 cm2 which is reported in [30,32,33]. The h value is concerned with the fixed charges and interface states, which cause the mobility degradation. This suggests that the influence of introduction of nitrogen into gate insulator films on the carrier scattering. These results enable to predict the accurate lifetime for NBTI stress in circuit level [30,32,33] (see Fig. 10). 4. Conclusions We demonstrated that the NBTI measurement and lifetime prediction of PMOSFET with gate insulators of SiO2 and SiON based on the hole injection method. using the hole injection method, the NBTI lifetime of SiON is less than that of SiO2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By introduction of effective stress time (=Qhole/Jinj0), accurate lifetime prediction for the Vth shift is realized,
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[32] Kuroda R, Teramoto A, Watanabe K, Mifuji M, Yamaha T, Sugawa S, et al. Circuit level prediction of device performance degradation due to negative bias temperature stress. Microelectron Rel 2007;47:930–6. [33] Teramoto A, Kuroda R, Ohmi T. NBTI mechanism based on hole-injection for accurate lifetime prediction. Electrochem Soc Trans 2007;6(3):229–43. [34] Uchiyama A, Fukuda H, Hayashi T, Iwabuchi T, Ohno S. High performance dualgate sub-halfmicron CMOSFETs with 6 nm-thick nitrided SiO2 films in an N2O ambient. In: IEDM Technical Digest, San Francisco; 1990. p. 425–8. [35] Hwang H, Ting W, Kwong D-L, Lee J. Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N2O. In: IEDM Technical Digest, San Francisco; 1990. p. 421–4. [36] Khosru QDM, Yasuda N, Maruyama A, Taniguchi K, Hamaguchi C. Spatial distribution of trapped holes in the oxide of metal oxide semiconductor fieldeffect transistors after uniform hot-hole injection. Jpn J Appl Phys 1991;30(12B):3652–6. [37] Chang C, Hu C, Broderson W. Quantum yield of electron impact ionization in silicon. J Appl Phys 1985;57(2):302–9. [38] Shi Y, Ma TP, Prasad S, Dhanda S. Polarity dependent gate tunneling currents in dual-gate CMOSFETs. IEEE Trans Electron Dev 1998;45(11):2355–60.
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Accurate negative bias temperature instability lifetime prediction based on hole injection Akinobu Teramoto a,*, Rihito Kuroda b,c, Shigetoshi Sugawa b, Tadahiro Ohmi a a
New Industry Creation Hatchery Center, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan Graduate School of Engineering, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan c Japan Society for the Promotion of Science Research Fellowship, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan b
a r t i c l e
i n f o
Article history: Received 18 March 2008 Received in revised form 7 July 2008 Available online 22 August 2008
a b s t r a c t Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO2 film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (=Qhole/Jinj0), accurate lifetime prediction in terms of the Vth shift is realized, and by analyzing of relationship between ID reduction and Vth shift, accurate lifetime prediction in terms of the ID reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction
DV FB ;
DV th / t0:20:25
ð1Þ b
Gate insulator films become thinner with the metal-oxidesemiconductor (MOS) device shrinking and reach around 1 nm. Thin gate insulators have severe problems such as very high leakage current and reliability issues. Negative bias temperature instability (NBTI) is one of the most crucial issues for the LSI reliability. For the prediction of long time reliability, the electrical stress acceleration is often employed. NBT stress induces the fixed charge in the gate insulator films and surface state at Si/gate insulator interface, as a result, causes the threshold voltage (Vth) shift and degradation of drain current [1–9]. For an accurate lifetime prediction, an accurate understanding of the degradation mechanism and an appropriate acceleration method are essentially required. Several models for NBTI induced degradation have been proposed [10–26]. It has been experimentally reported that the Vth and the flat-band voltage (VFB) shift in capacitance–voltage (C–V) characteristics of MOS diode and the fixed charge in the gate insulator films increase as follows [5–7,10,13,20–25]:
* Corresponding author. Tel.: +81 22 795 3977; fax: +81 22 795 3986. E-mail address: [email protected] (A. Teramoto). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.062
DV th / 1 expððt=sÞ Þ
ð2Þ
It has also been reported that the Si–H bond is broken at the Si/ gate insulator interface and H+ ion is diffused away from its interface to the gate electrode by NBT stress [10–14,16–24]. Following this model, the Vth shift increases as Eq. (1). Considering the trap sites created by Si–H decomposition, the Vth shift increase as Eq. (2) [26]. Recently, it has been reported that the stress time dependency of Vth shift is less than 0.25, when the on-the-fly measurement is employed [27,28]. However, these models are based on the conventional NBTI measurement performed under high electric field (>8 MV/cm) and high temperature (>398 K). Compared to the operation condition of 4–8 MV/cm and <398 K, measurement bias and temperature acceleration induces much larger degradation to p-MOSFETs’ electrical characteristics than that occurs in the LSI operation condition and makes the lifetime-prediction difficult. We have reported that the degradation mechanism is different between the operation condition and the high stress conditions which are often used for NBTI lifetime measurement [29–33]. The high gate voltage not only increases the hole density in the inversion layer but also causes an excessive band bending, as a result, the band bending enhances the hole energy. It means the degradation mechanism
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A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
might be deferent between the evaluation condition and operation condition. In this paper, we describe the NBTI lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration and lifetime comparison between SiO2 film and SiON film based on the method. 2. Experimental Sample devices are fabricated in a 130 nm CMOS process technology, and are fabricated on a p(epitaxial layer)/p+ substrate. Geometry of the devices is W/L = 10.0/10.0 lm. The gate insulator materials are thermally oxidized pure SiO2 and SiON formed by thermally oxidation and N2O oxynitridation [34,35]. Their equivalent oxide thicknesses from capacitance–voltage measurement are 2.0 nm. The operation voltage (VDD) is 1.2 V and then measurement voltages are 1.2 V and 2.0 V which is conventional NBTI stress condition. Temperature is 398 K. Stress gate voltage and temperature are applied while source, drain and n-well are grounded. Current of each terminal is monitored by ampere meters. In our evaluation method, the backside pn junction that consists of n-well and p/p+ substrate is used as a hole injection source. Vth is measured in-between the stress within 10 s to minimize a recovery effect. In this experiment, on the fly measurement [27,28] was not employed. However, the circuit simulation results of frequency degradation in the ring oscillator using Vth shift and ID degradation from this measurement technology have agreed with experimental results, and its oscillation frequency is as high as 80 MHz. (shown in Fig.
Output Voltage [V]
1.60
1) [30,32,33]. Vth is measured by conventional gm-max method. The resolution of Vth shift is 0.1 mV using the gm-max method. Fig. 2a and b shows the schematic view and the energy band diagram during the stressing period of the hole injection method [29–33,36], respectively. The acceleration parameter is defined by the gate current density (Jinj) which is proportional to the amount of the non-energetic cold holes injected into the inversion layer during the stress [31]. And it is controlled by bias level of the backside pn junction. Additionally, the grounded n-well guarantees that the injected holes are not given any energy while diffusing from backside p+ substrate to the end of the depletion layer of the stressed device, thus only the rate of the degradation is accelerated by increased number of holes, but not energy of holes. Hole injection method has its limit in allowable injection amount [29– 33]. With the appropriate region, we can obtain the quantitative NBTI degradation behavior with no acceleration of the gate voltage and the temperature. In this acceleration method, the degradation mechanism is same as the operation condition, however, acceleration factor is about one order of magnitude which is still small [31]. Furthermore improvement is necessary for quality assurance about reliability. The current flows during the stress are taken into account to define the acceleration parameter in our system. Almost all the generated holes in pn junction recombine with electrons in the n-well region. A part of the injected holes reach the depletion layer. A small numbers of these holes are injected into the inversion layer. Summation of the injected hole density (Ninj) and the static inversion hole density (Ninv) is the effective inversion hole density. A
199-stage ring oscillaor NMOS: W/L=10.0/0.13[μm], PMOS:W/L=20.0/0.13[μm] measured initial waveform lines: Simulation measured waveform after 650 hours stress (stress VDD=2.0V @398K)
1.20
0.80
0.40
0.00 0.0
10.0
20.0
30.0
40.0
50.0
Time [nsec] Fig. 1. Circuit simulation results of frequency degradation in the ring oscillator using Vth shift and ID degradation from this measurement technology [30,32,33]. These have agreed with experimental results, and its oscillation frequency is as high as 80 MHz.
For monitoring Gate Current
A -VG
Hole Source N-Well
ID/S
ID/S
Isub
(grounded)
P-Sub st ra te
N+ n-Well
Hole Injection
pn junction
p+ IPN
hole injection
Forward bias ( VP N )
a
b
Fig. 2. Schematic view (a) and the energy band diagram (b) during the stressing period of the hole injection method.
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
principal acceleration parameter (A) is determined as follows in our system:
A¼
ðNinj þ Ninv Þ Ninv
ð3Þ
However, we cannot directly observe Ninj. Fortunately, the tunneling current (gate current) has a physical relationship with the hole density in the inversion layer since then we can estimate Ninj from the gate current via some mathematical calculation. We take the gate current density as the unique acceleration parameter in our system. The gate currents with and without the hole injection are required to calculate Ninj. The gate current is measured by a conventional carrier separation technique [37,38]. The carrier separation measurement is executed while the drain/source and well are biased at common. The backside pn junction is also biased at common. Fig. 3 displays the measured currents. The dominant component of the gate current is the hole current at the operation condition. Here, we define the physical parameter Qhole for degradation analysis. The definition of Qhole is as follows:
Q hole ¼ J inj tstress
ð4Þ
where Jinj and tstress are the gate current with the hole injection and stress time, respectively. 3. Results and discussion Fig. 4 shows the Vth shift of PMOSFETs with gate insulator of SiO2 and SiON as a function of a stress time in conventional NBTI
-6
10
abs( IG , IDS , I well ) [A]
I DS (hole current) IG I well
SiO 2
-7
10
-8
10
-9
10
-10
10
SiON
-11
10
-12
10
-13
10
Temp.=398[K]
-14
10
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Gate Voltage [V] Fig. 3. Charge separation results for p-MOSFETs having SiO2 and SiON gate insulator.
3
10
Vth Shift [mV]
SiON SiO2
EOT = 2.0 [nm] Stress VG=-2.0 [V] Temp. = 398 [K]
2
10
1
10
0
10 0 10
1
10
2
10
3
10
4
10
5
10
Stress Time [sec] Fig. 4. Vth shift of PMOSFETs with gate insulator of SiO2 and SiON as a function of a stress time in conventional NBTI stress. VG = 2.0 V and Temperature = 398 K.
1651
stress condition of VG = 2.0 V and temperature = 398 K. The slopes in Fig. 4 are 0.25 for both SiON and SiO2 films and the Vth shift for SiON is one order of magnitude larger than that for SiO2. It has been reported the NBTI in SiON films is much larger that in SiO2 films [8,18,21–23,26]. This result agrees with these previous results. Fig. 5 shows the Vth shift as functions of Jinj (a) and Qhole (b) which is calculated by Eq. (4). Stress time is 1000 s for all devices. The Vth shifts clearly consist of two regions, which are named as the low and the high injection region. In the low injection region, the Vth shift at a certain Jinj increases as the stress gate voltage is increased. However, this behavior is not observed in the high injection region, i.e. the Vth shifts in the high injection region do not show the stress gate voltage dependence. Fig. 5b contains the results of the samples stressed by the operation voltage and temperature condition with and without the hole injection, accompanied by the results of samples stressed by conventional high gate voltage. Firstly, the Vth shifts of samples stressed by low Jinj with the operation voltage (VG = 1.2 V) are same as the Vth shifts of samples stressed in the operation condition without the hole injection. This result confirms that the holes injection method, when low injection region is used, accelerates the degradation by mean of the stress time, but does not change the degradation mechanism or magnitude from that of the operation condition without injections. However, the Vth shifts of devices stressed by high stress voltage or by the high Jinj show the completely different behavior, i.e. the exponential slope is around 0.25 throughout the measurement and the shifts are independent on the stress voltage, like previously reported [7,10,13,20–25]. This result indicates that the dominant degradation mechanism is changed in these acceleration conditions from that of the operation condition. Thus, to develop the degradation model for the lifetime prediction and the circuit performance prediction, we must only use the degradation behavior of devices stressed by hole injection method in the low Jinj regime with operation bias and temperature condition among the experimented degradation acceleration methods [29–33]. Then, the hole acceleration method is applied to these PMOSFETs with SiO2 and SiON films instead of the conventional stress condition such as high gate voltage stress. Stress conditions are VG of 1.2 V, temperature of 398 K, and Jinj of 9.2 104 A/cm2 for SiON and 3.9 102 A/cm2 for SiO2, respectively. Fig. 6 shows the Vth shift as a function of a stress time in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection. The Vth shifts for SiON is about one order of magnitude larger than that for SiO2 for each stress. Fig. 7 shows the Vth shift as a function of Qhole, which is calculated from the stress time and Jinj using Eq. (4), in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection. The Vth shift differences between SiO2 and SiON for same stress conditions increase compared to VG shift-stress time characteristics shown in Fig. 6. The increase of the difference between Figs. 6 and 7 is caused by the Jinj difference for SiO2 and SiON in stress conditions, i.e. Jinj for SiON and SiO2 are 9.2 104 and 3.9 102 A/cm2, respectively. Then, the differences between SiO2 and SiON in Fig. 7 are larger than that in Fig. 6. This indicates that the Jinj in stress condition and operation condition is very important parameter for comparing of NBTI lifetime in different devices such as PMOSFET with different gate insulators. Fig. 3 also shows the measured currents of the gate (IG), drain/source (ID/S) and the substrate (ISUB) electrodes of the MOSFETs with the gate insulators of SiO2 and SiON as a function of the gate voltage. The gate currents with and without the hole injection are required to calculate Jinj. The gate current is measured by a conventional carrier separation technique [29–33,37,38]. The carrier separation measurement is executed while the drain/source and well are biased at common. At the operation bias point of 1.2 V, the Jinj0 which is hole current without additional hole injection and is measured as ID/S for SiO2 and SiON are 3.32 102 and 8.30 104 A/
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
101 Stresdssed @300K for 10 [sec]
Vth Shift [mV]
Vth Shift [mV]
101
100
10-1
VG=0.7V VG=1.2V VG=2.0V
10-2 10-2
10-1
100
101
100
10-1 VG=0.7V VG=1.2V VG=2.0V
10-2 10-2
102
102
Stresdssed @300K for 100 [sec]
Vth Shift [mV]
1652
10-1
100
101
Stresdssed @300K f or 1000 [sec]
101
100
VG=0.7V VG=1.2V VG=2.0V
10-1 10-2
102
10-1
100
101
102
Injection Current Density (Jinj) [A/cm 2]
Injection Current Density (Jinj) [A/cm 2]
Injection Current Density (Jinj) [A/cm 2]
(a) 10 sec
(b) 100sec
(c) 1000sec
Fig. 5. Vth shift as functions of Jinj for stress time of (a) 10, (b) 100, and (c) 1000 s.
Fig. 8. Fig. 8 shows the Vth shift as a function of the effective stress time. Although Jinj is different in stress time, the Vth shifts for same gate insulator and same gate voltage are the almost same. This means that the NBTI lifetime measurement can be accelerated by hole injection without changing the degradation mechanism and an accurate lifetime prediction can be realized. In this experiment, the NBTI lifetime of SiON is much less than that of SiO2. The lifetime can be predicted applying of the previously reported charge trapping induced Vth shift model [26,29–33] shown as Eq. (6) to Fig. 8:
2
Vth Shift [mV]
Temperature=398 [K]
10
10
1
Tox=2.0 [nm], SiO2
~1/4
L/W=10/10 [μm]
0
VG=-1.2 V, No Injection VG=-1.2 V, Low Jinj.=3.8x10 -2[A/cm2 ] VG=-1.2 V, High Jinj.=1.9x100[A/cm 2 ] VG=-1.8 V, NO Injection
-1
10 -1 10
10
0
10
1
10
2
10
3
10
4
10
5
DV th ¼
2
Qhole[C/cm ] Fig. 6. Vth shift as functions of Qhole. Stress time.
10 3
Vth Shift [mV]
10 2
SiON -1.2V , Jinj .=9.2x 10 -4 [A/c m 2 ] SiON -2V, No injection SiO 2 -1.2V , Jinj .=3.9x 10 -2 [A/c m 2 ] SiO 2 -2 .0 V, No injection
101
10 0 Temp. = 398 [K] EOT = 2.0 [nm] -1
10 0 10
1
10
10
2
10
3
10 4
10 5
10 6
Stress Time [sec] Fig. 7. Vth shift as a function of a stress time in NBTI measurement for VG of 2.0 V without hole injection and VG of 1.2 V with hole injection.
cm2, respectively. The Jinj at operation condition of SiO2 is about 40 times larger than that of SiON and this means that the NBTI lifetime for SiON is 40 times larger than that for SiO2 when the Vth shift–Qhole characteristics of both SiO2 and SiON are the same. However, the Vth shift–Qhole characteristics of different gate insulator films are actually different for almost all cases. Then, an effective stress time which is shown as Eq. (5) is introduced:
Effective Stress time ¼ Q hole =J inj0 ð@V G ¼ 1:2 V without hole injection from the backside pn junctionÞ
ð5Þ
It is possible to predict the NBTI lifetime by comparing between the actual Vth shift and criteria of the Vth shift at the device guaranteed time in Vth shift – Effective stress time characteristics as shown in
( ) q c Q hole b Dtrap-max 1 exp r C ox q
ð6Þ
where Dtrap-max, is the maximum trap density effectively active for a stress bias condition. r and b are the capture cross-section and the dispersion constant of trap sites, respectively. When the criterion of Vth shift is 100 mV, the lifetime of SiON are 6.55 106 s for hole injection method and 104 sec for conventional high gate voltage condition. On the other hand, the lifetimes of SiO2 are about 7 106 s (or the less) for conventional method and infinity compared to the 10 years because the Vth shift saturates in Fig. 8 and cannot reach 100 mV. It is noticed that the lifetimes measured by the hole injection stress for both gate insulators are larger than those measured by the conventional stress. Especially in SiO2, the lifetime measured by the conventional method cannot be guaranteed for 10 years, however, that measured by the hole injection method can be guaranteed. This fact is very important for device performance and reliability. We have already reported the ID reduction model and a circuit degradation using the Vth shift and ID reduction caused by NBT stress [30,32,33]. The following equation that shows the total ID reduction including the effect of both voltage overdrive and mobility reduction has been reported [30,32,33]:
Vth Shift [mV]
10
10
3
10
2
SiON-1.2V, Jinj.=9.2x10-4[A/cm 2 ] SiON-2.0V, No injection SiO2-1.2V, Jinj.=3.9x10 -2[A/cm 2 ] SiO2 -2.0V, No injection
1
10
10 0
Temp. = 398 [K] EOT = 2.0 [nm]
-1
10
10
-3
10
-2
10
-1
10
0
Q hole
1
10
10
2
10 3
10 4
10 5
[C/cm 2]
Fig. 8. Vth shift as a function of Qhole, which is calculated from the stress time and Jinj using Eq. (5).
A. Teramoto et al. / Microelectronics Reliability 48 (2008) 1649–1654
101
and by analyzing of relationship between ID reduction and Vth shift, accurate lifetime prediction for the ID reduction and the degradation prediction in circuit level are realized. These results are essential for accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.
100
Acknowledgements
Temp. = 398 [K] EOT = 2.0 [nm]
102
th
V shift [mV]
103
10-1 0 10
1
10
10
2
6.55x1 0 6[sec ]
10
3
10
4
10
5
10
6
10
7
10
8
EffectiveStress Time [sec] Fig. 9. Vth shift as a function of the effective stress time. Effective stress time = Qhole/ Jinj (@ VG = 1.2 V without hole injection from the backside pn junction).
10
The authors gratefully acknowledge Dr. Kazufumi Watanabe, Mr. Michihiko Mifuji and Mr. Takahisa Yamaha for their technical advices and useful discussions. This work was supported in part by the New Intelligence for IC Differentiation project (DIIN project) in Tohoku University. R. Kuroda would like to acknowledge Japan Society for the Promotion of Science Research Fellowship Program (No. 19 1356).
2
References
measured at VG=VD=-1.2 [V] Id sat degradation [%]
1653
1
10
θ=4.50x10-12 [cm2] 10
0
VGstress SiON, -2.0 V SiON, -1.32 V SiON, -1.2V No injection SiON, -1.2V hole injection
-1
10
10
0
1
10
10
2
10
3
Vth Shift [mV] Fig. 10. Relationship of ID reduction and Vth shift for SiON.
DIDsat a h C i =q DV th ½% ¼ 100 þ IDsat V G V th ð1 þ aDi Þ
ð7Þ
where l is carrier mobility and Ci is gate capacitance, a is the parameter that accounts for the carrier velocity saturation effect and is 2 for the long channel device and less for short channel device and h is the mobility reduction parameter indicating carrier screening cross section of the stress induced positive charge at and near the interface. Fig. 9 shows the relationship of ID reduction and Vth shift for SiON. The ID reduction is proportional to the Vth shift. This indicates that h can be defined one value for this PMOSFET, and the h value in this experiment is 4.50 1012 cm2, and this value is a little larger than the h value for SiO2 of 3.72 1012 cm2 which is reported in [30,32,33]. The h value is concerned with the fixed charges and interface states, which cause the mobility degradation. This suggests that the influence of introduction of nitrogen into gate insulator films on the carrier scattering. These results enable to predict the accurate lifetime for NBTI stress in circuit level [30,32,33] (see Fig. 10). 4. Conclusions We demonstrated that the NBTI measurement and lifetime prediction of PMOSFET with gate insulators of SiO2 and SiON based on the hole injection method. using the hole injection method, the NBTI lifetime of SiON is less than that of SiO2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By introduction of effective stress time (=Qhole/Jinj0), accurate lifetime prediction for the Vth shift is realized,
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