Characterization and modeling of power MOSFET switching times variations under constant electrical stress

Microelectronics Reliability 55 (2015) 492–497

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Characterization and modeling of power MOSFET switching times variations under constant electrical stress Hatice Gül Sezgin a, Yasin Özçelep b,⇑ a b

Electrical & Electronics Dept., Bartın University, Bartın, Turkey _ _ University, Istanbul, Turkey Electrical & Electronics Dept., Istanbul

a r t i c l e Article history: Received 9 October Received in revised Accepted 7 January Available online 23

i n f o

2014 form 7 January 2015 2015 January 2015

Keywords: Electrical stress Power MOSFET MOSFET switch Degradation modeling

a b s t r a c t In this paper, we proposed a simple and accurate degraded power MOSFET model for digital applications. The model provides to determine the electrical stress induced changes in power MOSFET switching characteristics. To establish the degraded power MOSFET and stress induced changes in switching parameters relation we consider the on-state-resistance of the power MOSFET as a voltage controlled resistor. We implemented a voltage non-linearly dependent resistor model in Pspice. We compared the experimental and simulation results to explore the model capability. Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction Due to good combination of fast switching and low on-resistance of power MOSFET devices, they are very fast switchers and widely used in the industry [1,2]. The switching times variations of power MOSFETs are still on the agenda from the reliability point of view because the gate oxide degradation effects the switching characteristics. The electrical stress changes the interface and oxide charges into the gate oxide and these charges cause degradation in power MOSFET’s parameters such as threshold voltage, mobility and terminal capacitances which alter the switching parameters [1–7]. Electrical stress induced degradation in power MOSFET characteristics have to be translated into the circuit performance because simulation of the circuit performance degradation is an important issue in design-for-reliability. An accurate circuit degradation simulation helps designer to predict circuit reliability in the early stages of process optimization [8,9]. In the study, we characterized the power MOSFET switching time variations under constant stress by the stress time and implemented a simple and accurate simulation model. For this purpose, we degraded power MOSFET under constant stress by time intervals. We obtained stress induced changes in power MOSFET’s characteristics such as threshold voltage, mobility and terminal ⇑ Corresponding author. E-mail addresses: [email protected] (H.G. Sezgin), [email protected] (Y. Özçelep). http://dx.doi.org/10.1016/j.microrel.2015.01.002 0026-2714/Ó 2015 Elsevier Ltd. All rights reserved.

capacitances. We set up a resistive load NMOS inverter to extract the switching times of power MOSFET. We implemented voltage controlled on-state-resistor (RON) model and embedded it into the power MOSFET switching model. We simulated the resistive load NMOS inverter with the implemented model. 2. Materials and methods In the study, we performed stress tests on the n-channel BS107A transistors produced by on Semiconductor. The current and voltage ratings are 250 mA and 200 V, respectively. The structure of the power MOSFET is vertical double-diffused MOSFET (VDMOSFET). We applied stress voltage from gate terminal of transistor at 55 V DC where the source and drain were grounded for six hours. We measured that the 55 V is short of breaking gate oxide suddenly and it breaks gate oxide when applied for approximately 6.5 h. We select constant voltage stress because the most products are assumed to operate at a constant stress under normal use and constant stress is easy to run. Furthermore; constant stress models could be verified with experiments [10,11]. We observed the power MOSFET parameters in time intervals 20 min, 30 min, 1 h, 2 h, 3 h, 4 h, 5 h, and 6 h until just prior to oxide breakdown. GWInstek GPC-30600 Dual Tracking is used for DC power supply. Output current and gate current are measured by Agilent 34405A 5½ Digit Multimeter and Agilent 34450A 5½ Digit Multimeter, respectively. We measured parasitic capacitances of power MOSFET by GWInstek LCR-8110G Precision LCR Meter. We

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Fig. 1. Resistive load NMOS inverter test circuit.

measured and recorded the ID–VDS, ID–VGS and terminal capacitance measurements in time intervals during the stress. Changes in the power MOSFET parameters were determined from measured transfer characteristics. We used the capacitance measurement circuits [12,13] and measured the changes in the input capacitance CISS, output capacitance COSS and reverse capacitance CRSS. We extracted the changes in CGS, CDS and CGD capacitances from the measured capacitances using Eqs. (1)–(3).

ð1Þ

C DS ¼ C OSS  C RSS

ð2Þ

C GD ¼ C RSS

ð3Þ

We set up a resistive load NMOS inverter circuit as shown in Fig. 1 to extract the power MOSFET switching times. We applied 100 kHz square wave as input signal, 1 kX resistor as load and 10 V DC supply voltage. 3. Switching model of power MOSFET There is no connection between the drain and the source when the power MOSFET is off (VGS < VTH). If the voltage VGS between the gate and source terminals is above VTH (VGS P VTH), the power MOSFET turns on and displays a resistance RON between its D and S terminals due to transistors are not ideal switches [14–16]. Fig. 2 shows the schematic representation of switching model of power MOSFET when the MOSFET is off (Fig. 2(a)) and on (Fig. 2(b)). The RON resistance can be formulated as in Eq. (4) [14,15]

1 bðV GS  V DS  V TH Þ

1 bðV GS  V TH Þ

4 3.5 3 2.5 2 1.5

0

90

180

270

360

Stress me (min.)

(b) 30

ð4Þ 20

Here; b is the process parameter. When the power MOSFET is on state (VGS P VTH), Eq. (4) can be represented in Eq. (5) assuming the VDS  VGS and VDS  VTH.

RON 

(a) 4.5

β(mA/V2)

RON ¼

Fig. 2. The switching model of the power MOSFET (a) MOSFET is off and (b) MOSFET is on [14].

Threshold Voltage (V)

C GS ¼ C ISS  C RSS

10

ð5Þ

As seen in Eq. (5), the RON resistance can be controlled with the voltage difference between the gate-to-source voltage and threshold voltage. 4. Stress induced changes in power MOSFET and NMOS inverter parameters In the section, we presented the experimental results of stress induced changes in power MOSFET and NMOS inverter parameters. Electrical stress induced changes in threshold voltage and process parameter b (lC ox WL ; here l is the mobility, Cox is the oxide

0

0

90

180

270

360

Stress me (min.) Fig. 3. Electrical stress induced change in threshold voltage (a) and b (b) of MOSFET.

capacitance, W and L are the channel width and length respectively) of power MOSFET are shown in Fig. 3(a) and (b), respectively. As shown in Fig. 3, electrical stress causes an increase in threshold voltage of the transistor while it causes decrease in the process parameter b during the stress time.

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80

RON(Ω Ω)

60

40

20

0

0

90

180

270

360

Stress me (min.) Fig. 4. Electrical stress induced change in power MOSFET RON resistance during stress time. Fig. 6. Electrical stress induced change in CGD capacitance of MOSFET during stress time.

Fig. 5. Electrical stress induced change in CGS capacitance of MOSFET during stress time.

Considering Eq. (5), stress induced change in VTH and b cause change in the RON. Fig. 4 shows that the RON resistance of power MOSFET increases during the stress time. Electrical stress induced change in terminal capacitances between gate and source-CGS, gate and drain-CGD, drain and source-CDS are extracted from the stress induced change in measurable capacitances CISS, COSS and CRSS using Eqs. (1)–(3). The terminal capacitance CGS is decreased with the stress voltage during the time as given in Fig. 5. Capacitances CGD and CDS are increased with the stress for early stress time and decreased after 3 h stress as shown in Figs. 6 and 7, respectively. We used the circuit in Fig. 1 to analyze the stress induced changes in dynamic response parameters of resistive load NMOS inverter and thus, stress induced changes in power MOSFET switching times variations. The input and output signals of NMOS inverter during the stress are shown in Fig. 8. It is seen that electrical stress causes changes in the output response. We investigated the tp (average propagation delay), ton (turnon) and toff (turn-off) of the power MOSFET. The tp, ton and toff are considered by some researchers before [17]. They include the other dynamic analysis parameters as tlh (voltage to change from 10% to 90% of its high value), thl (time required for the output voltage to change from 90% to 10% of its high value), tplh (propagation delay low-to-high), tphl (propagation delay high-to-low) and

Fig. 7. Electrical stress induced change in CDS capacitance of MOSFET during stress time.

Fig. 8. Dynamic response of resistive load NMOS inverter.

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495

1

Switching mes ( μs)

0.8

0.6

tp ton toff

0.4

0.2

0

0

90

180

270

360

Stress me (min.) Fig. 10. The RON resistance and controlling voltage relation.

Fig. 9. Dynamic response parameters of resistive load NMOS inverter.

located in datasheets, etc. Therefore, we have investigated tp, ton and toff in our study. We extracted tp using Eq. (6).

tp ¼

t PLH þ t PHL 2

ð6Þ

Here, tPLH is propagation delay from low-to-high between the 50% points of input and output signal and tPHL is propagation delay from high-to-low between the 50% points of input and output signal. The ton is between the low-to-high 10% points of input signal and high-to-low 10% points of output signal. The toff is between the high-to-low 90% points of input signal and low-to-high 90% points of output signal. Fig. 9 represents the changes in dynamic response parameters of inverter. The ton is increased and other parameters are decreased. Decreasing tp indicates that the power MOSFET is getting faster after the stress. Fig. 11. Implemented degraded power MOSFET model.

5. Modeling the degradation effects We experimentally determined the parasitic capacitances and RON resistance in switching model of power MOSFET in Fig. 2 is changed after the stress. We focused on the modeling of RON. We consider the RON resistance as a voltage controlled resistor. Controlling voltage VCON is the voltage difference between the VGS and VTH (VCON = VGS–VTH). The RON resistance and controlling voltage relation is given in Fig. 10. Marking the VGS–VTH as VCON. the relation in Fig. 10 is formulated as in Eq. (7).

RON ¼ 1:56  108 e2:5V CON: þ 66:33e0:28V CON:

ð7Þ

As seen in Eq. (7) RON is nonlinearly dependent to VCON.. We used nonlinear dependent source in Pspice to modeling the voltage dependent resistor originated from the linear dependent source [18,19] equivalents. A DC voltage source is inserted between CGS and ground in switching model of power MOSFET to form the VCON.. The DC voltage source represents the stress induced change in threshold voltage. The switching model of degraded MOSFET is shown in Fig. 11. In the model BR is the nonlinear voltage dependent voltage source. The VS is used for current sensing therefore set 0 V. The VTHR. is used for the threshold voltage shift in VCON.. The analytical model of the change in threshold voltage on stress time can be presented with a single function as high order polynomial. For simplicity, we presented a piecewise function as in Eq. (8).

Fig. 12. Inverter simulation circuit with switching model of degraded power MOSFET.

 V THR ¼

0:0073  t þ 1:7601 for t < 20 min 0:08559 lnðtÞ  1:0052 for t P 20 min

ð8Þ

The CGS is the gate–source capacitance, CGD is the gate-drain capacitance, CDS is the drain–source capacitance. Note that, for simulating voltage non-linearly dependent resistor separately a

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1.2

(a)

Experimental(toff) Simulaon(toff) Experimental(tp)

1

Simulaon(tp) Experimental(ton) Simulaon(ton)

toff;ton;tp(μ μs)

0.8 0.6 0.4 0.2 0

(b) 80

0

90

180

270

360

Stress me (min.)

RON (Ω Ω)

60

Fig. 15. tp, ton and toff experimental and simulation results with implemented model.

Experimental Simulaon

40

the stress time are represented. The experimental and simulated results are in a good agreement. The resistive load NMOS inverter in Fig. 1 is simulated using the implemented model in Fig. 12 with Pspice. The input voltage Vin swing is the 0–10 V, 100 kHz square wave as in experiments and Rin is set to 50 X in simulations. We used the experimental CGS and VTHR. values for any stress time to form VCON.. The simulated Vin–Vout curve is seen in Fig. 14. Fig. 14 presents the experimental and simulation results of resistor load NMOS inverter. We saw that our experimental and simulation results are close to each other. It shows that implemented model is performing well. We calculated the tp, ton and toff values from simulations and presented the experimental and simulation results in Fig. 15. The tp and toff results are in good agreement but ton results are not in acceptable limits. We produced a linear fitting function between the simulation and experimental results to fit the simulation results to experimental results as, in Eq. (9).

20

0

0

90

180

270

360

Stress me (min.) Fig. 13. RON simulation with nonlinear resistor model.

12

8

Vin, Vout (V)

Experimental-Vin Experimental-Vout Simulaon-Vin

y ¼ 0:78x  0:033

Simulaon-Vout

4

0

ð9Þ

Here, y represents the experimental result and x represents the simulation result. Fig. 16 presents the experimental and fitting results after the fitting process. 7

11

15

19

t ( μs)

0.3 Experimental

Fig. 14. Inverter simulation circuit with implemented model.

6. Simulations We firstly simulated the nonlinear resistor and compared the experimental results. In Fig. 13(a) stress induced change in RON with the VCON. and in Fig. 13(b) stress induced change in RON with

0.2

ton(μ μs)

current source from V 0S negative terminal to B0R positive terminal is needed. When MOSFET is on, the voltage on CGS is VCON., the voltage on CGD is approximately Vin and the voltage on CDS is approximately 0 V. We selected the corresponding values from Figs. 5–7 and used in simulations. The resistive load NMOS inverter for simulation is formed with the implemented degraded MOSFET model as in Fig. 12. Vin and Rin are the Thevenin equivalent of the input voltage source.

fit

0.1

0

0

90

180

270

Stress me (min.) Fig. 16. ton simulation results after fitting process.

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7. Conclusion In the study, we degraded the power MOSFET under constant electrical stress and determined the changes in switching characteristics. We proposed a simple and accurate degraded power MOSFET model for switching applications. We implemented voltage non-linearly controlled RON model for MOSFET on-state. We simulated the resistor model and find the simulation results close to experimental results. We embedded it into the power MOSFET switching model. We simulated the resistive load NMOS inverter with the implemented model and extracted the switching times of power MOSFET. The simulation and experimental results are in good agreement. The proposed degradation model helps designers to predict circuit reliability in early stages of process.

Acknowledgements The authors would like to thank Istanbul University Research Fund for this financial support. This work was partially supported by Istanbul University Research Fund with the project code 31768.

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