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A new constant-current technique for MOSFET parameter extraction
Solid-State Electronics 49 (2005) 351–356 www.elsevier.com/locate/sse
A new constant-current technique for MOSFET parameter extraction Chao-Yang Lu, James A. Cooper Jr.* School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035, USA Received 11 February 2004; received in revised form 31 July 2004; accepted 25 September 2004
The review of this paper was arranged by Prof. A. Zaslavsky
Abstract It is often of interest to extract MOSFET parameters such as channel mobility in situations where the source/drain resistances are not negligible and may be non-linear. We propose and demonstrate a new technique that avoids difficulties with non-linear source/ drain resistance by conducting all measurements under constant drain current conditions. Ó 2004 Elsevier Ltd. All rights reserved.
1. Introduction During last two decades, many methods had been developed for MOSFET parameter extraction. Methods for channel length extraction have been reviewed by Ng and Brews [1] and by Taur [2]. Threshold extraction techniques have recently been reviewed by Ortiz-Conde et al. [3]. In almost all of the mobility extraction techniques, the MOSFET is operated in the linear regime at low drain voltage, where the drain current can be expressed as I d ¼ leff C ox
W ðV g V t V s0 ÞV ds : Leff
ð1Þ
Here Id, leff, Cox, W, Leff, and Vt are the drain current, effective mobility, oxide capacitance per unit area, channel width, effective channel length, and threshold voltage, respectively. The effective channel length is simply the physical spacing between the n+ source and drain regions. The voltages Vg, Vs0, and Vds are defined in Fig. 1. Because terminal voltages differ from the internal voltages, it is necessary to account for the effect of series resistance Rs0 and Rd0. The channel resistance (CR) *
Corresponding author. Tel.: +1 765 494 3514. E-mail address: [email protected] (J.A. Cooper Jr.).
0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.09.002
technique [4,5] measures the total resistance of devices with different channel lengths to eliminate the effect of series resistance. In 1992, a shift and ratio (S&R) technique was reported [6]. In this method, the shifted ratio of the derivative of total resistance with respect to gate voltage between two devices with different channel lengths is taken, and based on this ratio, the threshold voltage, effective channel length, and series resistance are found. Both the CR and S&R methods rely on the correct measurement of total resistance on devices with different channel lengths. Since the resistance is the ratio of the applied drain-to-source voltage to the drain current, one has some freedom to choose the applied voltage, which is usually kept smaller than 50–100 mV to meet the uniform channel requirement of (1). However, extra care must be taken if the series resistance is not truly ohmic. For example, a MOSFET with un-annealed source and drain contacts has contact resistances that depend upon drain current, so it is necessary to hold the drain current constant while measuring devices with different channel lengths to produce a valid comparison. Wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have attracted attention recently due to their superior electrical and physical properties that make them especially well-suited for
352
C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356 Vg
Rs
-
Vs0
-
be shown below). We define the sheet conductance of the channel as
Id
Vds
+
+
Rd
-
Vd0
Gch ðV g Þ ¼ I d =ðWEeff Þ ¼ C ox leff ðV g V t V s0 Þ,
Vds
+
Fig. 1. Definition of potentials within the MOSFET.
high-temperature, high-power, and high-frequency applications. In these semiconductors it is often desirable to measure channel mobility before and after contact anneal, so as to evaluate the impact of contact annealing conditions on the mobility. Even after a contact anneal, the source and drain contacts can still be non-linear due to poor annealing procedures. The source and drain resistances may also depend upon gate voltage, due to the overlap between gate and source/drain regions in non-self-aligned MOSFETs. A better way to measure such devices (having non-linear contacts that may depend on gate voltage) is to hold the drain current constant during measurement. In this paper we introduce a new constant drain current technique that eliminates errors due to source/drain resistances that are non-linear or depend upon gate voltage.
2. Theory of the technique For a long-channel device operated at a sufficiently small drain voltage, the drain current is given by (1), and can be written V ds L ¼ leff C ox W ðV g V t V s0 ÞEeff ,
ð3Þ
where the effective mobility leff is a function of gate voltage. The threshold voltage can be defined by the intersection of the abscissa and the linear portion of the Gch(Vg) vs. Vg curve. The intersection is actually a combination of the true transistor threshold voltage Vt, and the source voltage drop Vs0. If Rs is small, Vs0 is negligible. If Rs is not small, we can use a small Id and make Vs0 negligible. Once the threshold voltage is known, the effective mobility leff is obtained from (3), leff ðV g Þ ¼ I d =½C ox W ðV g V t ÞEeff ¼ Gch =C ox ðV g V t Þ,
ð4Þ
where we assume Id is small enough that Vs0 can be neglected. The field-effect mobility lfe can be calculated from the slope of the Gch vs. Vg plot, lfe ðV g Þ ¼
oGch ðV g Þ=oV g : C ox
ð5Þ
We should point out that (5) does not neglect the dependence of dVs0/dVg. In fact, Vs0 is constant during the measurement, because we use a constant drain current. This ensures a clean definition of the field effect mobility. In the next section we illustrate this method by using it to measure inversion layer mobility on SiC MOSFETs with un-annealed source/drain contacts.
3. Experiment
I d ¼ leff C ox W ðV g V t V s0 Þ
ð2Þ
where leff, the effective mobility, is a function of gate voltage, and Eeff = Vds/L is the tangential electric field in the channel. L is the designed separation between source and drain regions on the mask. We use L instead of Leff here, since we are assuming a long-channel device. For a given pair of (Id, Vg), we measure the terminal source–drain voltage V 0ds for devices with different channel lengths. In (2), all parameters are constant except Vds and L, and a plot of V 0ds vs. L can be generated. This plot is analogous to the total resistance vs. L plot in the traditional constant-drain–voltage method, except in our case it is the drain current that is held constant. On each plot of V 0ds vs. L, we determine the tangential electric field in the channel Eeff by extracting the slope dV 0ds =dL, and we determine the voltage drop across the source and drain contacts by calculating the voltage intercept at zero effective channel length. Zero effective channel length is determined by the intercept of regression lines of dV 0ds vs. L at different gate biases (as will
To illustrate the technique, we now describe a set of measurements on n-channel 4H–SiC MOSFETs with un-annealed nickel source/drain contacts. These devices are from sample W of Refs. [7,8]. As described therein, these MOSFETs are thermally oxidized in a pyrogenic system at 1150 °C, followed by an in situ Ar anneal at 1150 °C, a 950 °C re-oxidation anneal in wet O2, and an 1175 °C post-oxidation anneal in nitric oxide (NO). All transistors are identical except for their channel length, which takes on values of 50, 80, 110, and 140 lm. All devices are 110 lm wide, and the source/ gate and source/drain overlap are 5 lm. Three drain currents, 10, 50, and 90 nA, are used in the measurement. For a given (Id, Vg) pair, we measure the V 0ds for at least five devices of each channel length, and take the average of V 0ds . A typical plot is shown in Fig. 2a. The intercept of a least squares regression line at zero effective channel length defines the voltage drop across the series resistances, and the slope is used to determine Eeff. The linearity of the data can be judged by the correlation coefficient of four (V 0ds , L) pairs, as
C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356
353
Fig. 4. Channel conductivity of sample W as a function of gate voltage for drain currents of 10, 50, and 90 nA.
Fig. 2. (a) Drain voltage vs. channel length for a 110 lm wide MOSFET on sample W of Refs. [7,8] measured with a drain current of 90 nA and a gate voltage of 20 V. (b) Drain voltage vs. channel length measured with a drain current of 90 nA and gate voltages of 12, 14, 16, and 18 V. The intersection of the four curves defines the point where the effective channel length is zero. This region is shown in more detail in the inset.
The channel conductance calculated from (3) is shown in Fig. 4. The threshold voltage can be obtained from the intercept of a linear fit to these curves at zero channel conductance, and is approximately 0.9 V for these devices. Once the threshold voltage is known, the effective mobility can be readily obtained using (4). Fig. 5 shows the field-effect mobility determined from (5) for three different drain currents. As seen, data obtained at the lowest drain current, 10 nA, is noisy, but still agrees qualitatively with data at higher drain currents. Fig. 6 shows the voltage drop across the source/ drain series resistances. The series resistance can be calculated independently from each curve, and is approximately 4.5 kX at high gate voltages for all three curves. Even though the series resistance is small, the voltage drop across the source and drain resistances in these devices cannot be neglected compared to the total source–drain voltage shown in Fig. 2. Fig. 7 shows the tangential field in the channel during these measurements. This field is extremely small, insuring that we
Fig. 3. Correlation coefficient of the drain current vs. channel length data (c.f. Fig. 2) as a function of gate voltage, for three different drain currents. The correlation coefficients are approximately 0.999 for gate voltages more than a few volts above threshold.
shown in Fig. 3. As seen, the correlation coefficient is around 0.999 for gate voltages more than a few volts above threshold.
Fig. 5. Field-effect mobility of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
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C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356 40 Constant Current Technique ID = 50 and 90 nA
Mobility (cm 2 /Vs)
35 30 25 20 15 10
Constant Voltage Technique (5 Devices)
5 0 0
5
(a) Fig. 6. Voltage drop across the series resistance of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
10
15
20
15
20
Gate Voltage (V) 40
Constant Current Technique ID = 50 and 90 nA
Mobility (cm 2/Vs)
35 30 25 20
Constant Voltage Technique (3 Devices)
15 10 5 0 0
(b)
5
10
Gate Voltage (V)
Fig. 8. Mobility on sample B of Refs. [7,8] (a) before contact anneal, and (b) after contact anneal, obtained using the constant-current technique (upper curves in each figure) and the constant-voltage technique (lower curves in each figure). Fig. 7. Tangential electric field in the channel of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
are well within the linear portion of the MOSFET I–V characteristic. To demonstrate the utility of the technique, we compare mobility measurements on the same device obtained from the new constant-current technique and the conventional constant-voltage technique. Fig. 8a shows mobility obtained on a SiC MOSFET with un-annealed source/drain contacts (sample B of Refs. [7,8]) using the two techniques. The mobility from the constant-voltage technique is extremely low due the high source/drain series resistance. Fig. 8b shows mobility on the same MOSFET from the two techniques after the source/drain contacts are annealed. The mobility from the constant-current technique is virtually identical to that in Fig. 8a, while the mobility from the constantvoltage technique is now very close to that from the constant-current technique. The dramatic increase in mobility from the constant-voltage technique occurs because the source/drain resistances are reduced by the
contact anneal. The fact that the channel mobility from the constant-current technique is virtually unchanged by the contact anneal is evidence that the correct mobility is obtained even in the presence of high, and possibly nonlinear, source/drain resistances, Fig. 8a.
4. Discussion Fig. 2b shows V 0ds vs. gate length curves at several gate biases. If all the regression lines intersect at the same point, the value of the channel length at that point is the channel length bias DL, defined as Lmask Leff, where Lmask and Leff are channel length on the mask and the effective channel length, respectively. In this case, DL = 2.6 lm. The negative value of DL implies that the effective channel length Leff is longer than the mask length Lmask. As is the case with all other channel resistance techniques, the effective channel length Leff is only well-defined when the source/drain resistance is not a function of Vg. Therefore, it is necessary to find a range where the voltage drop across the series resistance is not Vg dependent. For Id = 90 nA, this range is Vg > 6 V, as we will show later.
C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356
The high correlation coefficients (about 0.999) in Fig. 3 justify the linearity of the slope-based method. The curves associated with larger drain currents have better linearity close to threshold because the surface leakage currents are relatively less significant, and they are less noisy at high gate bias because the gate leakage is less significant. Therefore drain currents above 50 nA are preferred. However, the drain current should always be kept low enough to meet the uniform channel assumption. In Figs. 4 and 5, despite the deviation of the 10 nA curves, the conductivities and field-effect mobilities obtained from all drain currents are consistent. If compared to a conventional plot of Id vs. Vg, Fig. 4 exhibits a more extensive linear portion and a sharper turn-on characteristic, because the effect of series resistance is eliminated. Fig. 6 shows the voltage drop across the series resistances as a function of gate voltage for three drain currents. These voltage drops are measured at the intersections of the regression lines in plots like Fig. 2b, i.e. they represent the drain voltages that would be observed at zero effective channel length. The plot in Fig. 6 can be used to determine the series resistance due to the source/ drain regions and source/drain ohmic contacts. We note that the voltage drop across the series resistance in these devices increases as the gate bias decreases. We believe this is due to gate modulation of the source/drain resistance under the 5 lm gate/source and gate/drain overlap regions. Note that in a SiC MOSFET, the n+ source and drain implants must be annealed at a temperature above the melting point of the polysilicon gate, preventing us from using the gate as an implant mask and precluding a ‘‘self-aligned gate’’ process. Since the gate must be formed after the source–drain implant, it must overlap the source and drain regions by an alignment tolerance, and the gate voltage can then modulate the source–drain resistance by forming an accumulation layer on the surface. The plot in Fig. 6 is also used to determine the gate voltage dependence of the series resistance. The effective channel length Leff obtained in Fig. 2b is only well-defined in the regime where the voltage drop across series resistance is independent of Vg, for example, Vg > 6 V at Id = 90 nA. The effective mobility is often assumed to have the form leff = l0/[1 + h(Vg Vt)] [9,10]. Using this assumption, as shown in Appendix A, we may differentiate (2) with respect to gate voltage to obtain
355
Fig. 9. A plot of Eq. (6) as applied to the experimental devices of Fig. 8b. The linear dependence predicted by (6) is evident. The intersection with the abscissa determines Vt. Fitting to the curves for Vg > 6 V, where the series resistance is independent of Vg, projects a threshold voltage close to zero, consistent with Fig. 8b.
plot is shown in Fig. 9. Fitting to the curves in the range Vg > 6 V, where the source resistance is independent of Vg, gives a threshold voltage very close to zero, consistent with Fig. 8b. However, the parameter h still must be determined by analyzing several devices with different channel lengths.
5. Conclusions A new MOSFET parameter extraction method, the constant current technique, is proposed and experimentally demonstrated. The method is especially useful for devices with non-linear source/drain resistances, or in situations where the source/drain resistance is a function of gate bias.
Acknowledgment This work was supported by the Office of Naval Research under grant no. N00014-01-1-0072.
Appendix A. Derivation of Eq. (6)
ð6Þ
Differentiating (2) with respect to gate voltage with Id constant yields oI d 1 oleff 1 1 oV ds þ ¼0¼ þ I d : ðA:1Þ leff oV g ðV g V t Þ V ds oV g oV g
If the left side of (6) is plotted vs. gate voltage and the data fit to a straight line, the intersection at Id = 0 gives the threshold voltage, and the slope determines l0. This
The internal drain-to-source voltage V ds ¼ V 0ds I d Rt , where V 0ds is the terminal drain-to-source voltage and Rt = Rs + Rd. If Rt is independent of Vg, (A.1) can be written
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Id W 0 ¼ l0 C ox ðV g V t Þ: L oV ds =oV g
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C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356
oI d ¼0 oV g 1 oleff 1 1 oV 0ds þ þ I d: ¼ leff oV g ðV g V t Þ ðV 0ds I d Rt Þ oV g ðA:2Þ Since the drain current is not zero, the pre-factor on the right side of (A.2) must be zero. Substituting 1 oleff h ¼ leff oV g 1 þ hðV g V t Þ
ðA:3Þ
into (A.2) yields 0¼
h 1 1 oV 0ds þ þ 0 : 1 þ hðV g V t Þ ðV g V t Þ ðV ds I d Rt Þ oV g ðA:4Þ
After some manipulation, we can write oV 0 V 0ds I d Rt ¼ 1 þ hðV g V t Þ ðV g V t Þ ds : oV g
ðA:5Þ
Substituting (A.5) into (2) and expressing leff = l0/ [1 + h(Vg Vt)] yields I d ¼ l0 C ox
W oV 0 ðV g V t Þ2 ds , L oV g
which leads directly to (6).
ðA:6Þ
References [1] Ng KK, Brews JR. Measuring the effective channel length of MOSFETs. IEEE Circ Dev Mag 1990;6:33–8. [2] Taur Y. MOSFET channel length: extraction and interpretation. IEEE Trans Electron Dev 2000;47:160–70. [3] Ortiz-Conde A, Garcia Sanchez FJ, Liou JJ, Cerdeira A, Estrada M, Yue Y. A review of recent MOSFET threshold voltage extraction methods. Microelectron Reliab 2002;42:583–96. [4] Chern JGJ, Chang P, Motta RF, Godinho N. A new method to determine MOSFET channel length. IEEE Electron Dev Lett 1980;EDL-1:170–3. [5] Terada K, Muta H. A new method to determine effective MOSFET channel length. Jap J Appl Phys 1979;18:953–9. [6] Taur Y, Zicherman DS, Lombardi DR, Restle PJ, Hsu CH, Nanafi HI, et al. A new Ôshift and ratioÕ method for MOSFET channel-length extraction. IEEE Electron Dev Lett 1992;13:267–9. [7] Lu C-Y, Cooper Jr JA, Chung GY, Williams JR, McDonald K, Feldman LC. Effect of process variations on 4H silicon carbide n-channel MOSFET mobilities. Mater Sci Forum 2002;389– 393:977–80, [The sample used in the present study is sample W, measured before ohmic contact anneal.]. [8] Lu C-Y, Cooper Jr JA, Tsuji T, Chung G, Williams JR, McDonald K, et al. Effect of process variations and ambient temperature on electron mobility at the SiO2/4H–SiC interface. IEEE Trans Electron Dev 2003;50:1582–8, [The sample used in the present study is sample W, measured before ohmic contact anneal.]. [9] Ghibaudo G. New method for the extraction of MOSFET parameters. Electron Lett 1988;24:543–5. [10] Fikry W, Ghibaudo G, Haddara H, Cristoloveanu S, Dutoit M. Method for extracting deep submicrometre MOSFET parameters. Electron Lett 1995;31:762–4.
A new constant-current technique for MOSFET parameter extraction Chao-Yang Lu, James A. Cooper Jr.* School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035, USA Received 11 February 2004; received in revised form 31 July 2004; accepted 25 September 2004
The review of this paper was arranged by Prof. A. Zaslavsky
Abstract It is often of interest to extract MOSFET parameters such as channel mobility in situations where the source/drain resistances are not negligible and may be non-linear. We propose and demonstrate a new technique that avoids difficulties with non-linear source/ drain resistance by conducting all measurements under constant drain current conditions. Ó 2004 Elsevier Ltd. All rights reserved.
1. Introduction During last two decades, many methods had been developed for MOSFET parameter extraction. Methods for channel length extraction have been reviewed by Ng and Brews [1] and by Taur [2]. Threshold extraction techniques have recently been reviewed by Ortiz-Conde et al. [3]. In almost all of the mobility extraction techniques, the MOSFET is operated in the linear regime at low drain voltage, where the drain current can be expressed as I d ¼ leff C ox
W ðV g V t V s0 ÞV ds : Leff
ð1Þ
Here Id, leff, Cox, W, Leff, and Vt are the drain current, effective mobility, oxide capacitance per unit area, channel width, effective channel length, and threshold voltage, respectively. The effective channel length is simply the physical spacing between the n+ source and drain regions. The voltages Vg, Vs0, and Vds are defined in Fig. 1. Because terminal voltages differ from the internal voltages, it is necessary to account for the effect of series resistance Rs0 and Rd0. The channel resistance (CR) *
Corresponding author. Tel.: +1 765 494 3514. E-mail address: [email protected] (J.A. Cooper Jr.).
0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.09.002
technique [4,5] measures the total resistance of devices with different channel lengths to eliminate the effect of series resistance. In 1992, a shift and ratio (S&R) technique was reported [6]. In this method, the shifted ratio of the derivative of total resistance with respect to gate voltage between two devices with different channel lengths is taken, and based on this ratio, the threshold voltage, effective channel length, and series resistance are found. Both the CR and S&R methods rely on the correct measurement of total resistance on devices with different channel lengths. Since the resistance is the ratio of the applied drain-to-source voltage to the drain current, one has some freedom to choose the applied voltage, which is usually kept smaller than 50–100 mV to meet the uniform channel requirement of (1). However, extra care must be taken if the series resistance is not truly ohmic. For example, a MOSFET with un-annealed source and drain contacts has contact resistances that depend upon drain current, so it is necessary to hold the drain current constant while measuring devices with different channel lengths to produce a valid comparison. Wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have attracted attention recently due to their superior electrical and physical properties that make them especially well-suited for
352
C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356 Vg
Rs
-
Vs0
-
be shown below). We define the sheet conductance of the channel as
Id
Vds
+
+
Rd
-
Vd0
Gch ðV g Þ ¼ I d =ðWEeff Þ ¼ C ox leff ðV g V t V s0 Þ,
Vds
+
Fig. 1. Definition of potentials within the MOSFET.
high-temperature, high-power, and high-frequency applications. In these semiconductors it is often desirable to measure channel mobility before and after contact anneal, so as to evaluate the impact of contact annealing conditions on the mobility. Even after a contact anneal, the source and drain contacts can still be non-linear due to poor annealing procedures. The source and drain resistances may also depend upon gate voltage, due to the overlap between gate and source/drain regions in non-self-aligned MOSFETs. A better way to measure such devices (having non-linear contacts that may depend on gate voltage) is to hold the drain current constant during measurement. In this paper we introduce a new constant drain current technique that eliminates errors due to source/drain resistances that are non-linear or depend upon gate voltage.
2. Theory of the technique For a long-channel device operated at a sufficiently small drain voltage, the drain current is given by (1), and can be written V ds L ¼ leff C ox W ðV g V t V s0 ÞEeff ,
ð3Þ
where the effective mobility leff is a function of gate voltage. The threshold voltage can be defined by the intersection of the abscissa and the linear portion of the Gch(Vg) vs. Vg curve. The intersection is actually a combination of the true transistor threshold voltage Vt, and the source voltage drop Vs0. If Rs is small, Vs0 is negligible. If Rs is not small, we can use a small Id and make Vs0 negligible. Once the threshold voltage is known, the effective mobility leff is obtained from (3), leff ðV g Þ ¼ I d =½C ox W ðV g V t ÞEeff ¼ Gch =C ox ðV g V t Þ,
ð4Þ
where we assume Id is small enough that Vs0 can be neglected. The field-effect mobility lfe can be calculated from the slope of the Gch vs. Vg plot, lfe ðV g Þ ¼
oGch ðV g Þ=oV g : C ox
ð5Þ
We should point out that (5) does not neglect the dependence of dVs0/dVg. In fact, Vs0 is constant during the measurement, because we use a constant drain current. This ensures a clean definition of the field effect mobility. In the next section we illustrate this method by using it to measure inversion layer mobility on SiC MOSFETs with un-annealed source/drain contacts.
3. Experiment
I d ¼ leff C ox W ðV g V t V s0 Þ
ð2Þ
where leff, the effective mobility, is a function of gate voltage, and Eeff = Vds/L is the tangential electric field in the channel. L is the designed separation between source and drain regions on the mask. We use L instead of Leff here, since we are assuming a long-channel device. For a given pair of (Id, Vg), we measure the terminal source–drain voltage V 0ds for devices with different channel lengths. In (2), all parameters are constant except Vds and L, and a plot of V 0ds vs. L can be generated. This plot is analogous to the total resistance vs. L plot in the traditional constant-drain–voltage method, except in our case it is the drain current that is held constant. On each plot of V 0ds vs. L, we determine the tangential electric field in the channel Eeff by extracting the slope dV 0ds =dL, and we determine the voltage drop across the source and drain contacts by calculating the voltage intercept at zero effective channel length. Zero effective channel length is determined by the intercept of regression lines of dV 0ds vs. L at different gate biases (as will
To illustrate the technique, we now describe a set of measurements on n-channel 4H–SiC MOSFETs with un-annealed nickel source/drain contacts. These devices are from sample W of Refs. [7,8]. As described therein, these MOSFETs are thermally oxidized in a pyrogenic system at 1150 °C, followed by an in situ Ar anneal at 1150 °C, a 950 °C re-oxidation anneal in wet O2, and an 1175 °C post-oxidation anneal in nitric oxide (NO). All transistors are identical except for their channel length, which takes on values of 50, 80, 110, and 140 lm. All devices are 110 lm wide, and the source/ gate and source/drain overlap are 5 lm. Three drain currents, 10, 50, and 90 nA, are used in the measurement. For a given (Id, Vg) pair, we measure the V 0ds for at least five devices of each channel length, and take the average of V 0ds . A typical plot is shown in Fig. 2a. The intercept of a least squares regression line at zero effective channel length defines the voltage drop across the series resistances, and the slope is used to determine Eeff. The linearity of the data can be judged by the correlation coefficient of four (V 0ds , L) pairs, as
C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356
353
Fig. 4. Channel conductivity of sample W as a function of gate voltage for drain currents of 10, 50, and 90 nA.
Fig. 2. (a) Drain voltage vs. channel length for a 110 lm wide MOSFET on sample W of Refs. [7,8] measured with a drain current of 90 nA and a gate voltage of 20 V. (b) Drain voltage vs. channel length measured with a drain current of 90 nA and gate voltages of 12, 14, 16, and 18 V. The intersection of the four curves defines the point where the effective channel length is zero. This region is shown in more detail in the inset.
The channel conductance calculated from (3) is shown in Fig. 4. The threshold voltage can be obtained from the intercept of a linear fit to these curves at zero channel conductance, and is approximately 0.9 V for these devices. Once the threshold voltage is known, the effective mobility can be readily obtained using (4). Fig. 5 shows the field-effect mobility determined from (5) for three different drain currents. As seen, data obtained at the lowest drain current, 10 nA, is noisy, but still agrees qualitatively with data at higher drain currents. Fig. 6 shows the voltage drop across the source/ drain series resistances. The series resistance can be calculated independently from each curve, and is approximately 4.5 kX at high gate voltages for all three curves. Even though the series resistance is small, the voltage drop across the source and drain resistances in these devices cannot be neglected compared to the total source–drain voltage shown in Fig. 2. Fig. 7 shows the tangential field in the channel during these measurements. This field is extremely small, insuring that we
Fig. 3. Correlation coefficient of the drain current vs. channel length data (c.f. Fig. 2) as a function of gate voltage, for three different drain currents. The correlation coefficients are approximately 0.999 for gate voltages more than a few volts above threshold.
shown in Fig. 3. As seen, the correlation coefficient is around 0.999 for gate voltages more than a few volts above threshold.
Fig. 5. Field-effect mobility of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
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C.-Y. Lu, J.A. Cooper Jr. / Solid-State Electronics 49 (2005) 351–356 40 Constant Current Technique ID = 50 and 90 nA
Mobility (cm 2 /Vs)
35 30 25 20 15 10
Constant Voltage Technique (5 Devices)
5 0 0
5
(a) Fig. 6. Voltage drop across the series resistance of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
10
15
20
15
20
Gate Voltage (V) 40
Constant Current Technique ID = 50 and 90 nA
Mobility (cm 2/Vs)
35 30 25 20
Constant Voltage Technique (3 Devices)
15 10 5 0 0
(b)
5
10
Gate Voltage (V)
Fig. 8. Mobility on sample B of Refs. [7,8] (a) before contact anneal, and (b) after contact anneal, obtained using the constant-current technique (upper curves in each figure) and the constant-voltage technique (lower curves in each figure). Fig. 7. Tangential electric field in the channel of sample W as a function of gate voltage, measured at drain currents of 10, 50, and 90 nA.
are well within the linear portion of the MOSFET I–V characteristic. To demonstrate the utility of the technique, we compare mobility measurements on the same device obtained from the new constant-current technique and the conventional constant-voltage technique. Fig. 8a shows mobility obtained on a SiC MOSFET with un-annealed source/drain contacts (sample B of Refs. [7,8]) using the two techniques. The mobility from the constant-voltage technique is extremely low due the high source/drain series resistance. Fig. 8b shows mobility on the same MOSFET from the two techniques after the source/drain contacts are annealed. The mobility from the constant-current technique is virtually identical to that in Fig. 8a, while the mobility from the constantvoltage technique is now very close to that from the constant-current technique. The dramatic increase in mobility from the constant-voltage technique occurs because the source/drain resistances are reduced by the
contact anneal. The fact that the channel mobility from the constant-current technique is virtually unchanged by the contact anneal is evidence that the correct mobility is obtained even in the presence of high, and possibly nonlinear, source/drain resistances, Fig. 8a.
4. Discussion Fig. 2b shows V 0ds vs. gate length curves at several gate biases. If all the regression lines intersect at the same point, the value of the channel length at that point is the channel length bias DL, defined as Lmask Leff, where Lmask and Leff are channel length on the mask and the effective channel length, respectively. In this case, DL = 2.6 lm. The negative value of DL implies that the effective channel length Leff is longer than the mask length Lmask. As is the case with all other channel resistance techniques, the effective channel length Leff is only well-defined when the source/drain resistance is not a function of Vg. Therefore, it is necessary to find a range where the voltage drop across the series resistance is not Vg dependent. For Id = 90 nA, this range is Vg > 6 V, as we will show later.
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The high correlation coefficients (about 0.999) in Fig. 3 justify the linearity of the slope-based method. The curves associated with larger drain currents have better linearity close to threshold because the surface leakage currents are relatively less significant, and they are less noisy at high gate bias because the gate leakage is less significant. Therefore drain currents above 50 nA are preferred. However, the drain current should always be kept low enough to meet the uniform channel assumption. In Figs. 4 and 5, despite the deviation of the 10 nA curves, the conductivities and field-effect mobilities obtained from all drain currents are consistent. If compared to a conventional plot of Id vs. Vg, Fig. 4 exhibits a more extensive linear portion and a sharper turn-on characteristic, because the effect of series resistance is eliminated. Fig. 6 shows the voltage drop across the series resistances as a function of gate voltage for three drain currents. These voltage drops are measured at the intersections of the regression lines in plots like Fig. 2b, i.e. they represent the drain voltages that would be observed at zero effective channel length. The plot in Fig. 6 can be used to determine the series resistance due to the source/ drain regions and source/drain ohmic contacts. We note that the voltage drop across the series resistance in these devices increases as the gate bias decreases. We believe this is due to gate modulation of the source/drain resistance under the 5 lm gate/source and gate/drain overlap regions. Note that in a SiC MOSFET, the n+ source and drain implants must be annealed at a temperature above the melting point of the polysilicon gate, preventing us from using the gate as an implant mask and precluding a ‘‘self-aligned gate’’ process. Since the gate must be formed after the source–drain implant, it must overlap the source and drain regions by an alignment tolerance, and the gate voltage can then modulate the source–drain resistance by forming an accumulation layer on the surface. The plot in Fig. 6 is also used to determine the gate voltage dependence of the series resistance. The effective channel length Leff obtained in Fig. 2b is only well-defined in the regime where the voltage drop across series resistance is independent of Vg, for example, Vg > 6 V at Id = 90 nA. The effective mobility is often assumed to have the form leff = l0/[1 + h(Vg Vt)] [9,10]. Using this assumption, as shown in Appendix A, we may differentiate (2) with respect to gate voltage to obtain
355
Fig. 9. A plot of Eq. (6) as applied to the experimental devices of Fig. 8b. The linear dependence predicted by (6) is evident. The intersection with the abscissa determines Vt. Fitting to the curves for Vg > 6 V, where the series resistance is independent of Vg, projects a threshold voltage close to zero, consistent with Fig. 8b.
plot is shown in Fig. 9. Fitting to the curves in the range Vg > 6 V, where the source resistance is independent of Vg, gives a threshold voltage very close to zero, consistent with Fig. 8b. However, the parameter h still must be determined by analyzing several devices with different channel lengths.
5. Conclusions A new MOSFET parameter extraction method, the constant current technique, is proposed and experimentally demonstrated. The method is especially useful for devices with non-linear source/drain resistances, or in situations where the source/drain resistance is a function of gate bias.
Acknowledgment This work was supported by the Office of Naval Research under grant no. N00014-01-1-0072.
Appendix A. Derivation of Eq. (6)
ð6Þ
Differentiating (2) with respect to gate voltage with Id constant yields oI d 1 oleff 1 1 oV ds þ ¼0¼ þ I d : ðA:1Þ leff oV g ðV g V t Þ V ds oV g oV g
If the left side of (6) is plotted vs. gate voltage and the data fit to a straight line, the intersection at Id = 0 gives the threshold voltage, and the slope determines l0. This
The internal drain-to-source voltage V ds ¼ V 0ds I d Rt , where V 0ds is the terminal drain-to-source voltage and Rt = Rs + Rd. If Rt is independent of Vg, (A.1) can be written
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Id W 0 ¼ l0 C ox ðV g V t Þ: L oV ds =oV g
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oI d ¼0 oV g 1 oleff 1 1 oV 0ds þ þ I d: ¼ leff oV g ðV g V t Þ ðV 0ds I d Rt Þ oV g ðA:2Þ Since the drain current is not zero, the pre-factor on the right side of (A.2) must be zero. Substituting 1 oleff h ¼ leff oV g 1 þ hðV g V t Þ
ðA:3Þ
into (A.2) yields 0¼
h 1 1 oV 0ds þ þ 0 : 1 þ hðV g V t Þ ðV g V t Þ ðV ds I d Rt Þ oV g ðA:4Þ
After some manipulation, we can write oV 0 V 0ds I d Rt ¼ 1 þ hðV g V t Þ ðV g V t Þ ds : oV g
ðA:5Þ
Substituting (A.5) into (2) and expressing leff = l0/ [1 + h(Vg Vt)] yields I d ¼ l0 C ox
W oV 0 ðV g V t Þ2 ds , L oV g
which leads directly to (6).
ðA:6Þ
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