- Email: [email protected]
A new drain current model for short-channel MOSFETs
Microelectronics Reliability 43 (2003) 333–338 www.elsevier.com/locate/microrel
Research Note
A new drain current model for short-channel MOSFETs Sadegh Abbasian, Ebrahim Farjah
*
Department of Electrical and Electronics Engineering, Shiraz University, Engineering Building 1, Zand Avenue, Shiraz 7134851154, Iran Received 25 April 2002; received in revised form 26 August 2002
Abstract Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction For a MOS transistor operating in saturation mode, the electric field near the drain region which is often called as the velocity saturation region or the pinch-off region, increases significantly and causes impact ionization. The generated electrons (for the case of nchannel MOSFET) are swept into the drain and enhance the drain current significantly whereas the holes flow into the substrate (see Fig. 1). On the other hand, the source, substrate, and drain together form a parasitic nþ pnþ transistor. For short-channel devices, the small base width of the parasitic transistor results in an increase of current flowing into the impact ionization region. These problems causes difference between IDsat and ID . Figs. 2–4 show these currents for three MOSFET with different channel length. It is seen that with decreasing in channel length this difference is increased. In Section 2 by using multiplication factor model [1,2] and an approximation that have been explained in Appendix A a model is presented to predict drain current. The
*
Corresponding author. Tel.: +98-711-2303081; fax: +98711-6287294. E-mail addresses: [email protected], mm112045@ kcc.shirazu.ac.ir (S. Abbasian), [email protected] (E. Farjah).
validity of model with the results from MINIMOS simulation is presented in Section 3.
2. Model formulation If the total current enters the impact ionization region is IDsat þ IC (where IDsat is the drain saturation current before breakdown and IC is the collector current of the parasitic transistor), then the total drain current is [3] ID ¼ MðIDsat þ IC Þ
ð1Þ
Also the substrate current is given by: Isub ¼ ðM 1ÞðIDsat þ IC Þ
ð2Þ
where M is the avalanche multiplication factor and can be characterized by [1,2] M¼
1 K2 1 K1 exp VDS V Dsat
ð3Þ
where VDS and VDsat are the drain-to-source voltage and saturation voltage. K1 and K2 are parameters proportional to the width of depletion region and should be extracted for each device. In the other hand: ID ¼ IDsat þ IC þ Igen
0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 2 ) 0 0 2 7 2 - X
ð4Þ
334
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
Fig. 1. Cross-section of an NMOS transistor showing the currents in the parasitic npn transistor (After Ref. [3]). Fig. 4. Variation ID and IDsat versus VDS for a device with L ¼ 0:5 lm.
that: Igen ¼ Isub þ Ib
ð5Þ
where Isub is the substrate current, and Ib is the base current of PBT. If Ib is assumed negligible, then Eq. (4) is rewritten as Eq. (6): ID ¼ IDsat þ IC þ Isub
ð6Þ
By using MINIMOS and considering (6), one should obtain IC and Isub for several MOSFETs. Figs. 5 and 6 show the variation of IC versus Isub for two different MOSFETs. From these curves one should consider following approximation: Fig. 2. Variation ID and IDsat versus VDS for a device with L ¼ 2 lm.
Fig. 3. Variation ID and IDsat versus VDS for a device with L ¼ 1 lm.
IC ¼ K3 ð1 þ K4 VGS ÞIsub
ð7Þ
Fig. 5. Plot of IC versus Isub for an NMOS with L ¼ 0:4 lm.
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
335
Table 1 Values of model parameters used in MINIMOS simulation Channel length, L (lm) Channel width, W (lm) Oxide thickness tOX (A°) Substrate doping concentration ni (cm3 ) Diffuse material
0.4 10 500 5:2 1016 Arsenic
and K4 are necessary to be extracted. In following the method of parameters extraction is explained. Eq. (3) can be rewritten as follows: 1 K2 ¼ þ LnðK1 Þ ð11Þ ln 1 M VDS VDsat
Fig. 6. Plot of IC versus Isub for an NMOS with L ¼ 0:5 lm.
Where K3 and K4 are parameters that should be extracted for each device. It has been shown in Appendix A that: qVBsnap Rsub Leff csch ð8Þ K3 ð1 þ K4 VGS Þ ¼ c exp KT NB Ln That: c¼
q2 n2i ADn KTLn
ð9Þ
where Rsub , NB , Leff , VBsnap are the substrate resistance, substrate doping concentration, effective channel length of the MOSFET and potential on the substrate resistance in snapback point, respectively. ni , A, Ln , Dn , are the intrinsic carrier concentration, effective area of emitter–base junction, diffusion length of electron in the substrate and diffusion coefficient respectively. Substituting (7) into (1) and combining with (3), we have:
It is to be noted that Eq. (11) represents the linear relation between lnð1 ð1=MÞÞ and 1=ðVDS VDsat Þ with a slope of ðK2 Þ and its constant value equals to lnðK1 Þ. By using (1) and (2) and MINIMOS simulated data for drain and substrate currents, Multiplication factor is obtained, Fig. 7 shows variations of lnð1 ð1=MÞÞ versus ð1=ðVDS VDsat ÞÞ. Using this figure and considering Eq. (11), K1 and K2 are extracted which are 1.94 and 15.65 respectively. In Fig. 8 the ðIC =Isub Þ as a function of VGS is plotted, from this figure K3 and K4 could be obtained that are 4.69 and )0.025 respectively. Extracted values for K1 , K2 , K3 and K4 are used to determine drain current. Fig. 9. shows the simulated drain current by using proposed model and the MINIMOS results, either IDsat has been shown. In order to show the validity of model against the variation of channel lengths, some more simulation are carried out using channel length of 0.5 and 0.6 lm. Other parameters are the same as in Table 1. The extraction methods of K1 , K2 , K3 , and K4 are same as before. Extracted values for MOSFET with channel length
ID ¼
IDsat h i 2 ½K3 ð1 þ K4 VGS Þ þ 1 1 K1 exp VDSK K3 ð1 þ K4 VGS Þ VDsat
ð10Þ In subsequent section, by using this equation the drain current variation against different channel length of a MOSFET is investigated.
3. Analysis and results The parameters are defined in the input file of MINIMOS [4] and are used for simulation and summarized in Table 1. For the calculation of ID ; K1 , K2 , K3
1 . Fig. 7. Plot of ln 1 M1 versus VDS V Dsat
336
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
Fig. 8. (IC =Isub ) as a function of gate–source potential.
Fig. 10. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:5 lm, VGS ¼ 2 V.
Fig. 9. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:4 lm, VGS ¼ 2 V.
Fig. 11. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:6 lm, VGS ¼ 2 V.
0.5 lm are; K1 ¼ 2:3, K2 ¼ 21:8, K3 ¼ 4:85, K4 ¼ :05, and for 0.6 lm are; K1 ¼ 4:9, K2 ¼ 35:46, K3 ¼ 4:5, K4 ¼ 0:057. Figs. 10 and 11 show the simulation of drain current resulted from model and MINIMOS for above MOSFETs. Just as explained before; it is shown that by increasing in channel length, difference between IDsat and drain current becomes less. One reason is that by increasing base width of the parasitic transistor, it has a minor effect on drain current. In the other hand the function K3 ð1 þ K4 VGS Þ represents the influence of current PBT. Therefore it is expected that the same as current PBT, reduction in
channel length causes increase of K3 ð1 þ K4 VGS Þ and vice versa. Of course Eq. (8) can explain the effect of channel length on this function. In order to study this subject, the values of function have been obtained for MOSFETs with channel length between 0.5 and 1 lm and VGS ¼ 2 V. Fig. 12 shows the values of function versus channel length. Eq. (8) represents that increase of substrate doping (NB ) causes decrease of K3 ð1 þ K4 VGS Þ that results reduction in drain current. Fig. 13 shows the variation of this function versus NB for a device with L ¼ 0:4 lm and VGS ¼ 2 V that is in agreement with the trends predicted in Eq. (8).
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
337
Appendix A The collector current can be expressed as IC ¼ aIES expðqRsub Isub =KT Þ
ðA:1Þ
where a and IES are the common-base amplification factor and reverse saturation current of emitter junction of the parasitic transistor, KT =q is the thermal voltage and Rsub is the substrate resistance. Assuming unity emitter injection efficiency, the aIES product can be approximated by [3] aIES ¼
Fig. 12. Variation of K3 ð1 þ K4 VGS Þ versus channel length.
qADn n2i Leff csch Ln NB Ln
ðA:2Þ
where A, Dn , ni , NB , Ln , Leff are the effective area of emitter–base junction, diffusion coefficient, intrinsic carrier concentration, substrate doping concentration, diffusion length of electron in the substrate and the effective channel length of the MOSFET, respectively. In the snapback point, the potential of substrate resistance is bigger than thermal voltage [1,6], then: Rsub Isub KT =q
ðA:3Þ
If IC =Isub is approximated by a linear function that passes through the snapback point; then by applying (A.3) in (A.1), this function can be finally approximated as: IC qVBsnap Rsub Leff ðA:4Þ ¼ c exp csch Isub KT NB Ln That: c¼ Fig. 13. Variation of K3 ð1 þ K4 VGS Þ versus substrate doping for L ¼ 0:4 lm and VGS ¼ 2 V.
4. Conclusion In this paper a model of the drain current in shortchannel MOSFETs was presented. Decreasing in channel length causes the difference between channel current and drain current, This can be explained by factors, like multiplication factor, PBT current and variation of threshold voltage of MOSFET [5]. Eq. (1) uses of multiplication factor and current of PBT, but these factors are not constant parameters and vary with VDS . The proposed model uses four constant parameters instead of these two factors, which could be extracted for each device. The methods of parameter extraction were explained and simulation carried out for some MOSFETs with difference lengths. For the validation of model, MINIMOS software is chosen and the comparison of obtained results from proposed model with MINIMOS results are given that show a good agreement.
q2 n2i ADn KTLn
ðA:5Þ
where VBsnap is the potential of substrate resistance in snapback point. For a device with defined VGS , (A.4) is a constant value, but it depends on VBsnap and can change by variation of VGS , although the simulated results in Fig. 8 show that these changes are small and can be considered as a linear function. So the IC =Isub could be represented by a constant value plus a term related to changes of VGS IC ¼ K3 ð1 þ K4 VGS Þ Isub
ðA:6Þ
References [1] Amerasekera A, Ramaswamy S, Chang M, Duvvury C. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. In: Proc. IEEE IRPS 1996. p. 318–27. [2] Mergens M, Wilkening W, Mettler S, Wolf H, Fichtner W. Modular approach of high current MOS compact model for
338
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
circuit-level ESD simulation including transient gate coupling behavior. In: Proc. IEEE IRPS 1999. p. 167–78. [3] Wong H. Modeling of parasitic transistor-induced drain breakdown in MOSFETS. IEEE Trans Electron Dev 1996;ED-43:2190–6. [4] Fischer C, Habos P, Heinreichsberger O, Kosina H, Lindorfer Ph, Pichler P, et al. MINIMOS 6.1 UserÕs Guide, Technical University Vienna, 1999.
[5] Wong H. A physically based drain avalanche model for MOSFETs. IEEE Trans Electron Dev 1995;42:2197– 202. [6] Chen M, Lee H, Chen S. Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I–V characteristics in NMOS devices. IEEE Trans Electron Dev 2001;48:1237– 44.
Research Note
A new drain current model for short-channel MOSFETs Sadegh Abbasian, Ebrahim Farjah
*
Department of Electrical and Electronics Engineering, Shiraz University, Engineering Building 1, Zand Avenue, Shiraz 7134851154, Iran Received 25 April 2002; received in revised form 26 August 2002
Abstract Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction For a MOS transistor operating in saturation mode, the electric field near the drain region which is often called as the velocity saturation region or the pinch-off region, increases significantly and causes impact ionization. The generated electrons (for the case of nchannel MOSFET) are swept into the drain and enhance the drain current significantly whereas the holes flow into the substrate (see Fig. 1). On the other hand, the source, substrate, and drain together form a parasitic nþ pnþ transistor. For short-channel devices, the small base width of the parasitic transistor results in an increase of current flowing into the impact ionization region. These problems causes difference between IDsat and ID . Figs. 2–4 show these currents for three MOSFET with different channel length. It is seen that with decreasing in channel length this difference is increased. In Section 2 by using multiplication factor model [1,2] and an approximation that have been explained in Appendix A a model is presented to predict drain current. The
*
Corresponding author. Tel.: +98-711-2303081; fax: +98711-6287294. E-mail addresses: [email protected], mm112045@ kcc.shirazu.ac.ir (S. Abbasian), [email protected] (E. Farjah).
validity of model with the results from MINIMOS simulation is presented in Section 3.
2. Model formulation If the total current enters the impact ionization region is IDsat þ IC (where IDsat is the drain saturation current before breakdown and IC is the collector current of the parasitic transistor), then the total drain current is [3] ID ¼ MðIDsat þ IC Þ
ð1Þ
Also the substrate current is given by: Isub ¼ ðM 1ÞðIDsat þ IC Þ
ð2Þ
where M is the avalanche multiplication factor and can be characterized by [1,2] M¼
1 K2 1 K1 exp VDS V Dsat
ð3Þ
where VDS and VDsat are the drain-to-source voltage and saturation voltage. K1 and K2 are parameters proportional to the width of depletion region and should be extracted for each device. In the other hand: ID ¼ IDsat þ IC þ Igen
0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 2 ) 0 0 2 7 2 - X
ð4Þ
334
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
Fig. 1. Cross-section of an NMOS transistor showing the currents in the parasitic npn transistor (After Ref. [3]). Fig. 4. Variation ID and IDsat versus VDS for a device with L ¼ 0:5 lm.
that: Igen ¼ Isub þ Ib
ð5Þ
where Isub is the substrate current, and Ib is the base current of PBT. If Ib is assumed negligible, then Eq. (4) is rewritten as Eq. (6): ID ¼ IDsat þ IC þ Isub
ð6Þ
By using MINIMOS and considering (6), one should obtain IC and Isub for several MOSFETs. Figs. 5 and 6 show the variation of IC versus Isub for two different MOSFETs. From these curves one should consider following approximation: Fig. 2. Variation ID and IDsat versus VDS for a device with L ¼ 2 lm.
Fig. 3. Variation ID and IDsat versus VDS for a device with L ¼ 1 lm.
IC ¼ K3 ð1 þ K4 VGS ÞIsub
ð7Þ
Fig. 5. Plot of IC versus Isub for an NMOS with L ¼ 0:4 lm.
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
335
Table 1 Values of model parameters used in MINIMOS simulation Channel length, L (lm) Channel width, W (lm) Oxide thickness tOX (A°) Substrate doping concentration ni (cm3 ) Diffuse material
0.4 10 500 5:2 1016 Arsenic
and K4 are necessary to be extracted. In following the method of parameters extraction is explained. Eq. (3) can be rewritten as follows: 1 K2 ¼ þ LnðK1 Þ ð11Þ ln 1 M VDS VDsat
Fig. 6. Plot of IC versus Isub for an NMOS with L ¼ 0:5 lm.
Where K3 and K4 are parameters that should be extracted for each device. It has been shown in Appendix A that: qVBsnap Rsub Leff csch ð8Þ K3 ð1 þ K4 VGS Þ ¼ c exp KT NB Ln That: c¼
q2 n2i ADn KTLn
ð9Þ
where Rsub , NB , Leff , VBsnap are the substrate resistance, substrate doping concentration, effective channel length of the MOSFET and potential on the substrate resistance in snapback point, respectively. ni , A, Ln , Dn , are the intrinsic carrier concentration, effective area of emitter–base junction, diffusion length of electron in the substrate and diffusion coefficient respectively. Substituting (7) into (1) and combining with (3), we have:
It is to be noted that Eq. (11) represents the linear relation between lnð1 ð1=MÞÞ and 1=ðVDS VDsat Þ with a slope of ðK2 Þ and its constant value equals to lnðK1 Þ. By using (1) and (2) and MINIMOS simulated data for drain and substrate currents, Multiplication factor is obtained, Fig. 7 shows variations of lnð1 ð1=MÞÞ versus ð1=ðVDS VDsat ÞÞ. Using this figure and considering Eq. (11), K1 and K2 are extracted which are 1.94 and 15.65 respectively. In Fig. 8 the ðIC =Isub Þ as a function of VGS is plotted, from this figure K3 and K4 could be obtained that are 4.69 and )0.025 respectively. Extracted values for K1 , K2 , K3 and K4 are used to determine drain current. Fig. 9. shows the simulated drain current by using proposed model and the MINIMOS results, either IDsat has been shown. In order to show the validity of model against the variation of channel lengths, some more simulation are carried out using channel length of 0.5 and 0.6 lm. Other parameters are the same as in Table 1. The extraction methods of K1 , K2 , K3 , and K4 are same as before. Extracted values for MOSFET with channel length
ID ¼
IDsat h i 2 ½K3 ð1 þ K4 VGS Þ þ 1 1 K1 exp VDSK K3 ð1 þ K4 VGS Þ VDsat
ð10Þ In subsequent section, by using this equation the drain current variation against different channel length of a MOSFET is investigated.
3. Analysis and results The parameters are defined in the input file of MINIMOS [4] and are used for simulation and summarized in Table 1. For the calculation of ID ; K1 , K2 , K3
1 . Fig. 7. Plot of ln 1 M1 versus VDS V Dsat
336
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
Fig. 8. (IC =Isub ) as a function of gate–source potential.
Fig. 10. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:5 lm, VGS ¼ 2 V.
Fig. 9. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:4 lm, VGS ¼ 2 V.
Fig. 11. Comparison of simulated values of the drain current obtained from model and the MINIMOS for L ¼ 0:6 lm, VGS ¼ 2 V.
0.5 lm are; K1 ¼ 2:3, K2 ¼ 21:8, K3 ¼ 4:85, K4 ¼ :05, and for 0.6 lm are; K1 ¼ 4:9, K2 ¼ 35:46, K3 ¼ 4:5, K4 ¼ 0:057. Figs. 10 and 11 show the simulation of drain current resulted from model and MINIMOS for above MOSFETs. Just as explained before; it is shown that by increasing in channel length, difference between IDsat and drain current becomes less. One reason is that by increasing base width of the parasitic transistor, it has a minor effect on drain current. In the other hand the function K3 ð1 þ K4 VGS Þ represents the influence of current PBT. Therefore it is expected that the same as current PBT, reduction in
channel length causes increase of K3 ð1 þ K4 VGS Þ and vice versa. Of course Eq. (8) can explain the effect of channel length on this function. In order to study this subject, the values of function have been obtained for MOSFETs with channel length between 0.5 and 1 lm and VGS ¼ 2 V. Fig. 12 shows the values of function versus channel length. Eq. (8) represents that increase of substrate doping (NB ) causes decrease of K3 ð1 þ K4 VGS Þ that results reduction in drain current. Fig. 13 shows the variation of this function versus NB for a device with L ¼ 0:4 lm and VGS ¼ 2 V that is in agreement with the trends predicted in Eq. (8).
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
337
Appendix A The collector current can be expressed as IC ¼ aIES expðqRsub Isub =KT Þ
ðA:1Þ
where a and IES are the common-base amplification factor and reverse saturation current of emitter junction of the parasitic transistor, KT =q is the thermal voltage and Rsub is the substrate resistance. Assuming unity emitter injection efficiency, the aIES product can be approximated by [3] aIES ¼
Fig. 12. Variation of K3 ð1 þ K4 VGS Þ versus channel length.
qADn n2i Leff csch Ln NB Ln
ðA:2Þ
where A, Dn , ni , NB , Ln , Leff are the effective area of emitter–base junction, diffusion coefficient, intrinsic carrier concentration, substrate doping concentration, diffusion length of electron in the substrate and the effective channel length of the MOSFET, respectively. In the snapback point, the potential of substrate resistance is bigger than thermal voltage [1,6], then: Rsub Isub KT =q
ðA:3Þ
If IC =Isub is approximated by a linear function that passes through the snapback point; then by applying (A.3) in (A.1), this function can be finally approximated as: IC qVBsnap Rsub Leff ðA:4Þ ¼ c exp csch Isub KT NB Ln That: c¼ Fig. 13. Variation of K3 ð1 þ K4 VGS Þ versus substrate doping for L ¼ 0:4 lm and VGS ¼ 2 V.
4. Conclusion In this paper a model of the drain current in shortchannel MOSFETs was presented. Decreasing in channel length causes the difference between channel current and drain current, This can be explained by factors, like multiplication factor, PBT current and variation of threshold voltage of MOSFET [5]. Eq. (1) uses of multiplication factor and current of PBT, but these factors are not constant parameters and vary with VDS . The proposed model uses four constant parameters instead of these two factors, which could be extracted for each device. The methods of parameter extraction were explained and simulation carried out for some MOSFETs with difference lengths. For the validation of model, MINIMOS software is chosen and the comparison of obtained results from proposed model with MINIMOS results are given that show a good agreement.
q2 n2i ADn KTLn
ðA:5Þ
where VBsnap is the potential of substrate resistance in snapback point. For a device with defined VGS , (A.4) is a constant value, but it depends on VBsnap and can change by variation of VGS , although the simulated results in Fig. 8 show that these changes are small and can be considered as a linear function. So the IC =Isub could be represented by a constant value plus a term related to changes of VGS IC ¼ K3 ð1 þ K4 VGS Þ Isub
ðA:6Þ
References [1] Amerasekera A, Ramaswamy S, Chang M, Duvvury C. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. In: Proc. IEEE IRPS 1996. p. 318–27. [2] Mergens M, Wilkening W, Mettler S, Wolf H, Fichtner W. Modular approach of high current MOS compact model for
338
S. Abbasian, E. Farjah / Microelectronics Reliability 43 (2003) 333–338
circuit-level ESD simulation including transient gate coupling behavior. In: Proc. IEEE IRPS 1999. p. 167–78. [3] Wong H. Modeling of parasitic transistor-induced drain breakdown in MOSFETS. IEEE Trans Electron Dev 1996;ED-43:2190–6. [4] Fischer C, Habos P, Heinreichsberger O, Kosina H, Lindorfer Ph, Pichler P, et al. MINIMOS 6.1 UserÕs Guide, Technical University Vienna, 1999.
[5] Wong H. A physically based drain avalanche model for MOSFETs. IEEE Trans Electron Dev 1995;42:2197– 202. [6] Chen M, Lee H, Chen S. Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I–V characteristics in NMOS devices. IEEE Trans Electron Dev 2001;48:1237– 44.