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A new driving waveform to improve the minimum data voltage
Available online at www.sciencedirect.com
Displays 29 (2008) 369–375 www.elsevier.com/locate/displa
A new driving waveform to improve the minimum data voltage Yongduk Kim a, Sekwang Park b
b,*
a R&D Center, Orion PDP Co. Ltd., 257 Gongdan-dong, Gumi, Kyung-buk 703-030, Republic of Korea Department of Electrical Engineering, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu 702-701, Republic of Korea
Received 30 October 2007; accepted 19 November 2007 Available online 3 December 2007
Abstract Currently, a high-speed driving technology is a rapidly developing creative environment that is looking for ways of driving PDP for high image quality. Herein, a new waveform is proposed for high-speed driving. A proposed driving waveform, which had a log-type scan waveform, was proved by applying to a 4-in. test panel. The results showed that the minimum Vdata voltage of the driving waveform was about 27.0 V at a scan pulse width of 0.8 ls. This result shows that the minimum Vdata voltage decreases by 27.0 V from the conventional driving waveform. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Plasma display; High-speed driving technology; Priming effect; Address discharge characteristics
1. Introduction Regarding large-screen displays, a plasma display panel is in the spotlight because it has wide viewing angle and high luminance. PDPs involve important research themes; luminance efficiency enhancement, high-speed addressing technology, power consumption reduction technology, low cost technology, and environment-friendly material development. Factors such as gray-scale levels, dynamic false contours, and burning, however, have to be improved. Also, a high density display should be developed with high image quality. High-speed addressing technology is required in order to meet these consumer demands. The number of subfields, which are being produced for driving a PDP, is normally 10–12 for image data processing above 8 bits. Since the increase of the number of subfields also enhances the number of gray-scale levels, clearer pictures can be offered. In PDP driving, a high-speed addressing technology is essential to increase the data processing and to enhance gray-scale levels by increasing the number of
*
Corresponding author. Tel.: +82 53 950 5606; fax: +82 53 950 6600. E-mail address: [email protected] (S. Park).
0141-9382/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.displa.2007.11.002
subfields [1–5]. The dynamic false contour also can be improved by the increase of the number of subfields and the optimization of the weight value for each subfield [3]. High-speed driving methods are geared forwards the improvement of discharge characteristics and the development of driving waveforms. In order to improve discharge characteristics, a panel’s structure needs to be improved so as to decrease the discharge delay time lag or to develop discharge gas compositions [5]. For the driving waveform, methods included the priming effect or the dual scan method in the past [1–5]. The priming effect is the effect of the charged particles which are generated by weak reset discharges [4–6]. The dual-scan method can decrease the total scan time because it can drive two scan lines simultaneously after a panel is divided by two parts. In this case, the cost of the product increases because twice the number of Data-ICs for data driving must be used. Therefore, the new technology that can improve image quality, lower cost, and allow high-speed addressing with a single-scan method needs to be developed. In the case of the conventional waveform, the address discharge delay was analyzed by measuring exposed light when the address discharge occurred, in this paper. A new driving waveform that embodies high-speed addressing using enhanced address characteristics was proposed.
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Y. Kim, S. Park / Displays 29 (2008) 369–375
This improved waveform performed better with a lower minimum Vdata voltage than the conventional waveform and the stable address discharge.
2. Conventional driving waveform 2.1. The conventional driving waveform and the address discharge delay The driving waveform usually uses a ramp-reset waveform. Fig. 1 shows the basic ramp-reset waveform. The driving waveform for PDP is separated by the reset, address, and sustain periods. In the reset period, the wall charges are uniformed for good address discharge by weak discharges in ramp reset. In the address period, the ONcells and OFF-cells are separated by the address discharge. And then, the sustain discharges occur in sustain period for luminance with the wanted gray-scale levels. The discharge occurs when the applied cell voltage (Vc) between the electrodes is over the firing voltage (Vf) of each cell. The cell voltage is defined by the summation of the wall voltage (Vw) and the applied voltage (Vc), as shown in Eq. (1). A discharge strength is depended on the cell and firing voltages. Weak discharges, which occur in the ramp-reset period, uniformly accumulate wall charges on each electrode, as mentioned above. These wall charges influence the discharge between electrodes. Vc ¼VwþVa
ð1Þ
In particular, after ramp-reset period (t0 in Fig. 1), the cell voltages VcAY between the A and Y electrodes and VcXY between the X and Y electrodes are equal to the firing voltages VfAY and VfXY, respectively [7]. The charged particles, which are generated by the weak reset discharges in the reset period, exist within a cell. If the Vdata voltage is applied to the address (A) electrode in the address period, a strong trigger discharge occurs, because VcAY is the summation of VfAY and Vdata, as shown in Eq. (2). V cAY ¼ V fAY þ V data
ð2Þ
Vramp
Vsus
Vsus Vylevel
Y Vxr
Vxl
X
The charged vacuum particles, which are generated by these trigger discharges, decrease the firing voltage between the X and Y electrodes, as shown in Eqs. (3) and (4). Also, they induce a strong discharge between the X and Y electrodes. V 0fXY ¼ V fXY DV
ð3Þ
V cXY ¼ V 0fXY þ DV
ð4Þ
here, V 0fXY is the new firing voltage between the X and Y electrodes and DV is the difference between the firing voltages before and after the trigger discharge. In particular, the priming particles, which are not located on any electrode and float in discharge vacuum area, decrease highly the firing voltages. After ramp reset, the charged particles distribute like Fig. 2(a). At this time, the priming particles remain in the discharged area. The address discharges occur in order of the scan lines. When the scan lines close in the time of the reset period, these priming particles will have an influence on the address discharges and can decrease the Vdata [6]. These priming particles, however, disappear as time goes by, as shown in Fig. 2(b), and the minimum Vdata voltage that needs to be discharged will increase because the priming effects do not have an influence on the address discharges. It is the reason of the increase of the Vdata voltage as the Ts increases. Fig. 3 shows the results whereby the address discharge delays were measured according to Ts, when the scan pulse width was 2.0 ls, Vsus was 170 V, Vxr was 160 V, Vxl was 165 V, Vramp was 230 V, and the Vdata voltage was fixed at 70 V in the conventional driving waveform, as shown in Fig. 1. In this test, the specification of test panel was 4-in. stripe-type VGA within He(69%)–Ne(27%)–Xe(4%) gas mixture. The cell pitch was 1.08 by 1.08 lm. The formative and statistical time lagged and the strength of the address discharge became weaker as the Ts increases because the minimum Vdata voltage rose because the address discharge had an effect on the priming particles. The larger the Ts was, the weaker the address discharge became and the delay time increased further. These results show that the address discharges are unstable as the Ts increases. The minimum Vdata voltage increases according to Ts, because the charge particles disappear and discharge time delay increases. Fig. 4 shows the results that the minimum Vdata voltages were measured according to the scan pulse width and Ts. The minimum Vdata voltage rapidly increased before Ts of 120 ls but slowly increased after Ts of 120 ls. For scan pulse widths of 2.0 ls and 0.8 ls, the minimum X
Y
X
+ + + + + + +
- - - - - - - - -
+ + + + + + + + + +
+
+ +
-
Y - - - - - - - - - - - -
-
Vdata +
A t0 Reset
+ + +
t1 Ts Address
Sustain
Fig. 1. The conventional driving waveform.
+ + + +
A
A
(a) at t0 (after reset)
(b) at t1 (before scan pulse input)
Fig. 2. The distribution of charged particles.
Y. Kim, S. Park / Displays 29 (2008) 369–375
371
Vramp
Vsus Y
Vsus
Vylevel
ΔVscan
Vyd
Vsc
X Vdata A t0
t2
Fig. 5. The driving waveform, which was proposed by Sakita, for highspeed addressing [2]. Fig. 3. The optical signal according to Ts when address discharges occur (Vdata = 70 V). The discharge signals were measured after the scan pulse and the Vdata voltage were applied.
60
Min. Vdata [V]
50 40
DV scan ¼ V yd V sc
30 Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
20 10 0 0.0
and main discharge between X and Y electrodes. The trigger discharge strongly occurs when the Vdata is supplied to the A electrode because VcAY is higher than VfAY as the Vdata. If we want to obtain a lower Vdata voltage, the scan voltage in the address period should be set lower scan voltage than the applied voltage of the Y electrode at time t0, as indicated in Fig. 1. Fig. 5 shows that the scan voltage in the driving waveform, which was proposed by Sakita, had lower scan voltage than the applied voltage of Y electrode at t0 [2]. Herein, the DVscan voltage is defined as Eq. (5).
0.2
0.4
0.6
0.8
1.0
Ts [ms] Fig. 4. The minimum Vdata voltage according to the scan pulse width using the conventional driving waveform [8].
ð5Þ
The Vyd and Vsc are the voltage of Y electrode at t0 (at the end of reset period) and t2 (at the time of scan pulse input) in Fig. 5, respectively. At first, to analyze the influence on the DVscan voltage, the minimum Vdata voltage was measured, when the DVscan voltage was 10 V (Vyd was 0 V and Vsc was 10 V) at the driving waveform, as shown in Fig. 5. Fig. 6 shows these experimental results. From these results, the minimum Vdata voltages rapidly increased before Ts of 120 ls and slowly increased like the 60
2.2. The driving waveform with the DVscan voltage As mentioned above, the address discharge is composed of the trigger discharge between the A and Y electrodes
50
Min. Vdata [V]
Vdata voltages were 21.5 V and 30.0 V at Ts of 10 ls and 25.0 V and 46.0 V at Ts of 120 ls, respectively. In the case of Ts of 1000 ls, the Vdata voltages were 27.5 V and 54.0 V, respectively. Therefore, in order to drive a PDP, the minimum Vdata voltage must be decided by the last scan line, because the Vdata is the highest voltage at Ts of 1.0 ms in these experimental results. If the scan pulse width is set at 2.0 ls for the driving VGA, the minimum Vdata voltage will be 27.5 V. If the pulse width is 1.2 ls, however, this voltage rises to 38.5 V. It increases rapidly to a high of 54.0 V at the width of 0.8 ls.
40 30 20 Pw=0.8µs Pw=1.2µs Pw=1.6µs
10 0 0.0
0.2
0.4
0.6
Pw=1.0µs Pw=1.4µs Pw=2.0µs
0.8
1.0
Ts [ms] Fig. 6. The minimum Vdata voltage according to a scan pulse width at the DVscan of 10 V.
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conventional waveform. These minimum Vdata voltages were 19.0 V and 50.0 V, respectively, at a scan pulse width of 2.0 ls and 0.8 ls. These were the decrease of 8.5 V and 4.0 V from the conventional waveform, respectively. The scan voltage decreased by 10.0 V. However the minimum Vdata voltage just decreased 4.0 V, when the scan pulse width was 0.8 ls. These decreasing rates are insufficient for high-speed addressing with a scan pulse width of 0.8 ls. Consequently, a higher DVscan voltage is required. These DVscan voltages can be set the highest value without misaddressing of the OFF-cells. The maximum DVscan voltage that can be applied increases as the scan pulse width narrows [8]. The allowed maximum DVscan voltages of the first and last scan lines were 12.0 V and 15.5 V at a scan pulse width of 2.0 ls and 25.0 V and 33.5 V at a scan pulse width of 0.8 ls, respectively [8]. From these previous experimental results, we got the result that the applied DVscan voltage had to be increased according to the scan pulse input time (Ts) to achieve the high-speed driving for a PDP without misaddressing of the OFF-cells. 3. The principal of proposed driving waveform The higher DVscan voltage is, the lower minimum Vdata voltage becomes. However, the conventional scan voltage was set by the same DVscan voltage in all address period. If the same DVscan voltage is applied to all scan lines, as shown in Fig. 5, the minimum Vdata voltage should be decided by the last scan line. Because the highest value among the minimum Vdata voltage is the Vdata at the last scan line. On the other hand, the maximum DVscan voltage is decided by the misaddressing of the OFF-cells in the 1st scan line. If the DVscan voltage can be set to high, the minimum Vdata voltage could decrease more and more in spite of a narrower scan pulse width of 0.8 ls. However, the DVbscan cannot extremely be high because of misaddressing of the OFF-cells. So, the minimum Vdata voltage is limited. Therefore, the waveform, that had the linearly increased DVscan voltage according to the Ts, was proposed in Ref. [8], as shown in Fig. 7(a) and (b). The minimum Vdata voltage could be lowered by using the priming effects at low Ts and a high DVscan voltage at a high Ts. However, those results were not enough to reduce the minimum Vdata voltage for full HD PDP. So, the new driving waveform for high-speed addressing is proposed, as shown in Fig. 7(c) in this paper. The proposed waveform is that the DVscan voltage increases with log-type DVscan voltages shape as the Ts increases. In here, the amplitude of Vylevel voltage is not varied in all address period. The operating principle of the proposed driving waveform is explained as follows. For the compensation of the increase of the Vdata voltage as the Ts increased, the DVscan voltage continuously increased in the address period as the Ts increased, as shown in Fig. 7. The DVscanvoltages for Y1, . . . , Ym, . . . , and Yn are applied, as expressed by Eq. (6).
Y1 … Ym …
ΔVsc1 ΔVscm
Yn
ΔVscn
X A (a) The proposed driving waveform for high speed addressing
Y1
Ym
Yn
Y (b) The method that the scan voltage was supplied by a linear-type [8]
Y1 Y
Ym
Yn
(c) The method that the scan voltage was supplied by a log-type Fig. 7. The proposed waveform for high-speed addressing. The scan voltage was changed according to Ts.
DV sc1 < DV sc2 < < DV scm < < DV scn
ð6Þ
The priming particles decrease the firing voltages among the electrodes and the voltage of transition region. The firing voltages and voltages of transition regions continuously increase as Ts increases, because these particles disappear. The outline of the Vt closed curve that is the firing voltage and the transition region will go away from original point on the Vt plane, as shown in Fig. 8. The minimum Vdata voltage is defined by the lowest Vdata to induce the continuous sustain discharge for all ON-cells. Theoretically, this is voltage between the edge (VfAY) of Vt closed curve and transition region, as shown in Fig. 8(a) [9]. In the conventional driving waveform, the increasing voltages of the firing voltage and transition region were not compensated, as expressed by Fig. 8(a). So, the minimum Vdata voltage must be increased. On the other hand, in the proposed driving waveform, the increasing Vdata voltage can be compensated by the continuous increase of the scan voltage. In that time, the scan voltage is limited by the measured maximum DVscan voltage to avoid the misaddressing of OFF-cells.
Y. Kim, S. Park / Displays 29 (2008) 369–375 Transition region Vdatan(min) Vdatam(min) Tym
Vdata1(min) ΔVsc
40
Tyn
Ty1
VT1 VTm
Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=2.0µs
50
Min. V data [V]
VAY
373
30 20
VTn
10
VXY
(a) Conventional condition
0 0.0
0.2
0.4
Transition region VAY
Vdatan(min) Vdatam(min) Vdata1(min)
ΔVscn ΔVscm ΔVsc1 Ty1
Tym
Tyn
1.0
4.2. Log-type DVscan voltage
VTn VXY
(b) Proposed condition Fig. 8. Operating mechanism of the proposed waveform. In here, VT1, VTm and VTn are the Vt closed curves of 1st, mth and nth scan line, Ty1, Tym, Tyn are the transition region of the 1st, mth and nth scan line, Vdata1(min), Vdatam(min) and Vdatan(min) are the minimum data voltage of the 1st, mth and nth scan line, and DVsc1, DVscm and DVscn are the DVscan voltage of the 1st, mth and nth scan line, respectively.
4. Experimental results and discussion 4.1. Linear-type DVscan voltage In the previous waveform test [8], the dynamic Vdata margins were measured according to Ts and scan pulse width, when the DVscan voltage was linearly varied between 5 V and 20 V for the fabricated test panel, as shown in Eq. 7. The experimental results were shown in Fig. 9. DV scan ¼ 15T s þ 5
0.8
Fig. 9. The minimum Vdata voltage according to Ts. The applied DVscan voltage waveform is similar to equation in Eq. (7). The DVscan voltage is varied between 5 V and 20 V [8].
VT1 VTm
0.6 Ts [ms]
ð7Þ
From those experimental results, the dynamic Vdata margin, in the case of a scan pulse width of 2.0 ls, could not be obtained because of the discharge of OFF-cells at high Ts. The Vdata margins, however, could be obtained at another scan pulse widths. The minimum Vdata voltages were lowered as the DVscan voltage was increased, when these were compared with the conventional waveform in Fig. 4. In the case of a scan pulse width of 0.8 ls, the dynamic margin of the minimum Vdata was 39.5 V. This result showed a decrease of 14.5 V from the conventional driving waveform, which had the minimum Vdata of 54.0 V [8].
As we mentioned above, those results using the lineartype DVscan voltage waveforms were not enough to drive full HD PDP. Therefore, the two different driving waveforms with log-type DVscan Voltage, as shown in Fig. 7(c), were proposed and tested. The two applied DVscan voltage waveforms were approximated to Eqs. (8) and (9). The DVscan voltage in Eq. (9) is higher than that in Eq. (8). DV scan ¼ 4:2 lnð9T s Þ þ 10
ð8Þ
DV scan ¼ 4:2 lnð9T s Þ þ 20
ð9Þ
Fig. 10(a) and (b) show the measured minimum Vdata voltage in case of Eqs. (8) and (9), respectively. In Fig. 10(a), the dynamic Vdata margin could be obtained when the scan pulse widths were below 1.4 ls. In particular, the minimum Vdata voltage was 36.0 V at the scan pulse width of 0.8 ls and it was a decrease of 18.0 V when it was compared with the conventional waveform. This voltage was nearly constant over all ranges of Ts. In the case of Fig. 10(b), however, the dynamic margin was obtained when the scan pulse widths were below 0.8 ls. This is due to the misaddressing of the OFF-cells. The minimum Vdata voltage was 27.0 V. This result is a decrease of 27.0 V from the conventional waveform at the scan pulse width of 0.8 ls. Fig. 11 shows the experimental results, when the new driving waveform is compared with the conventional waveform and the proposed waveform by Sakita, at a scan pulse width of 0.8 ls. The dynamic minimum Vdata of the conventional waveform is 54.0 V and that of the proposed waveform by Sakita is 50.0 V. In the case of the proposed driving waveform, however, the minimum Vdata voltage was 27.0 V and there was a decrease of 27.0 V from the conventional waveform. So, these experimental results
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Y. Kim, S. Park / Displays 29 (2008) 369–375
60 50 Min. Vdata [V]
show the proposed driving waveform has the excellent address discharge characteristics.
Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
40
5. Conclusions
30 20 10 0 0.0
0.2
0.4
0.6 0.8 1.0 Ts [ms] (a) Whereby the ΔVscan voltage was varied as in Eq. (8)
60 Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
Min. Vdata [V]
50 40 30 20
Acknowledgement
10 0 0.0
0.2
0.4
0.6
0.8
1.0
Ts [ms] (b) Whereby the Vscan voltage was varied as in Eq. (9) Fig. 10. The minimum Vdata voltage according to Ts. The DVscan voltages were varied as in Eqs. (8) and (9).
50
40 Min. Vdata [V]
Priming effects can be used for driving PDP. The priming particles, however, which are generated in the reset period, disappeared after Ts is 120 ls, in these experiments. The minimum Vdata voltage continuously increased for the sustain discharges, because the charged particles in the vacuum quickly disappeared and the wall charges were slowly redistributed. In order to compensate for the increase of the minimum Vdata, the new driving waveform with the log-type DVscan voltage was proposed and tested. In testing the proposed waveform, a 4-in. panel was fabricated and a driving circuit was designed. Then, the minimum Vdata voltages were compared with the conventional waveform. In the case of a scan pulse width of 0.8 ls, the minimum Vdata voltage of the proposed waveform was 27.0 V and was a decrease of 27.0 V, when it was compared with the minimum Vdata of the conventional waveform. From these results, it was proved that the proposed waveform for the PDP was usable. If the new waveform is used for a driving PDP, the increase of the number of the subfields and the improvements of the gray-scale levels can be anticipated.
30 20 Conventional Vscan = -10V 10V Vscan= Vscan Linear Vscan Proposed Proposed
10 0 0.0
0.2
0.4
0.6
0.8
1.0
Ts [ms] Fig. 11. A comparison between the minimum Vdata voltages of the conventional and proposed waveform.
This work was also partly supported by the Brain Korea 21 (BK21) program of the Ministry of Education and supported by the ERC program of KOSEF (Grant R11-2000075-02002-0). References [1] Jae Sung Kim, Jin Ho Yang, Ki Woong Whang, A driving method for high-speed addressing in an AC PDP using priming effect, IEEE Trans. Electron Devices 51 (4) (2004) 548–553. [2] K. Sakita, K. Takayama, K. Awamoto, Y. Hashimoto, High-speed address driving waveform analysis using wall voltage transfer function for three terminal and Vt close curve in three-electrode surfacedischarge AC-PDP’s, SID Tech. Dig., 2001 (2001) 1022–1025. [3] M. Kasahara, M. Ishikawa, T. Morita, S. Inohara, New drive system for PDPs with improved image quality: plasma AI, SID Tech. Dig.,’99 (1999) 158–161. [4] M. Ishii, A. Gotoda, T. Shiga, K. Igarashi, S. Mikoshiba, Addresswhile-display drive scheme of AC PDP’s with 50 V scan and 20 V data pulses by use of erase addressing with space charge priming, Proc. IDW01 (2001) 817–820. [5] Jae Sung Kim, Jin Ho Yang, Tae Jun Kim, Ki Woong Whang, Comparison of electric field and priming particle effects on address discharge time lag and addressing characteristics of high-Xe content AC PDP, IEEE Trans. Plasma Sci. 31 (5) (2003) 1083–1090. [6] S.K. Lee, W.J. Kim, Y.J. Lee, Y.D. Kim, M.S. Kim, S.J. Moon, Y.H. Kwon, S.J. Yoo, J.D. Kim, Analysis of priming effect using Vt close curve, Proc. IDW02 (2002) 709–712. [7] Y.D. Kim, W.J. Kim, Y.J. Lee, S.K. Lee, M.S. Kim, S.J. Moon, Y.H. Kwon, S.J. Yoo, J.D. Kim, The relation between opposed firing and ramp reset voltage in AC-PDP driving waveform, Proc. IDW02 (2002) 717–720.
Y. Kim, S. Park / Displays 29 (2008) 369–375 [8] Y. Kim, S. Park, The improvement of the driving waveform for highspeed addressing, Displays, accepted, 2007.07. [9] Y. Kim, S. Park, Analysis of the influence of the address electrode width on high-speed addressing using the Vt close curve and dynamic Vdata margin, KIEE Int. Trans. Electrophys. Appl. 5-C (5) (2005) 183–190.
Yongduk Kim received the B.S., M.S. and Ph. D. degrees in Electrical Engineering from Kyungpook National University, Daegu, Korea, in 1995, 1997 and 2006, respectively. He is currently with the PDP R&D center of Orion PDP Co., Ltd., Gumi, Kyung-Buk, Korea. His research interests are the design of driving waveforms, driving circuits, and the analysis of plasma discharge for AC-PDP, micro-
electronics, motor technology.
375 control,
sensors
and
actuators,
and
MEMS
Sekwang Park received the B.S. degree in Electrical Engineering from Seoul National University, Seoul, Korea, in 1976, and M.S. and Ph.D. degrees in electrical engineering from Case Western Reserve University, Cleveland, OH, U.S.A. in 1984 and 1988, respectively. He was project leader of L. VAD Technology, U.S.A., from 1988 until 1989. He is currently a Professor in the Department of Electrical Engineering at Kyungpook National University. His research interests are the driving waveforms and circuits for PDP, microelectronics, sensors and actuators using MEMS technology, especially, pressure sensors, flow sensors, temperature sensors, and humidity sensors.
Displays 29 (2008) 369–375 www.elsevier.com/locate/displa
A new driving waveform to improve the minimum data voltage Yongduk Kim a, Sekwang Park b
b,*
a R&D Center, Orion PDP Co. Ltd., 257 Gongdan-dong, Gumi, Kyung-buk 703-030, Republic of Korea Department of Electrical Engineering, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu 702-701, Republic of Korea
Received 30 October 2007; accepted 19 November 2007 Available online 3 December 2007
Abstract Currently, a high-speed driving technology is a rapidly developing creative environment that is looking for ways of driving PDP for high image quality. Herein, a new waveform is proposed for high-speed driving. A proposed driving waveform, which had a log-type scan waveform, was proved by applying to a 4-in. test panel. The results showed that the minimum Vdata voltage of the driving waveform was about 27.0 V at a scan pulse width of 0.8 ls. This result shows that the minimum Vdata voltage decreases by 27.0 V from the conventional driving waveform. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Plasma display; High-speed driving technology; Priming effect; Address discharge characteristics
1. Introduction Regarding large-screen displays, a plasma display panel is in the spotlight because it has wide viewing angle and high luminance. PDPs involve important research themes; luminance efficiency enhancement, high-speed addressing technology, power consumption reduction technology, low cost technology, and environment-friendly material development. Factors such as gray-scale levels, dynamic false contours, and burning, however, have to be improved. Also, a high density display should be developed with high image quality. High-speed addressing technology is required in order to meet these consumer demands. The number of subfields, which are being produced for driving a PDP, is normally 10–12 for image data processing above 8 bits. Since the increase of the number of subfields also enhances the number of gray-scale levels, clearer pictures can be offered. In PDP driving, a high-speed addressing technology is essential to increase the data processing and to enhance gray-scale levels by increasing the number of
*
Corresponding author. Tel.: +82 53 950 5606; fax: +82 53 950 6600. E-mail address: [email protected] (S. Park).
0141-9382/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.displa.2007.11.002
subfields [1–5]. The dynamic false contour also can be improved by the increase of the number of subfields and the optimization of the weight value for each subfield [3]. High-speed driving methods are geared forwards the improvement of discharge characteristics and the development of driving waveforms. In order to improve discharge characteristics, a panel’s structure needs to be improved so as to decrease the discharge delay time lag or to develop discharge gas compositions [5]. For the driving waveform, methods included the priming effect or the dual scan method in the past [1–5]. The priming effect is the effect of the charged particles which are generated by weak reset discharges [4–6]. The dual-scan method can decrease the total scan time because it can drive two scan lines simultaneously after a panel is divided by two parts. In this case, the cost of the product increases because twice the number of Data-ICs for data driving must be used. Therefore, the new technology that can improve image quality, lower cost, and allow high-speed addressing with a single-scan method needs to be developed. In the case of the conventional waveform, the address discharge delay was analyzed by measuring exposed light when the address discharge occurred, in this paper. A new driving waveform that embodies high-speed addressing using enhanced address characteristics was proposed.
370
Y. Kim, S. Park / Displays 29 (2008) 369–375
This improved waveform performed better with a lower minimum Vdata voltage than the conventional waveform and the stable address discharge.
2. Conventional driving waveform 2.1. The conventional driving waveform and the address discharge delay The driving waveform usually uses a ramp-reset waveform. Fig. 1 shows the basic ramp-reset waveform. The driving waveform for PDP is separated by the reset, address, and sustain periods. In the reset period, the wall charges are uniformed for good address discharge by weak discharges in ramp reset. In the address period, the ONcells and OFF-cells are separated by the address discharge. And then, the sustain discharges occur in sustain period for luminance with the wanted gray-scale levels. The discharge occurs when the applied cell voltage (Vc) between the electrodes is over the firing voltage (Vf) of each cell. The cell voltage is defined by the summation of the wall voltage (Vw) and the applied voltage (Vc), as shown in Eq. (1). A discharge strength is depended on the cell and firing voltages. Weak discharges, which occur in the ramp-reset period, uniformly accumulate wall charges on each electrode, as mentioned above. These wall charges influence the discharge between electrodes. Vc ¼VwþVa
ð1Þ
In particular, after ramp-reset period (t0 in Fig. 1), the cell voltages VcAY between the A and Y electrodes and VcXY between the X and Y electrodes are equal to the firing voltages VfAY and VfXY, respectively [7]. The charged particles, which are generated by the weak reset discharges in the reset period, exist within a cell. If the Vdata voltage is applied to the address (A) electrode in the address period, a strong trigger discharge occurs, because VcAY is the summation of VfAY and Vdata, as shown in Eq. (2). V cAY ¼ V fAY þ V data
ð2Þ
Vramp
Vsus
Vsus Vylevel
Y Vxr
Vxl
X
The charged vacuum particles, which are generated by these trigger discharges, decrease the firing voltage between the X and Y electrodes, as shown in Eqs. (3) and (4). Also, they induce a strong discharge between the X and Y electrodes. V 0fXY ¼ V fXY DV
ð3Þ
V cXY ¼ V 0fXY þ DV
ð4Þ
here, V 0fXY is the new firing voltage between the X and Y electrodes and DV is the difference between the firing voltages before and after the trigger discharge. In particular, the priming particles, which are not located on any electrode and float in discharge vacuum area, decrease highly the firing voltages. After ramp reset, the charged particles distribute like Fig. 2(a). At this time, the priming particles remain in the discharged area. The address discharges occur in order of the scan lines. When the scan lines close in the time of the reset period, these priming particles will have an influence on the address discharges and can decrease the Vdata [6]. These priming particles, however, disappear as time goes by, as shown in Fig. 2(b), and the minimum Vdata voltage that needs to be discharged will increase because the priming effects do not have an influence on the address discharges. It is the reason of the increase of the Vdata voltage as the Ts increases. Fig. 3 shows the results whereby the address discharge delays were measured according to Ts, when the scan pulse width was 2.0 ls, Vsus was 170 V, Vxr was 160 V, Vxl was 165 V, Vramp was 230 V, and the Vdata voltage was fixed at 70 V in the conventional driving waveform, as shown in Fig. 1. In this test, the specification of test panel was 4-in. stripe-type VGA within He(69%)–Ne(27%)–Xe(4%) gas mixture. The cell pitch was 1.08 by 1.08 lm. The formative and statistical time lagged and the strength of the address discharge became weaker as the Ts increases because the minimum Vdata voltage rose because the address discharge had an effect on the priming particles. The larger the Ts was, the weaker the address discharge became and the delay time increased further. These results show that the address discharges are unstable as the Ts increases. The minimum Vdata voltage increases according to Ts, because the charge particles disappear and discharge time delay increases. Fig. 4 shows the results that the minimum Vdata voltages were measured according to the scan pulse width and Ts. The minimum Vdata voltage rapidly increased before Ts of 120 ls but slowly increased after Ts of 120 ls. For scan pulse widths of 2.0 ls and 0.8 ls, the minimum X
Y
X
+ + + + + + +
- - - - - - - - -
+ + + + + + + + + +
+
+ +
-
Y - - - - - - - - - - - -
-
Vdata +
A t0 Reset
+ + +
t1 Ts Address
Sustain
Fig. 1. The conventional driving waveform.
+ + + +
A
A
(a) at t0 (after reset)
(b) at t1 (before scan pulse input)
Fig. 2. The distribution of charged particles.
Y. Kim, S. Park / Displays 29 (2008) 369–375
371
Vramp
Vsus Y
Vsus
Vylevel
ΔVscan
Vyd
Vsc
X Vdata A t0
t2
Fig. 5. The driving waveform, which was proposed by Sakita, for highspeed addressing [2]. Fig. 3. The optical signal according to Ts when address discharges occur (Vdata = 70 V). The discharge signals were measured after the scan pulse and the Vdata voltage were applied.
60
Min. Vdata [V]
50 40
DV scan ¼ V yd V sc
30 Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
20 10 0 0.0
and main discharge between X and Y electrodes. The trigger discharge strongly occurs when the Vdata is supplied to the A electrode because VcAY is higher than VfAY as the Vdata. If we want to obtain a lower Vdata voltage, the scan voltage in the address period should be set lower scan voltage than the applied voltage of the Y electrode at time t0, as indicated in Fig. 1. Fig. 5 shows that the scan voltage in the driving waveform, which was proposed by Sakita, had lower scan voltage than the applied voltage of Y electrode at t0 [2]. Herein, the DVscan voltage is defined as Eq. (5).
0.2
0.4
0.6
0.8
1.0
Ts [ms] Fig. 4. The minimum Vdata voltage according to the scan pulse width using the conventional driving waveform [8].
ð5Þ
The Vyd and Vsc are the voltage of Y electrode at t0 (at the end of reset period) and t2 (at the time of scan pulse input) in Fig. 5, respectively. At first, to analyze the influence on the DVscan voltage, the minimum Vdata voltage was measured, when the DVscan voltage was 10 V (Vyd was 0 V and Vsc was 10 V) at the driving waveform, as shown in Fig. 5. Fig. 6 shows these experimental results. From these results, the minimum Vdata voltages rapidly increased before Ts of 120 ls and slowly increased like the 60
2.2. The driving waveform with the DVscan voltage As mentioned above, the address discharge is composed of the trigger discharge between the A and Y electrodes
50
Min. Vdata [V]
Vdata voltages were 21.5 V and 30.0 V at Ts of 10 ls and 25.0 V and 46.0 V at Ts of 120 ls, respectively. In the case of Ts of 1000 ls, the Vdata voltages were 27.5 V and 54.0 V, respectively. Therefore, in order to drive a PDP, the minimum Vdata voltage must be decided by the last scan line, because the Vdata is the highest voltage at Ts of 1.0 ms in these experimental results. If the scan pulse width is set at 2.0 ls for the driving VGA, the minimum Vdata voltage will be 27.5 V. If the pulse width is 1.2 ls, however, this voltage rises to 38.5 V. It increases rapidly to a high of 54.0 V at the width of 0.8 ls.
40 30 20 Pw=0.8µs Pw=1.2µs Pw=1.6µs
10 0 0.0
0.2
0.4
0.6
Pw=1.0µs Pw=1.4µs Pw=2.0µs
0.8
1.0
Ts [ms] Fig. 6. The minimum Vdata voltage according to a scan pulse width at the DVscan of 10 V.
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Y. Kim, S. Park / Displays 29 (2008) 369–375
conventional waveform. These minimum Vdata voltages were 19.0 V and 50.0 V, respectively, at a scan pulse width of 2.0 ls and 0.8 ls. These were the decrease of 8.5 V and 4.0 V from the conventional waveform, respectively. The scan voltage decreased by 10.0 V. However the minimum Vdata voltage just decreased 4.0 V, when the scan pulse width was 0.8 ls. These decreasing rates are insufficient for high-speed addressing with a scan pulse width of 0.8 ls. Consequently, a higher DVscan voltage is required. These DVscan voltages can be set the highest value without misaddressing of the OFF-cells. The maximum DVscan voltage that can be applied increases as the scan pulse width narrows [8]. The allowed maximum DVscan voltages of the first and last scan lines were 12.0 V and 15.5 V at a scan pulse width of 2.0 ls and 25.0 V and 33.5 V at a scan pulse width of 0.8 ls, respectively [8]. From these previous experimental results, we got the result that the applied DVscan voltage had to be increased according to the scan pulse input time (Ts) to achieve the high-speed driving for a PDP without misaddressing of the OFF-cells. 3. The principal of proposed driving waveform The higher DVscan voltage is, the lower minimum Vdata voltage becomes. However, the conventional scan voltage was set by the same DVscan voltage in all address period. If the same DVscan voltage is applied to all scan lines, as shown in Fig. 5, the minimum Vdata voltage should be decided by the last scan line. Because the highest value among the minimum Vdata voltage is the Vdata at the last scan line. On the other hand, the maximum DVscan voltage is decided by the misaddressing of the OFF-cells in the 1st scan line. If the DVscan voltage can be set to high, the minimum Vdata voltage could decrease more and more in spite of a narrower scan pulse width of 0.8 ls. However, the DVbscan cannot extremely be high because of misaddressing of the OFF-cells. So, the minimum Vdata voltage is limited. Therefore, the waveform, that had the linearly increased DVscan voltage according to the Ts, was proposed in Ref. [8], as shown in Fig. 7(a) and (b). The minimum Vdata voltage could be lowered by using the priming effects at low Ts and a high DVscan voltage at a high Ts. However, those results were not enough to reduce the minimum Vdata voltage for full HD PDP. So, the new driving waveform for high-speed addressing is proposed, as shown in Fig. 7(c) in this paper. The proposed waveform is that the DVscan voltage increases with log-type DVscan voltages shape as the Ts increases. In here, the amplitude of Vylevel voltage is not varied in all address period. The operating principle of the proposed driving waveform is explained as follows. For the compensation of the increase of the Vdata voltage as the Ts increased, the DVscan voltage continuously increased in the address period as the Ts increased, as shown in Fig. 7. The DVscanvoltages for Y1, . . . , Ym, . . . , and Yn are applied, as expressed by Eq. (6).
Y1 … Ym …
ΔVsc1 ΔVscm
Yn
ΔVscn
X A (a) The proposed driving waveform for high speed addressing
Y1
Ym
Yn
Y (b) The method that the scan voltage was supplied by a linear-type [8]
Y1 Y
Ym
Yn
(c) The method that the scan voltage was supplied by a log-type Fig. 7. The proposed waveform for high-speed addressing. The scan voltage was changed according to Ts.
DV sc1 < DV sc2 < < DV scm < < DV scn
ð6Þ
The priming particles decrease the firing voltages among the electrodes and the voltage of transition region. The firing voltages and voltages of transition regions continuously increase as Ts increases, because these particles disappear. The outline of the Vt closed curve that is the firing voltage and the transition region will go away from original point on the Vt plane, as shown in Fig. 8. The minimum Vdata voltage is defined by the lowest Vdata to induce the continuous sustain discharge for all ON-cells. Theoretically, this is voltage between the edge (VfAY) of Vt closed curve and transition region, as shown in Fig. 8(a) [9]. In the conventional driving waveform, the increasing voltages of the firing voltage and transition region were not compensated, as expressed by Fig. 8(a). So, the minimum Vdata voltage must be increased. On the other hand, in the proposed driving waveform, the increasing Vdata voltage can be compensated by the continuous increase of the scan voltage. In that time, the scan voltage is limited by the measured maximum DVscan voltage to avoid the misaddressing of OFF-cells.
Y. Kim, S. Park / Displays 29 (2008) 369–375 Transition region Vdatan(min) Vdatam(min) Tym
Vdata1(min) ΔVsc
40
Tyn
Ty1
VT1 VTm
Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=2.0µs
50
Min. V data [V]
VAY
373
30 20
VTn
10
VXY
(a) Conventional condition
0 0.0
0.2
0.4
Transition region VAY
Vdatan(min) Vdatam(min) Vdata1(min)
ΔVscn ΔVscm ΔVsc1 Ty1
Tym
Tyn
1.0
4.2. Log-type DVscan voltage
VTn VXY
(b) Proposed condition Fig. 8. Operating mechanism of the proposed waveform. In here, VT1, VTm and VTn are the Vt closed curves of 1st, mth and nth scan line, Ty1, Tym, Tyn are the transition region of the 1st, mth and nth scan line, Vdata1(min), Vdatam(min) and Vdatan(min) are the minimum data voltage of the 1st, mth and nth scan line, and DVsc1, DVscm and DVscn are the DVscan voltage of the 1st, mth and nth scan line, respectively.
4. Experimental results and discussion 4.1. Linear-type DVscan voltage In the previous waveform test [8], the dynamic Vdata margins were measured according to Ts and scan pulse width, when the DVscan voltage was linearly varied between 5 V and 20 V for the fabricated test panel, as shown in Eq. 7. The experimental results were shown in Fig. 9. DV scan ¼ 15T s þ 5
0.8
Fig. 9. The minimum Vdata voltage according to Ts. The applied DVscan voltage waveform is similar to equation in Eq. (7). The DVscan voltage is varied between 5 V and 20 V [8].
VT1 VTm
0.6 Ts [ms]
ð7Þ
From those experimental results, the dynamic Vdata margin, in the case of a scan pulse width of 2.0 ls, could not be obtained because of the discharge of OFF-cells at high Ts. The Vdata margins, however, could be obtained at another scan pulse widths. The minimum Vdata voltages were lowered as the DVscan voltage was increased, when these were compared with the conventional waveform in Fig. 4. In the case of a scan pulse width of 0.8 ls, the dynamic margin of the minimum Vdata was 39.5 V. This result showed a decrease of 14.5 V from the conventional driving waveform, which had the minimum Vdata of 54.0 V [8].
As we mentioned above, those results using the lineartype DVscan voltage waveforms were not enough to drive full HD PDP. Therefore, the two different driving waveforms with log-type DVscan Voltage, as shown in Fig. 7(c), were proposed and tested. The two applied DVscan voltage waveforms were approximated to Eqs. (8) and (9). The DVscan voltage in Eq. (9) is higher than that in Eq. (8). DV scan ¼ 4:2 lnð9T s Þ þ 10
ð8Þ
DV scan ¼ 4:2 lnð9T s Þ þ 20
ð9Þ
Fig. 10(a) and (b) show the measured minimum Vdata voltage in case of Eqs. (8) and (9), respectively. In Fig. 10(a), the dynamic Vdata margin could be obtained when the scan pulse widths were below 1.4 ls. In particular, the minimum Vdata voltage was 36.0 V at the scan pulse width of 0.8 ls and it was a decrease of 18.0 V when it was compared with the conventional waveform. This voltage was nearly constant over all ranges of Ts. In the case of Fig. 10(b), however, the dynamic margin was obtained when the scan pulse widths were below 0.8 ls. This is due to the misaddressing of the OFF-cells. The minimum Vdata voltage was 27.0 V. This result is a decrease of 27.0 V from the conventional waveform at the scan pulse width of 0.8 ls. Fig. 11 shows the experimental results, when the new driving waveform is compared with the conventional waveform and the proposed waveform by Sakita, at a scan pulse width of 0.8 ls. The dynamic minimum Vdata of the conventional waveform is 54.0 V and that of the proposed waveform by Sakita is 50.0 V. In the case of the proposed driving waveform, however, the minimum Vdata voltage was 27.0 V and there was a decrease of 27.0 V from the conventional waveform. So, these experimental results
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Y. Kim, S. Park / Displays 29 (2008) 369–375
60 50 Min. Vdata [V]
show the proposed driving waveform has the excellent address discharge characteristics.
Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
40
5. Conclusions
30 20 10 0 0.0
0.2
0.4
0.6 0.8 1.0 Ts [ms] (a) Whereby the ΔVscan voltage was varied as in Eq. (8)
60 Pw=0.8µs Pw=1.0µs Pw=1.2µs Pw=1.4µs Pw=1.6µs Pw=2.0µs
Min. Vdata [V]
50 40 30 20
Acknowledgement
10 0 0.0
0.2
0.4
0.6
0.8
1.0
Ts [ms] (b) Whereby the Vscan voltage was varied as in Eq. (9) Fig. 10. The minimum Vdata voltage according to Ts. The DVscan voltages were varied as in Eqs. (8) and (9).
50
40 Min. Vdata [V]
Priming effects can be used for driving PDP. The priming particles, however, which are generated in the reset period, disappeared after Ts is 120 ls, in these experiments. The minimum Vdata voltage continuously increased for the sustain discharges, because the charged particles in the vacuum quickly disappeared and the wall charges were slowly redistributed. In order to compensate for the increase of the minimum Vdata, the new driving waveform with the log-type DVscan voltage was proposed and tested. In testing the proposed waveform, a 4-in. panel was fabricated and a driving circuit was designed. Then, the minimum Vdata voltages were compared with the conventional waveform. In the case of a scan pulse width of 0.8 ls, the minimum Vdata voltage of the proposed waveform was 27.0 V and was a decrease of 27.0 V, when it was compared with the minimum Vdata of the conventional waveform. From these results, it was proved that the proposed waveform for the PDP was usable. If the new waveform is used for a driving PDP, the increase of the number of the subfields and the improvements of the gray-scale levels can be anticipated.
30 20 Conventional Vscan = -10V 10V Vscan= Vscan Linear Vscan Proposed Proposed
10 0 0.0
0.2
0.4
0.6
0.8
1.0
Ts [ms] Fig. 11. A comparison between the minimum Vdata voltages of the conventional and proposed waveform.
This work was also partly supported by the Brain Korea 21 (BK21) program of the Ministry of Education and supported by the ERC program of KOSEF (Grant R11-2000075-02002-0). References [1] Jae Sung Kim, Jin Ho Yang, Ki Woong Whang, A driving method for high-speed addressing in an AC PDP using priming effect, IEEE Trans. Electron Devices 51 (4) (2004) 548–553. [2] K. Sakita, K. Takayama, K. Awamoto, Y. Hashimoto, High-speed address driving waveform analysis using wall voltage transfer function for three terminal and Vt close curve in three-electrode surfacedischarge AC-PDP’s, SID Tech. Dig., 2001 (2001) 1022–1025. [3] M. Kasahara, M. Ishikawa, T. Morita, S. Inohara, New drive system for PDPs with improved image quality: plasma AI, SID Tech. Dig.,’99 (1999) 158–161. [4] M. Ishii, A. Gotoda, T. Shiga, K. Igarashi, S. Mikoshiba, Addresswhile-display drive scheme of AC PDP’s with 50 V scan and 20 V data pulses by use of erase addressing with space charge priming, Proc. IDW01 (2001) 817–820. [5] Jae Sung Kim, Jin Ho Yang, Tae Jun Kim, Ki Woong Whang, Comparison of electric field and priming particle effects on address discharge time lag and addressing characteristics of high-Xe content AC PDP, IEEE Trans. Plasma Sci. 31 (5) (2003) 1083–1090. [6] S.K. Lee, W.J. Kim, Y.J. Lee, Y.D. Kim, M.S. Kim, S.J. Moon, Y.H. Kwon, S.J. Yoo, J.D. Kim, Analysis of priming effect using Vt close curve, Proc. IDW02 (2002) 709–712. [7] Y.D. Kim, W.J. Kim, Y.J. Lee, S.K. Lee, M.S. Kim, S.J. Moon, Y.H. Kwon, S.J. Yoo, J.D. Kim, The relation between opposed firing and ramp reset voltage in AC-PDP driving waveform, Proc. IDW02 (2002) 717–720.
Y. Kim, S. Park / Displays 29 (2008) 369–375 [8] Y. Kim, S. Park, The improvement of the driving waveform for highspeed addressing, Displays, accepted, 2007.07. [9] Y. Kim, S. Park, Analysis of the influence of the address electrode width on high-speed addressing using the Vt close curve and dynamic Vdata margin, KIEE Int. Trans. Electrophys. Appl. 5-C (5) (2005) 183–190.
Yongduk Kim received the B.S., M.S. and Ph. D. degrees in Electrical Engineering from Kyungpook National University, Daegu, Korea, in 1995, 1997 and 2006, respectively. He is currently with the PDP R&D center of Orion PDP Co., Ltd., Gumi, Kyung-Buk, Korea. His research interests are the design of driving waveforms, driving circuits, and the analysis of plasma discharge for AC-PDP, micro-
electronics, motor technology.
375 control,
sensors
and
actuators,
and
MEMS
Sekwang Park received the B.S. degree in Electrical Engineering from Seoul National University, Seoul, Korea, in 1976, and M.S. and Ph.D. degrees in electrical engineering from Case Western Reserve University, Cleveland, OH, U.S.A. in 1984 and 1988, respectively. He was project leader of L. VAD Technology, U.S.A., from 1988 until 1989. He is currently a Professor in the Department of Electrical Engineering at Kyungpook National University. His research interests are the driving waveforms and circuits for PDP, microelectronics, sensors and actuators using MEMS technology, especially, pressure sensors, flow sensors, temperature sensors, and humidity sensors.