- Email: [email protected]
A new dual bridge multilevel dc-link inverter topology
Electrical Power and Energy Systems 45 (2013) 376–383
Contents lists available at SciVerse ScienceDirect
Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes
A new dual bridge multilevel dc-link inverter topology S. Thamizharasan a,⇑, J. Baskaran b, S. Ramkumar c, S. Jeevananthan d a
Surya Group of Institutions, School of Engineering and Technology, Villupuram, India Adhiparasakthi Engineering College, Melmaruvathur, India c RMD Engineering College, Chennai, India d Pondicherry Engineering College, Puducherry, India b
a r t i c l e
i n f o
Article history: Received 25 June 2012 Received in revised form 12 September 2012 Accepted 26 September 2012 Available online 5 November 2012 Keywords: Multilevel dc-link inverter (MLDCLI) Switch count Total harmonic distortion (THD) Field programmable gate array (FPGA)
a b s t r a c t This paper attempts to construct a new hybrid multilevel dc-link inverter (MLDCLI) topology with a focus to synthesize a higher quality sinusoidal output voltage. The idea emphasizes the need to reduce the switch count considerably and thereby claim its superiority over the existing multilevel inverter (MLI) configurations. The structure incorporates a new module along with a differently used H-bridge that facilitates the increase in levels with much lower switch counts. The proposed dual bridge MLDCLI (DBMLDCLI) is evaluated using phase disposition (PD) multi-carrier pulse width modulation (MC-PWM) strategy in a filed programmable gate array (FPGA) platform. The MATLAB/System generator based simulation results validated through FPGA based prototype for a typical output level exhibit the drastic enhancement in the quality of output voltage. The total harmonic distortion (THD) obtained using a harmonic spectrum reveals the mitigation of the frequency components of output voltage other than the fundamental and paves the way to open a new avenue for nurturing innovative applications in this domain. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction MLIs are preferred for high power medium voltage applications owing allegiance to their inheritance of reduced harmonic content in the output side, lower blocking voltage in the switching devices and diminished losses due to less commutation stresses [1–8]. They appear to be an attractive solution for high power drives and reactive power compensation applications due to their ability to offer higher voltages from medium voltage dc-link and less distorted output voltage [9–17]. The introduction of a MLDCLI structure [18] invades far reaching consequences to orient an improved performance. It groups itself in either of the categories neutral point clamped phase leg [1,19], flying capacitor phase leg [20,21] or cascaded half bridge cells [22] with each cell having its own dc sources. These inverters reduce the number of switches and gate drivers as the number of voltage level increases. However, they evince inconveniences in their operation with balancing capacitor voltages [5,23]. A new variety of MLDCLI coined as series parallel switched multilevel dc-link inverter (SPSMLDCLI) synthesizes a nearly distortion less sinusoidal output voltage which uses lower number of sources, power switches and eliminates the necessity of capacitors [24].
⇑ Corresponding author. Tel.: +91 9443145013. E-mail address: [email protected] (S. Thamizharasan). 0142-0615/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.ijepes.2012.09.024
It is in this direction that there is a charter to develop a new class of MLDCLI topology namely dual bridge multilevel dc link inverter (DBMLDCLI) which requires a lower switch count to obtain a nearly sinusoidal voltage. The structure incorporates a module along with a differently used H-bridge that facilitates the increase in levels in addition to another H-bridge which account for the bi-directional power flow. The proposed DBMLDCLI is evaluated both using simulation and a suitable prototype. It seeks the role of phase disposition (PD) multi-carrier pulse width modulation (MC-PWM) strategy implemented using a Xilinx based system generator facility available as a toolbox in MATLAB R2010a in conjunction with a FPGA based processor [25].
2. Proposed topology A MLDCLI in its very generic form shown in Fig. 1 is constituted of two H-bridges and a number of distinctive modules depending on the level requirements. It depicts the general configuration of the proposed MLDCLI structure coined as DBMLDCLI through which it is viable to realize as many desired levels. While the modules and the first H-bridge serve to increase the level of the dc-link voltage, the second H-bridge provides bi-directional power flow through the load. The first bridge is connected in series with as many modules for every six level increase, with each module intertwined with a switch in series with the source, the combination shunted through an anti parallel diode. The precise number of
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Fig. 1. Generalized structure of DBMLDCLI.
Table 1 Comparison between topologies for 15 level. Multilevel inverter structure
Main switches Bypass diodes Clamping diodes DC split capacitors Clamping capacitors DC sources Total
Cascaded H-bridge
Diode clamped
28 – – – – 7 35
28 – 24 6 – 1 59
Flying capacitor
28 – – 6 12 1 47
Table 2 Comparison in terms of power components used for different level. No. of Levels
15 21 27 33 39
No. of power switches
No. of bypass diodes
SPSMLDCLI
DBMLDCLI
SPSMLDCLI
DBMLDCLI
10 13 16 19 22
10 11 12 13 14
1 1 1 1 1
2 3 4 5 6
Multilevel dc-link inverter
Proposed topology
Cascaded half bridge
Diode clamped
Flying capacitor
18 – – – – 7 25
18 – 12 6 – 1 37
18 – – 6 6 1 31
10 2 – – – 3 15
levels of output voltage that a DBMLDCLI can synthesize is expressed using a relation (2(3n + 1) + 1) where n is the number of voltage sources excluding V0, if arranged in the ratio V0:Vn = 1:3. It contributes to decreasing the switching losses, increasing the efficiency and eliminating the consequent effects of de-rating. A detailed comparison of the switch and source requirements is tabulated in Table 1 to bring out the reduction in the count that the proposed DBMLDCLI enjoys over the existing MLI topologies for a typical case of fifteen level output. Table 2 narrates comparison
Fig. 2. DBMLDCLI operating mode-level 1 (±50 V).
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Fig. 3. DBMLDCLI operating mode-level 2 (±100 V).
Fig. 4. DBMLDCLI operating mode-level 3 (±150 V).
Fig. 5. DBMLDCLI operating mode-level 4 (±200 V).
between SPSMLDCLI and the proposed topology in terms of components count. The highlight of the new structure is that it only requires only as many as ten switches which is around 74% less when compared with the basic MLI topologies and 40% with MLDCLIs as seen from
Table 1. It is interesting to drive home the fact that for a similar conventional topology the count is as high as 59. The component count can further be reduced to eleven devices if the voltage sources are arranged in the ratio V0:V1:V2:...:Vn = 1:21:22:23:...:2n with three voltage sources excluding V0. Now, the exact number
S. Thamizharasan et al. / Electrical Power and Energy Systems 45 (2013) 376–383
Fig. 6. DBMLDCLI operating mode-level 5 (±250 V).
Fig. 7. DBMLDCLI operating mode-level 6 (±300 V).
Fig. 8. DBMLDCLI operating mode-level 7 (±350 V).
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Fig. 12. Inductive load current. Fig. 9. Switching pattern. Table 3 Fundamental voltage Vs THD. Output fundamental voltage (V)
THD (%)
100 120 140 160 180 200 220
DBMLDCLI
CHBMLDCLI
19.28 15.60 12.80 12.14 9.70 9.67 8.18
39.87 37.85 33.69 26.74 21.96 22.33 20.95
P of levels in the output voltage is given by the relation ð2 ni¼1 2i þ 3Þ where n is the number of voltage sources excluding V0, if arranged in the ratio V0:Vn = 1:2n. For convenience to explain the operating modes for various levels, the dc link structure is represented by fixed dc source in the upcoming diagrams. The operation for each level of a fifteen level inverter with V0:V1:V2 = (50:150:150) V along with positive and negative half cycles is explained pictorially through Figs. 2–8. It is seen from Fig. 3 that the devices S03, S04, De1 and De2 in the dc-link circuit and either the pair S1–S2 or pair S3–S4 in the H-bridge alternately are required to conduct to extract the first level of the output voltage and goes through a similar sequence for other levels. The pattern of the output voltage shown in Fig. 9 clearly shows the devices that conduct for the various levels of the output voltage.
No. of output voltage levels
Fig. 10. Dc-link voltage waveform.
90 80 70 60 50 40 30 20 10 0
3
4
5
6
7
8
9
10
11
12
13
14
No. of DC sources Fig. 13. Comparison of output voltage level versus dc sources.
3. Simulation The proposed DBMLDCLI topology is simulated on a MATLAB platform using Insulated gate bipolar Transistor (IGBT) power
switches for the second H-bridge and MOSFET for the first H-bridge in the dc-link. Since these two bridges operated at two different voltage ratings, MOSFETs and IGBTs are used in order to distin-
Fig. 11. Output voltage waveform and harmonic spectrum.
S. Thamizharasan et al. / Electrical Power and Energy Systems 45 (2013) 376–383
381
Fig. 14. Prototype of DBMLDCI.
guish the operation. However, the two bridges require only any voltage controlled device to accomplish the operation. The cell voltages are chosen in the ratio 1:3 (V0 = 50, V1 = V2 = 150 V) in order to obtain a variable ac voltage at the line frequency across a 110 X resistive load. It uses a PD-MC-PWM technique with a carrier frequency of 4 kHz. While the multilevel dc-link voltage obtained using the distinctive modules and the first H-bridge is depicted in Figs. 10 and 11 show the unfolded ac output voltage waveform produced by the second H-bridge and respective harmonic spectrum. The output current waveform for an RL load of 5 mH inductance is shown in Figs. 12.
Fig. 16. Block diagram of proposed topology.
The variation of the THD with respect to fundamental component over a viable range of modulation indices is depicted in Table 3 and observed that as the output voltage magnitude increases the THD decreases. It is noteworthy to point out that the values of THD are significantly lower over a range of output targets when compared with a cascaded half bridge MLDCLI (CHBMLDCLI), which is perhaps the next best variety in terms of switch count for a similar output level. Fig. 13 shows the graph between No. of dc sources and No. of output voltage levels.
4. Hardware implementation
Fig. 15. Pulse generation methodology.
A prototype seen in Fig. 14 is constructed using similar power switches as those used in simulation to operate under similar specifications. The experimental arrangement is constituted of MOSFETs (IRF 840), bypass diode (BYQ 28E), IGBTs (FIO 5O12BD) and a resistive inductive load of 110 X and 5 mH respectively. The MC-PWM pulses are generated using the Xilinx based system generator facility available as a toolbox in MATLAB R2010a. The system generator involves a tailor made procedure that imbibes a method through which the time at which the rising and trailing edge pulses occur can be allowed to vary, the overlap of which serves to extract the desired PWM pulse. The approach explaining the pulse generation methodology and the associated flow diagram are shown in Figs. 15 and 16. It follows from the sequence that once the pulses are obtained the circuit schematics are penetrated where from the very high speed integrated circuit hardware description language (VHDL) code suitable for down loading on the portals of a Spartan based FPGA is inscribed. The pulses are buffered to fire the power switches in the DBMLDCLI. The gating signals captured through Tektronix TPS 2024 scope are shown in Fig. 17. The dc-link and the load voltage waveforms along with the harmonic spectrum corresponding to a modulation index of 0.9 and an output of 220 V are portrayed in Fig. 18. The fact that the same fundamental output is obtained for the designed output level both using simulation and hardware with comparable THD values goes to validate the PWM technique in addition to highlighting the practical feasibility of the proposed MLI configuration. Table 4 authenticates the simulated results through prototype results. The output current waveform for the same values of R-L load as that used in simulation is seen Fig. 19.
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Fig. 17. Gating signals (a) modules (b) first H-bridge and (c) second H-bridge.
Fig. 19. Output current waveform for RL load.
5. Conclusion
Fig. 18. (a) Dc-link voltage and load voltage waveforms and (b) load voltage spectrum.
An MLDCLI structure suitably built using a dual bridge configuration has been proposed with a view to reduce the number of power switches to synthesize an increasing level of output voltages. The topology has been developed using an appropriate choice of voltage ratios between the constituent parts in the power module. The accomplishment of the desired results has been found to add a feather to vindicate the technology revolution in progress. The higher quality of output voltage that can be extracted using the new structure will go a long way in insinuating greater horizons of power converter interfaces in the automated world.
References Table 4 Comparison chart. V01 (V)
Simulation THD (%)
Hardware THD (%)
100 120 140 160 180 200 220
19.28 15.6 12.8 12.14 9.7 9.67 8.18
21.26 14.36 14.12 13.23 9.12 9.50 7.77
[1] Rodriguez J, La Jih-Sheng, Peng Fang Zheng. Multilevel inverters: a survey of topologies, controls, and applications. IEEE Trans Ind Electron 2002;49:724–38. [2] Lai Jih-Sheng, Peng Fang Zheng. Multilevel converters – a new breed of power converters. IEEE Trans Ind Appl 1996;32:509–17. [3] Tolbert LM, Peng Fang Zheng, Habetler TG. Multilevel converters for large electric drives. IEEE Trans Ind Appl 1999;35:36–44. [4] Stemmler H, Guggenbach P. Configurations of high-power voltage source inverter drives. In: Proceedings of IEEE international conference, vol. 5; 1993. p. 7–14. [5] Fang Zheng Peng, Jih-Sheng Lai, McKeever J, VanCoevering J. A multilevel voltage-source converter system with balanced Dc voltages. In: Proceedings of IEEE international conference, vol. 2; 1995. p. 1144–50.
S. Thamizharasan et al. / Electrical Power and Energy Systems 45 (2013) 376–383 [6] Nabae A, Takahashi I, Akagi H. A new neutral-point clamped PWM inverter. IEEE Trans Ind Appl 1981;17:518–23. [7] Manjrekar MD, Steimer PK, Lipo TA. Hybrid multilevel power conversion system: a competitive solution for high-power applications. IEEE Trans Ind Appl 2000;36:834–41. [8] Meynard TA et al. Multicell converters: derived topologies. IEEE Trans Ind Electron 2002;49:978–87. [9] Carpita M, Marchesoni M, Pellerin M, Moser D. Multilevel converter for traction applications: small-scale prototype tests results. IEEE Trans Ind Electron 2008;55:2203–12. [10] Choi NS, Cho GC, Cho GH. Modeling and analysis of a static VAR compensator using multilevel voltage source inverter. In: Proceedings of IEEE international conference 1993; p. 901–8. [11] Shuai Lu, Corzine KA. Advanced control and analysis of cascaded multilevel converters based on P-Q compensation. IEEE Trans Ind Electron 2007;22:1242–52. [12] Bernet S. Recent developments of high power converters for industry and traction applications. IEEE Trans Ind Electron 2000;15:1102–17. [13] Krug D, Bernet S, Fazel SS, Jalili K, Malinowski M. Comparison of 2.3 KV medium-voltage multilevel converters for industrial medium-voltage drives. IEEE Trans Ind Electron 2007;54:2979–92. [14] Moreno-Munoz A, De-La-Rosa JJG, Lopez-Rodriguez MA, Flores-Arias JM, Bellido-Outerino FJ, Ruiz-de-Adana M. Improvement of power quality using distributed generation. Int J Electr Power Energy Syst 2010;32(10):1069–76. [15] Senthil Kumar N, Gokulakrishnan J. Impact of FACTS controllers on the stability of power systems connected with doubly fed induction generators. Int J Electr Power Energy Syst 2011;33(5):1172–84.
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[16] Munduate A, Figueres E, Garcera G. Robust model-following control of a threelevel neutral point clamped shunt active filter in the medium voltage range. Int J Electr Power Energy Syst 2009;31(10):577–88. [17] EL- Kholy EE, EL-Sabbe A, El-Hefnawy A, Mharo HM. Three-phase active power filter based on current controlled voltage source inverter. Int J Electr Power Energy Syst 2006;28(8):537–47. [18] Gui-Jia Su. Multilevel dc-link inverter. IEEE Trans Ind Appl 2005;41: 848–54. [19] Marchesoni M, Tenca P. Diode-clamped multilevel converters: a practicable way to balance dc-link voltages. IEEE Trans Ind Electron 2002;49:752–65. [20] Yuan Xiaoming, Stemmler H, Barbi I. Investigation on the clamping voltage self-balancing of the three-level capacitor clamping inverter. In: Proceedings of IEEE international conference vol. 2; 1999 p.1059–64. [21] Escalante MF, Vannier JC, Arzande. A flying capacitor multilevel inverters and DTC motor drive applications. IEEE Trans Ind Electron 2002;49:809–15. [22] Kouro S et al. Recent advances and industrial applications of multilevel converters. IEEE Trans Ind Electron 2010;57:2553–80. [23] Peng Fang Zheng. A generalized multilevel inverter topology with self voltage balancing. IEEE Tran Ind Appl 2001;37:611–8. [24] Ramkumar S, Kamaraj V, Thamizharasan S, Jeevananthan S. A new series parallel switched multilevel dc-link inverter topology. Int J Electr Power Energy Syst 2012;36:93–9. [25] http://www.xilinx.com.
Contents lists available at SciVerse ScienceDirect
Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes
A new dual bridge multilevel dc-link inverter topology S. Thamizharasan a,⇑, J. Baskaran b, S. Ramkumar c, S. Jeevananthan d a
Surya Group of Institutions, School of Engineering and Technology, Villupuram, India Adhiparasakthi Engineering College, Melmaruvathur, India c RMD Engineering College, Chennai, India d Pondicherry Engineering College, Puducherry, India b
a r t i c l e
i n f o
Article history: Received 25 June 2012 Received in revised form 12 September 2012 Accepted 26 September 2012 Available online 5 November 2012 Keywords: Multilevel dc-link inverter (MLDCLI) Switch count Total harmonic distortion (THD) Field programmable gate array (FPGA)
a b s t r a c t This paper attempts to construct a new hybrid multilevel dc-link inverter (MLDCLI) topology with a focus to synthesize a higher quality sinusoidal output voltage. The idea emphasizes the need to reduce the switch count considerably and thereby claim its superiority over the existing multilevel inverter (MLI) configurations. The structure incorporates a new module along with a differently used H-bridge that facilitates the increase in levels with much lower switch counts. The proposed dual bridge MLDCLI (DBMLDCLI) is evaluated using phase disposition (PD) multi-carrier pulse width modulation (MC-PWM) strategy in a filed programmable gate array (FPGA) platform. The MATLAB/System generator based simulation results validated through FPGA based prototype for a typical output level exhibit the drastic enhancement in the quality of output voltage. The total harmonic distortion (THD) obtained using a harmonic spectrum reveals the mitigation of the frequency components of output voltage other than the fundamental and paves the way to open a new avenue for nurturing innovative applications in this domain. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction MLIs are preferred for high power medium voltage applications owing allegiance to their inheritance of reduced harmonic content in the output side, lower blocking voltage in the switching devices and diminished losses due to less commutation stresses [1–8]. They appear to be an attractive solution for high power drives and reactive power compensation applications due to their ability to offer higher voltages from medium voltage dc-link and less distorted output voltage [9–17]. The introduction of a MLDCLI structure [18] invades far reaching consequences to orient an improved performance. It groups itself in either of the categories neutral point clamped phase leg [1,19], flying capacitor phase leg [20,21] or cascaded half bridge cells [22] with each cell having its own dc sources. These inverters reduce the number of switches and gate drivers as the number of voltage level increases. However, they evince inconveniences in their operation with balancing capacitor voltages [5,23]. A new variety of MLDCLI coined as series parallel switched multilevel dc-link inverter (SPSMLDCLI) synthesizes a nearly distortion less sinusoidal output voltage which uses lower number of sources, power switches and eliminates the necessity of capacitors [24].
⇑ Corresponding author. Tel.: +91 9443145013. E-mail address: [email protected] (S. Thamizharasan). 0142-0615/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.ijepes.2012.09.024
It is in this direction that there is a charter to develop a new class of MLDCLI topology namely dual bridge multilevel dc link inverter (DBMLDCLI) which requires a lower switch count to obtain a nearly sinusoidal voltage. The structure incorporates a module along with a differently used H-bridge that facilitates the increase in levels in addition to another H-bridge which account for the bi-directional power flow. The proposed DBMLDCLI is evaluated both using simulation and a suitable prototype. It seeks the role of phase disposition (PD) multi-carrier pulse width modulation (MC-PWM) strategy implemented using a Xilinx based system generator facility available as a toolbox in MATLAB R2010a in conjunction with a FPGA based processor [25].
2. Proposed topology A MLDCLI in its very generic form shown in Fig. 1 is constituted of two H-bridges and a number of distinctive modules depending on the level requirements. It depicts the general configuration of the proposed MLDCLI structure coined as DBMLDCLI through which it is viable to realize as many desired levels. While the modules and the first H-bridge serve to increase the level of the dc-link voltage, the second H-bridge provides bi-directional power flow through the load. The first bridge is connected in series with as many modules for every six level increase, with each module intertwined with a switch in series with the source, the combination shunted through an anti parallel diode. The precise number of
377
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Fig. 1. Generalized structure of DBMLDCLI.
Table 1 Comparison between topologies for 15 level. Multilevel inverter structure
Main switches Bypass diodes Clamping diodes DC split capacitors Clamping capacitors DC sources Total
Cascaded H-bridge
Diode clamped
28 – – – – 7 35
28 – 24 6 – 1 59
Flying capacitor
28 – – 6 12 1 47
Table 2 Comparison in terms of power components used for different level. No. of Levels
15 21 27 33 39
No. of power switches
No. of bypass diodes
SPSMLDCLI
DBMLDCLI
SPSMLDCLI
DBMLDCLI
10 13 16 19 22
10 11 12 13 14
1 1 1 1 1
2 3 4 5 6
Multilevel dc-link inverter
Proposed topology
Cascaded half bridge
Diode clamped
Flying capacitor
18 – – – – 7 25
18 – 12 6 – 1 37
18 – – 6 6 1 31
10 2 – – – 3 15
levels of output voltage that a DBMLDCLI can synthesize is expressed using a relation (2(3n + 1) + 1) where n is the number of voltage sources excluding V0, if arranged in the ratio V0:Vn = 1:3. It contributes to decreasing the switching losses, increasing the efficiency and eliminating the consequent effects of de-rating. A detailed comparison of the switch and source requirements is tabulated in Table 1 to bring out the reduction in the count that the proposed DBMLDCLI enjoys over the existing MLI topologies for a typical case of fifteen level output. Table 2 narrates comparison
Fig. 2. DBMLDCLI operating mode-level 1 (±50 V).
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Fig. 3. DBMLDCLI operating mode-level 2 (±100 V).
Fig. 4. DBMLDCLI operating mode-level 3 (±150 V).
Fig. 5. DBMLDCLI operating mode-level 4 (±200 V).
between SPSMLDCLI and the proposed topology in terms of components count. The highlight of the new structure is that it only requires only as many as ten switches which is around 74% less when compared with the basic MLI topologies and 40% with MLDCLIs as seen from
Table 1. It is interesting to drive home the fact that for a similar conventional topology the count is as high as 59. The component count can further be reduced to eleven devices if the voltage sources are arranged in the ratio V0:V1:V2:...:Vn = 1:21:22:23:...:2n with three voltage sources excluding V0. Now, the exact number
S. Thamizharasan et al. / Electrical Power and Energy Systems 45 (2013) 376–383
Fig. 6. DBMLDCLI operating mode-level 5 (±250 V).
Fig. 7. DBMLDCLI operating mode-level 6 (±300 V).
Fig. 8. DBMLDCLI operating mode-level 7 (±350 V).
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Fig. 12. Inductive load current. Fig. 9. Switching pattern. Table 3 Fundamental voltage Vs THD. Output fundamental voltage (V)
THD (%)
100 120 140 160 180 200 220
DBMLDCLI
CHBMLDCLI
19.28 15.60 12.80 12.14 9.70 9.67 8.18
39.87 37.85 33.69 26.74 21.96 22.33 20.95
P of levels in the output voltage is given by the relation ð2 ni¼1 2i þ 3Þ where n is the number of voltage sources excluding V0, if arranged in the ratio V0:Vn = 1:2n. For convenience to explain the operating modes for various levels, the dc link structure is represented by fixed dc source in the upcoming diagrams. The operation for each level of a fifteen level inverter with V0:V1:V2 = (50:150:150) V along with positive and negative half cycles is explained pictorially through Figs. 2–8. It is seen from Fig. 3 that the devices S03, S04, De1 and De2 in the dc-link circuit and either the pair S1–S2 or pair S3–S4 in the H-bridge alternately are required to conduct to extract the first level of the output voltage and goes through a similar sequence for other levels. The pattern of the output voltage shown in Fig. 9 clearly shows the devices that conduct for the various levels of the output voltage.
No. of output voltage levels
Fig. 10. Dc-link voltage waveform.
90 80 70 60 50 40 30 20 10 0
3
4
5
6
7
8
9
10
11
12
13
14
No. of DC sources Fig. 13. Comparison of output voltage level versus dc sources.
3. Simulation The proposed DBMLDCLI topology is simulated on a MATLAB platform using Insulated gate bipolar Transistor (IGBT) power
switches for the second H-bridge and MOSFET for the first H-bridge in the dc-link. Since these two bridges operated at two different voltage ratings, MOSFETs and IGBTs are used in order to distin-
Fig. 11. Output voltage waveform and harmonic spectrum.
S. Thamizharasan et al. / Electrical Power and Energy Systems 45 (2013) 376–383
381
Fig. 14. Prototype of DBMLDCI.
guish the operation. However, the two bridges require only any voltage controlled device to accomplish the operation. The cell voltages are chosen in the ratio 1:3 (V0 = 50, V1 = V2 = 150 V) in order to obtain a variable ac voltage at the line frequency across a 110 X resistive load. It uses a PD-MC-PWM technique with a carrier frequency of 4 kHz. While the multilevel dc-link voltage obtained using the distinctive modules and the first H-bridge is depicted in Figs. 10 and 11 show the unfolded ac output voltage waveform produced by the second H-bridge and respective harmonic spectrum. The output current waveform for an RL load of 5 mH inductance is shown in Figs. 12.
Fig. 16. Block diagram of proposed topology.
The variation of the THD with respect to fundamental component over a viable range of modulation indices is depicted in Table 3 and observed that as the output voltage magnitude increases the THD decreases. It is noteworthy to point out that the values of THD are significantly lower over a range of output targets when compared with a cascaded half bridge MLDCLI (CHBMLDCLI), which is perhaps the next best variety in terms of switch count for a similar output level. Fig. 13 shows the graph between No. of dc sources and No. of output voltage levels.
4. Hardware implementation
Fig. 15. Pulse generation methodology.
A prototype seen in Fig. 14 is constructed using similar power switches as those used in simulation to operate under similar specifications. The experimental arrangement is constituted of MOSFETs (IRF 840), bypass diode (BYQ 28E), IGBTs (FIO 5O12BD) and a resistive inductive load of 110 X and 5 mH respectively. The MC-PWM pulses are generated using the Xilinx based system generator facility available as a toolbox in MATLAB R2010a. The system generator involves a tailor made procedure that imbibes a method through which the time at which the rising and trailing edge pulses occur can be allowed to vary, the overlap of which serves to extract the desired PWM pulse. The approach explaining the pulse generation methodology and the associated flow diagram are shown in Figs. 15 and 16. It follows from the sequence that once the pulses are obtained the circuit schematics are penetrated where from the very high speed integrated circuit hardware description language (VHDL) code suitable for down loading on the portals of a Spartan based FPGA is inscribed. The pulses are buffered to fire the power switches in the DBMLDCLI. The gating signals captured through Tektronix TPS 2024 scope are shown in Fig. 17. The dc-link and the load voltage waveforms along with the harmonic spectrum corresponding to a modulation index of 0.9 and an output of 220 V are portrayed in Fig. 18. The fact that the same fundamental output is obtained for the designed output level both using simulation and hardware with comparable THD values goes to validate the PWM technique in addition to highlighting the practical feasibility of the proposed MLI configuration. Table 4 authenticates the simulated results through prototype results. The output current waveform for the same values of R-L load as that used in simulation is seen Fig. 19.
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Fig. 17. Gating signals (a) modules (b) first H-bridge and (c) second H-bridge.
Fig. 19. Output current waveform for RL load.
5. Conclusion
Fig. 18. (a) Dc-link voltage and load voltage waveforms and (b) load voltage spectrum.
An MLDCLI structure suitably built using a dual bridge configuration has been proposed with a view to reduce the number of power switches to synthesize an increasing level of output voltages. The topology has been developed using an appropriate choice of voltage ratios between the constituent parts in the power module. The accomplishment of the desired results has been found to add a feather to vindicate the technology revolution in progress. The higher quality of output voltage that can be extracted using the new structure will go a long way in insinuating greater horizons of power converter interfaces in the automated world.
References Table 4 Comparison chart. V01 (V)
Simulation THD (%)
Hardware THD (%)
100 120 140 160 180 200 220
19.28 15.6 12.8 12.14 9.7 9.67 8.18
21.26 14.36 14.12 13.23 9.12 9.50 7.77
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