A new topology for multilevel inverter considering its optimal structures

Electric Power Systems Research 103 (2013) 145–156

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A new topology for multilevel inverter considering its optimal structures Ebrahim Babaei ∗ , Ali Dehqan, Mehran Sabahi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

a r t i c l e

i n f o

Article history: Received 21 November 2012 Received in revised form 18 March 2013 Accepted 2 June 2013 Available online 26 June 2013 Keywords: Cascaded multilevel inverter Full-bridge converter Multilevel inverter

a b s t r a c t In this paper, a new topology for multilevel inverters is proposed. The proposed topology consists of a basic unit and a full bridge converter. An extended topology is proposed and for the extended topology, three algorithms have been proposed to determine magnitudes of dc voltage sources. The proposed topology from viewpoint of the number of switches, the number of dc voltage sources, and the number of output voltage steps are optimized. The optimal structures for the extended topology are investigated for various objectives such as minimum number of switches and dc voltage sources for producing the maximum output voltage steps. Both simulation results and experimental verification of the proposed multilevel inverter for a single-phase 19-level multilevel inverter are presented. © 2013 Elsevier B.V. All rights reserved.

1. Introduction Power electronic converters are widely used in industrial power conversion systems for power industry applications and drives. When the power level is increased, the voltage level accordingly to achieve satisfactory performance increases. In recent years, nominal voltage of high voltage semiconductors with high switching speed, such as insulated-gate bipolar transistor (IGBT) has increased. However, there is still a need to series connection of switching devices. In recent years, multilevel inverters have received more and more attention because of their capability of high voltage operation, high efficiency and low electromagnetic interference (EMI) [1]. The desired output of a multilevel inverter is synthesized by several sources of dc voltages. With an increasing number of dc voltage sources, the inverter voltage output waveform approaches a nearly sinusoidal waveform while using a fundamental frequency switching scheme. These results in low switching losses, and because of several dc sources, the switches experience lower voltage stresses [2]. In comparison with the traditional two-level converters and by increasing the number of dc voltage sources (steps), the small voltage steps lead to the production of high power quality waveforms, lower harmonic components, lower voltage ratings of devices, lower switching losses, higher efficiency, and also reduction of dv/dt

∗ Corresponding author. Tel.: +98 411 3300819; fax: +98 411 3300819. E-mail addresses: [email protected], [email protected] (E. Babaei), [email protected] (A. Dehqan), [email protected] (M. Sabahi). 0378-7796/$ – see front matter © 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.epsr.2013.06.001

stresses on the load and gives the possibility of working with low speed semiconductors [3,4]. Famous multilevel inverters can be classified as two classes, one multilevel with common dc source such as diode clamped and flying capacitor and second multilevel with isolated dc source like cascade H-bridge (CHB) [5]. New family of multilevel inverter and the topologies where the input dc voltages are the same that investigated in [6–11]. Multilevel inverters have some disadvantages. One particular disadvantage is the great number of power semiconductor switches requirements. Although low voltage rate switches can be utilized in a multilevel inverter, each switches require a related gate driver circuits. This may cause the overall system to be more expensive and complex. So, in practical implementation, reducing the number of switches and gate driver circuits is very important [6,7]. A new topology of cascaded multilevel inverter with reduced number of switches and insulated gate driver circuit has been presented in [8]. In addition, to produce all steps (odd and even) at the output voltage, a procedure for calculating the required dc voltage sources is proposed. It is important to mention that the presented topology in [8] needs four high rating switches for output side Hbridge. The presented unit in [8] requires bi-directional switches with the capability of blocking voltage and conducting current in both directions. In [9] a new topology of cascaded multilevel inverter has been presented. In [9], the optimal structures for presented topology have been investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156 Table 1 Values of vo and vo for permitted states of the switches. Switches states

Fig. 1. Proposed submultilevel topology.

steps. Two new algorithms to determine the magnitude of dc voltage sources have been presented. This topology needs no H-bridge at the output side, but needs bi-directional switches. A new three-phase multilevel inverter specially suited for electrical drive applications has been presented in [10]. Unlike the CHB inverters, this topology is based on cascaded power cells in which each cell utilizes two series inverter legs. A detailed analysis of the structure and the development of design equations for the load voltage with Nstep steps have been carried out using pulsewidth-modulation phase-shifted multicarrier modulation. The high number of dc voltage sources in presented topology in [10] is a disadvantage for this structure that leads to increase in the total cost of the inverter. In [12] a new topology of high level multilevel inverter has been presented. The problem is focused on minimizing the number of power transistors for a given number of levels. Different combinations of topologies are presented, and the corresponding mathematical relations have been derived. This paper shows optimized curves to obtain the relation between a minimum numbers of power semiconductors required for a given number of levels. The presented topology in [12] requires some bi-directional switches with the capability of blocking voltage and conducting current in both directions. In [13] a new class of multilevel inverters based on a multilevel dc link (MLDCL) and a bridge inverter has been presented. An MLDCL can be a diode-clamped phase leg, a flying-capacitor phase leg, or cascaded half-bridge cells in which the cells have their own dc sources. Despite a higher total VA rating of the switches, the MLDCL inverters can still cost less due to the savings from the eliminated gate drivers and from fewer assembly steps because of the substantially reduced number of components, which also leads to a smaller size and volume. It is important to mention that the presented topology in [13] needs four high rating switches for output side H-bridge. This paper proposes a new topology for cascaded multilevel inverters that produces a large number of steps with a low number of power switches. Three different procedures to calculate required magnitudes of dc voltage sources are proposed. In addition, the structure of the proposed topology is optimized for various aims. A comparative analysis with some recently presented topologies and conventional structures is also provided. Finally, the paper includes the simulation and experimental results of single-phase 19-level multilevel inverter to prove the feasibility of the proposed multilevel inverter. 2. Proposed topology Fig. 1 shows the proposed topology for a submultilevel inverter, which consists of the basic unit and a full-bridge converter. The basic unit consists of n dc voltage sources. Each of dc voltage source is connected to the output by two switches and can produce a zero or positive polarity voltage, except for dc voltage source V1 . Three dc voltage sources V1 , V2 , and V3 bypassed by switch S1 . As shown in Fig. 1, each switch is consist of an IGBT with an anti parallel diode,

v0

vo

0 V1 − V1 V4 − V4 . . . Vn − Vn V1 + V2 − V1 − V2 . . .

S1

S2

S2

···

Sn

T1

T2

1 0 0 1 1 . . . 1 1 0 0 . . .

0 0 0 0 0 . . . 0 0 1 1 . . .

0 1 1 0 0 . . . 1 1 0 0 . . .

··· ··· ··· ··· ··· . . . ··· ··· ··· ··· . . .

0 0 0 0 0 . . . 1 1 0 0 . . .

1 1 0 1 0 . . . 1 0 1 0 . . .

0 1 0 1 0 . . . 1 0 1 0 . . .

0 V1 V1 V4 V4 . . . Vn Vn V1 + V2 V1 + V2 . . .

0

1

0

···

0

1

1

Vi

n−1 

i=1 n−1

0

1

0

···

0

0

Vi i=1 n

0

1

0

···

1

1

1

0

···

0

Vi

n 

0

Vi i=1

Vi i=1

 1



Vi i=1 n

0

−

i=1

 1

Vi i=1 n−1

 0

n−1 

−

n 

Vi i=1

except switch S  2 . Only S  2 is bi-directional switch and the other switches are unidirectional, from the blocking voltage viewpoint. Both switches, Si and S  i (for i = 2, 3, . . ., n), are working in a complementary way. When the switch S1 is turned on, the switches S2 , S  2 , and S3 must be turned off and the switch S  3 must be turned on to prevent need for further bi-directional switches. In other words S1 and S  3 with S2 , S  2 , and S3 are complementary controlled on the entire operation cycle. The basic unit produces a staircase voltage waveform with positive polarity. The output side of the basic unit is connected to a single-phase full-bridge converter, which provides a positive or negative staircase waveform at the output. It is mentionable that if the numbers of dc voltage sources in each basics unit are less than four (n ≤ 3), there is no need to S1 and also no need to bi-directional switch. If the number of dc voltage sources in basic unit is considered equal to 1, in that case there isn’t any switch in basic unit and the dc voltage source is directly connected to the fullbridge converter. In other words, this topology is equivalent to the H bridge inverter. The values of voltages v o and vo for permitted states of the switches S1 , S2 , S  2 , . . ., Sn , T1 , and T  2 are shown in Table 1. States conditions 1 and 0 means that the switch is on and off, respectively. It is noticeable that there are different switching states for producing the zero voltage level and in Table 1 only one of them is presented. The proposed topology is constituted of a series connection of submultilevel inverters as shown in Fig. 2. The structure of the first, second . . . and kth basic unit have 2n1 , 2n2 , . . ., and 2nk IGBTs, respectively. The H-bridge inverters provide positive or negative voltage steps between the output terminals. The overall output voltage of the proposed cascaded multilevel inverter is the sum of output voltages of the submultilevel inverters as follows:

vo = vo1 + vo2 + · · · + vok

(1)

The different output voltage steps can be obtained by combinations of switching states of each unit. If proper values for the dc voltage

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147

3.1. First proposed algorithm According to the first proposed algorithm, all the magnitudes of dc voltage sources in each unit are equal. The first dc voltage source is considered as the base value for the per-unit system. V11 = Vdc

(4)

To produce all voltage steps, magnitudes of the other dc voltage sources are chosen as follows: First unit: V1i = V11 = Vdc

for i = 2, . . . , n1

(5)

Second unit: V2i = V21 = V11 + 2

n1 

V1j = (2n1 + 1) Vdc

for i = 2, . . . , n2 (6)

j=1

Third unit: V3i = V31 = V11 + 2

n1 

V1j + 2

n2 

j=1

Fig. 2. Proposed extended topology.

= (2n1 + 1)(2n2 + 2) Vdc

sources are selected, then the output voltage of the proposed topology (vo ) can be obtained as follows:

 k

ni

−

i=1 j=1

 k

Vij ≤ vo ≤ +

Vij

nr m−1  

(2)

(7)

Vrj

r=1 j=1

i=1 j=1



m−1

If the number of dc voltage sources in each basic unit is considered equal to 1, in that case there is not any switch in basic unit and the dc voltage source is directly connected to the full-bridge converter. In other words, this topology is equivalent to the CHB inverter. Although this topology requires multiple dc voltage sources, but they may be available in some systems through renewable energy sources, such as photovoltaic panels or fuel cells, or with energy storage devices, such as capacitors or batteries. When ac voltage is already available, then, multiple dc sources can be generated using isolated transformers and rectifiers, too [8]. The proposed topology requires dc sources with unbalanced active power requirements. There are some methods by the name of “charge balance control” presented in some references to balances the active power supplied from various dc voltage sources [14–18]. Balancing the supplied power is dependant on control methods. The main goal of this paper is to focus on proposing a new topology using less elements and obtaining optimal structures for the various conditions.

= Vdc ×

(2nr + 1) for i = 2, . . . , nm

(8)

r=1

For this algorithm the maximum output voltage Vomax is obtained as follows: Vo max =

ni k  

k 

Vij =

i=1 j=1

(ni × Vi1 )

(9)

i=1

The number of output voltage steps for the first proposed algorithm Nstep1 can be obtained by the following equation: Nstep1 =

k 

(2ni + 1) = (2n1 + 1)(2n2 + 1), . . . , (2nk + 1)

(10)

i=1

3.2. Second proposed algorithm In this algorithm, the numbers of dc voltage sources in each unit must be more than 1 (ni ≥ 2 for i = 1, . . ., k). According to the second proposed algorithm, the magnitudes of dc voltage sources for units are chosen as follows:

3. Proposed algorithms for determination of magnitudes of dc voltage sources In order to provide a large number of output voltage steps with minimum number of switches by proposed extended multilevel inverter that shown in Fig. 2, asymmetric structures can be used. Three algorithms for determination of magnitudes of dc voltage sources are proposed. These proposed algorithms can produce all voltage steps (odd and even) at the output of proposed extended multilevel inverter. In all proposed algorithms, the base value of the per-unit systems considered as Vdc . V11 = Vdc

for i = 2, . . . , n3

mth unit: Vmi = Vm1 = V11 + 2

ni

V2j

j=1

(3)

First unit V11 = V12 = Vdc

(11)

V1i = 2 V11 = 2 Vdc

for i = 3, . . . , n1

(12)

Second unit n1 

V21 = V22 = V11 + 2

i=1

V1i = (4n1 − 3) Vdc

(13)

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

V2i = 2 V21 = 2(4n1 − 3) Vdc

for i = 3, . . . , n2

(14)

Third unit: n1 

Third unit n1 

V31 = V32 = V11 + 2

n2 

V1i + 2

i=1

V31 = V32 = V11 + 2

i=1

V2i = (4n1 − 3)(4n2 − 3) Vdc

i=1

n2 

V1i + 2

V2i

i=1

= (5 × 2n1 −2 − 1) (5 × 2n2 −2 − 1) Vdc

(27)

(15) V33 = 2 V31 = 2 (5 × 2n1 −2 − 1) (5 × 2n2 −2 − 1) Vdc

V3i = 2 V31 = 2(4n1 − 3)(4n2 − 3) Vdc

for i = 3, . . . , n3

(16)

mth unit: nr m−1  

Vm1 = Vm2 = V11 + 2

for i = 4, . . . , n3

Vrj = Vdc ×

(4nr − 3)

(17)

r=1

(29)

mth unit: nr m−1  

Vm1 = Vm2 = V11 + 2

m−1

Vmi = 2 Vm1 = 2 Vdc ×

V3i = 2i−4 × 5 V31 = (2i−4 × 5)(5 × 2n1 −2 − 1)(5 × 2n2 −2 − 1) Vdc

m−1

r=1 j=1





(4nr − 3) for i = 3, . . . , nm

(18)

For the second proposed algorithm the maximum output voltage Vomax is obtained as follows: Vo max =

Vij =

i=1 j=1

(5 × 2nr −2 − 1)

(30)

r=1

m−1

Vm3 = 2 Vm1 = 2Vdc ×

k 





m−1

Vrj = Vdc ×

r=1 j=1

r=1

ni k  

(28)

[(2ni − 2) × Vi1 ]

(19)

i=1

(5 × 2nr −2 − 1)

(31)

r=1



m−1

Vmi = 2i−4 × 5 Vm1 = (2i−4 × 5)Vdc ×

(5 × 2nr −2 − 1)

r=1

for i = 4, . . . , nm

(32)

The number of output voltage steps for this algorithm Nstep2 can be determined by the following equation: Nstep2 =

k 

(4ni − 3)

(20)

For the third proposed algorithm the maximum output voltage Vomax is obtained as follows:

i=1

It is necessary to consider that when the number of dc voltage sources in each unit is more than 1 (Eqs. (11)–(20)) are true. If the number of dc voltage sources in each unit is less than 2 (equal 1) in that case (Eqs. (4)–(10)) are true. 3.3. Third proposed algorithm

Vo max =

i=1 j=1

Vij =

k 

[(5 × 2ni −3 − 1) × Vi1 ]

(33)

i=1

The number of output voltage steps for this algorithm Nstep3 can be obtained by the following equation: Nstep3 =

In this algorithm, the number of dc voltage sources in each unit must be more than 3 (ni ≥ 4 for i = 1, . . ., k). According to this proposed algorithm, the magnitudes of dc voltage sources for units are chosen as follows:

ni k  

k 

(5 × 2ni −2 − 1)

(34)

i=1

As mentioned previously, when the number of dc voltage sources in each unit is more than 3 (Eqs. (21)–(34)) are true. 4. Optimal structures

First unit:

(24)

One of the main objectives in multilevel inverters design field is to obtain the maximum number of output voltage steps with a minimum number of dc voltage sources and switches. In the proposed extended structure, there are different submultilevel configurations for specific output voltage steps. These specific output voltage steps can be obtained by using different number of dc voltage sources and switches. To reduce the cost, weight, and size, an optimized structure must be obtained, so that in optimal structure to produce a given output voltage steps, there is less need to dc voltage sources and switches. In this section these optimal structures are investigated.

(25)

4.1. Optimal structure for maximum number of voltage steps with constant number of IGBTs

(26)

One of the important objectives that considered is to obtain the maximum number of steps for minimum number of IGBTs. In this section for the proposed extended topology the number of IGBTs

V11 = V12 = Vdc

(21)

V13 = 2 V11 = 2 Vdc

(22)

V1i = 2i−4 × 5 V11 = 2i−4 × 5 Vdc

for i = 4, . . . , n1

(23)

Second unit: n1 

V21 = V22 = V11 + 2

V1i = (5 × 2n1 −2 − 1) Vdc

i=1

V23 = 2 V21 = 2 (5 × 2n1 −2 − 1) Vdc V2i = 2i−4 × 5 V21 = (2i−4 × 5)(5 × 2n1 −2 − 1) Vdc for i = 4, . . . , n2

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NIGBT is assumed to be constant. The goal is to obtain the maximum number of output voltage steps by this constant number of IGBTs. Suppose that the proposed topology consists of k submultilevel inverters and each of units has ni dc voltage sources (i = 1, 2, . . ., k). In that case the number of IGBTs in proposed topology is obtained as follows: NIGBT = 2(n1 + n2 + · · · + nk ) + 4k

(35)

The number of voltage steps that obtained by three proposed algorithms are given by Eqs. (10), (20) and (34). According to these equations and (35), the product of the numbers, whose summation is constant, will be maximized, when all are equal. n1 = n2 = · · · = nk = n

(36)

According to Eqs. (35) and (36), the following equation is obtained k=

NIGBT 2n + 4

(37)

Considering Eqs. (10), (20), (34) and (36), the maximum number of voltage steps for each three proposed algorithms achieve from these following equations, respectively: Nstep1 = (2n + 1)k

(38)

Nstep2 = (4n − 3)k

(39)

Nstep3 = (5 × 2n−2 − 1)

k

Nstep1 = [(2n + 1)1/(2n+4) ]

NIGBT

Nstep2 = [(4n − 3)1/(2n+4) ]

NIGBT

(41) (42)

1/(2n+4) NIGBT

]

(43)

The number of output voltage steps will be maximized when the expressions inside the brackets are maximized. Fig. 3 shows the variation of (2n + 1)1/(2n+4) , (4n − 3)1/(2n+4) , and (5 × 2n−2

− 1)

1/(2n+4)

1/(2n+4)

versus n.

that the maximum number of voltage steps for the first proposed algorithm obtained by n = 2 (Fig. 4a). This means that a structure consisting of two dc voltage sources in each basic unit can provide maximum output voltage steps with a minimum number of IGBTs (two IGBTs in each basic unit). For the second proposed algorithm, the maximum is obtained for n = 3 (Fig. 4b). This means there are three dc voltage sources in each basic unit (four IGBTs in each basic unit). As mentioned previously if the number of dc voltage sources in each basic unit is less than four (n ≤ 3), there is no need to Si1 (i = 1, 2, . . ., k) and also no need to bi-directional switch S  i2 (i = 1, 2, . . ., k). For the third proposed algorithm, the maximum is theoretically obtained for n = ∞ . This means that a structure consisting of one basic unit (k = 1) with available IGBTs is desirable for a constant number of IGBTs (Fig. 1).

(40)

According to Eqs. (37)–(40), the following equations can be obtained

Nstep3 = [(5 × 2n−2 − 1)

Fig. 3. Variation of (2n + 1)1/(2n+4) , (4n − 3)1/(2n+4) , and (5 × 2n−2 − 1)

versus n. According to Fig. 3, it is evident

4.2. Optimal structure for maximum number of voltage steps with constant number of dc voltage sources Suppose that the number of dc voltage sources Nsource is constant. This section’s goal is to obtain the maximum number of output voltage steps by this constant number of dc voltage sources. Suppose that the proposed topology consists of k submultilevel inverters and each of units has ni dc voltage sources (i = 1, 2, . . ., k). In that case the number of dc voltage sources of proposed topology is obtained as follows: Nsource =

k 

ni = n1 + n2 + · · · + nk

(44)

i=1

Fig. 4. Optimal structures to produce maximum output voltage steps with constant number of IGBTs; (a) First proposed algorithm; and (b) Second proposed algorithm.

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

the maximum are obtained for n = 2 (Fig. 4a) and n = 4 (Fig. 6b) respectively. 4.3. Optimal structure for minimum number of switches with constant number of voltage steps

According to Eqs. (36) and (44) the following equation can be obtained:

Assume that the number of voltage steps is constant and equal to Nstep . In this section the goal is to obtain the optimal structure that can produce constant Nstep with the minimum number of IGBTs. As mentioned previously, according to Eqs. (36) the maximum number of voltage steps can be obtained when the number of IGBTs in each unit is equal to each other. With considering that the number of voltage steps is constant and according to Eqs. (38), (39) and (40), k for first, second, and third proposed algorithms can be obtained as Eqs. (50), (51) and (52), respectively:

Nsource = k × n

k=

ln(Nstep ) ln(2n + 1)

(50)

k=

ln(Nstep ) ln(4n − 3)

(51)

Fig. 5. Variation of (2n + 1)

1/n

, (4n − 3)

1/n

and (5 × 2n−2 − 1)

1/n

versus n.

(45)

According to that Nsource is constant, so k can be obtained from Eq. (45) as follows: Nsource k= n

(46)

According to Eqs. (38)–(40), and (46) the following equations can be obtained: Nstep1 = [(2n + 1)1/n ]

Nsource

Nstep2 = [(4n − 3)1/n ]

Nsource

n−2

Nstep3 = [(5 × 2

− 1)

(47)

1/n

ln(Nstep )

1/n Nsource

According to the above equations, the overall number of IGBTs for three proposed algorithms can be obtained as following equations, respectively: NIGBT 1 = (2n + 4)k =

2n + 4 × ln(Nstep ) ln(2n + 1)

(53)

NIGBT 2 = (2n + 4)k =

2n + 4 × ln(Nstep ) ln(4n − 3)

(54)

NIGBT 3 = (2n + 4)k =

2n + 4 × ln(Nstep ) ln(5 × 2n−2 − 1)

(55)

(49)

]

(2n + 1)1/n ,

(4n − 3)1/n ,

and

− 1) versus n. According to Fig. 5, it is evident that the maximum number of voltage steps for the first proposed algorithm obtained by n = 1 (Fig. 6a). This means one dc voltage source in each basic unit can provide maximum output voltage steps with a minimum numbers of dc voltage sources. In that case there are four IGBTs (in H-bridge) and there is one dc voltage source in each submultilevel unit. For the second and third proposed algorithms,

(52)

ln(5 × 2n−2 − 1)

(48)

Fig. 5 shows the variation of (5 × 2n−2

k=

Fig. 7 shows the variation of 2n + 4/ln(2n + 1), 2n + 4/ln(4n − 3), and 2n + 4/ln(5 × 2n−2 − 1) versus n. According to Fig. 7, it is clear that the number of IGBTs for a constant Nstep will be minimized at the

Fig. 6. Optimal structures to produce maximum output voltage steps with constant number of dc voltage sources; (a) First proposed algorithm; and (b) Third proposed algorithm.

E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

Fig. 7. Variation of 2n + 4/ln(2n + 1), 2n + 4/ln(4n − 3) and 2n + 4/ln(5 × 2n−2 − 1) versus n.

minimum point of these figures. For the first and second proposed algorithms, the minimums are obtained in n = 2 (Fig. 4a) and n = 3 (Fig. 4b), respectively. For the third proposed algorithm, the minimum is theoretically obtained for n =∞ (Fig. 1). 5. Comparison of the proposed topology with other conventional topologies In order to show the capabilities of the proposed algorithms and topology, the proposed topology and algorithms are compared with the symmetrical CHB multilevel inverter (CHB1), asymmetrical CHB multilevel inverters (magnitudes of dc voltage sources increase with multiples of 2 and 3 that shown with CHB2 and CHB3, respectively), recommended topologies in [8] (Fig. 8a), [9] (Fig. 8b),

151

[10] (Fig. 8c), [11] (Fig. 8d) [12], and [13]. These comparisons are studied from the viewpoints of the number of IGBTs, output voltage steps, driver circuits, dc voltage sources, variety of magnitudes of dc voltage sources, and blacked voltages on switches. It is important to mention that each switch in the presented topologies in [10,11,13], and CHB multilevel inverters is based on unidirectional switch that consists of one IGBT and one anti-parallel diode. Each switch in the presented topologies in [8] and [9] is based on bi-directional switches that are composed of two IGBTs and two anti-parallel diodes. In [12] there are some bi-directional switches. In the proposed topology in this paper only one bi-directional switch has been used in each unit. Therefore, to compare the different topologies, the number of IGBTs (instead of switches) is used in this paper. According to optimality results in Section 4, topologies that used first and second algorithms do not need to bi-directional switches (and also Si1 switch) in each basic unit. Because the number of dc voltage sources in each optimal basic unit is less than four for first and second algorithms. Fig. 9 shows the comparative results of the number of IGBTs (NIGBT ) to produce specific voltage steps (Nstep ). In Figs. 9a, b, and c the magnitudes of dc voltage sources for optimal structures in this paper are obtained by first, second, and third proposed algorithms respectively. Also in these figures the magnitudes of dc voltage sources for presented topology in [11] have been obtained by first, second, and third presented algorithms in [11], respectively. Also the magnitudes of dc voltage sources in CHB have been obtained by multiples of 1, 2 and 3, respectively. As this figure shows, the proposed topology needs less IGBTs for specific Nstep voltage for

Fig. 8. Presented topologies in (a) [8]; (b) [9]; (c) [10]; and (d) [11].

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

Fig. 9. Variation of Nstep versus NIGBT for proposed topology with topologies presented in [8–13] and CHB; (a) Determination of magnitudes of dc voltage sources from first algorithm; (b) Determination of magnitudes of dc voltage sources from second algorithm; and (c) Determination of magnitudes of dc voltage sources from third algorithm.

output. Considering Fig. 9b to produce specific output voltage, CHB3 and proposed topology (that uses second proposed algorithm) use the same number of IGBT. Also considering Fig. 9c up to step 81 (Nstep < 81), CHB3 needs less IGBTs than proposed topology (that uses third proposed algorithm) but after level 81 (Nstep ≥ 81) it need more. It is noticeable that the number of anti-parallel diodes and IGBTs are the same. Fig. 10 compares the required number of gate driver circuits (Ndriver ) to produce specific Nstep . In structures with bi-directional switches (optimal structure of third proposed algorithm and structures that presented in [8,9,12]) if the common emitter configuration is used each bi-directional switches requires a gate driver

circuit [8]. By using common emitter configuration, in [8,9,12] structures, there is a less need of gate driver circuit. Fig. 11 shows the comparative results of the number of dc voltage sources (Nsource ) versus Nstep . As Fig. 11 shows, the number of dc sources that required in the first proposed algorithm is less than second and third proposed algorithms. In the asymmetric topologies, the values of dc voltage sources magnitude are unequal or changed dynamically .One of the important problems for asymmetric structures of multilevel inverters is the variety of magnitudes of dc voltage sources. Fig. 12 shows the variety of magnitudes in dc voltage sources (Nvariety ) to produce specific. The structures presented in [10], and [13], and CHB1

Fig. 10. Variation of Ndriver versus Nstep for proposed topology with topologies presented in [8–13] and CHB (a). Determination of magnitudes of dc voltage sources from first algorithm; (b) Determination of magnitudes of dc voltage sources from second algorithm; and (c) Determination of magnitudes of dc voltage sources from third algorithm.

E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

153

120

80

V switch 60

second algorithm

40

[9]

[12]

20 0

[8]

third algorithm [11] & [13]

100

1

[10] & CHB

first algorithm 5

15

10

20 N step

25

30

35

40

Fig. 13. Variation of Vswitch versus Nstep for proposed topology with topologies presented in [8–11] and CHB. Fig. 11. Variation of Nsource versus Nstep for proposed topology with topologies presented in [8–13] and CHB.

do not have magnitude variety in dc voltage sources, because of symmetrical structure. The next comparison index is blocking voltages on switches. The current and voltage ratings of the switches in a multilevel inverter play important roles in the cost and realization of the multilevel inverter. In all topologies, the currents of all switches are equal to the rated current of the load. This is, however, not the case for the voltage [8]. Suppose that peak inverse voltage of all switches (Vswitch ) is represented by: Vswitch = Vswitch,U + Vswitch,H =

k 

Vswitch,u,j +

j=1

k 

Vswitch,h,j

(56)

j=1

where Vswitch,U and Vswitch,H are the peak voltage of basic units and full bridge converter switches, respectively. Also Vswitch,u,j and Vswitch,h,j represent the peak voltage of switches in the jth basic unit and jth full bridge converter, respectively. Therefore, Eq. (56) can be considered as a criterion for comparison of different topologies considering the maximum voltage on switches [8]. According to Section 4.1 the maximum number of voltage steps for the first and second proposed algorithms are obtained for n = 2 and n = 3, respectively. The maximum number of voltage steps for the third proposed algorithm is obtained when k = 1. So Eqs. (38)–(40) can be written as follows: Nstep1 = 5k

(57)

Nstep2 = 9k

(58)

Nstep3 = 5 × 2n−2 − 1

(59)

9 8 7 6 N variety5 4 3 2 1 0



Vswitch1 = 10 Vdc

 Vswitch2 = 22 Vdc

5k − 1 4 9k − 1 8



(60)

 (61)

Vswitch3 = 30 Vdc (2n−3 − 1) + 26 Vdc

(62)

According to Eqs. (57)–(59), Eqs. (60)–(62) can be rewritten as follows: Vswitch1 =

5 Vdc (Nstep − 1) for Nstep ≥ 2 2

(63)

Vswitch2 =

11 V (Nstep − 1) for Nstep ≥ 2 4 dc

(64)

Vswitch3 = 3 Vdc (Nstep − 1) + 2 Vdc

for Nstep ≥ 2

(65)

Fig. 13 compares the normalized blocking voltages on switches to realize Nstep by the proposed topology and those presented in [8–13] and CHB. It is evident that the blocking voltage on switches in the proposed topology is less than that presented in [8]. The proposed topology utilizes multiple cascaded full bridges in the output side of the inverter while in [8] it utilizes one full bridge in the output side. According to Eq. (62) the overall peak voltage of full bridge converters in the proposed topology is equal to that presented in [8]. But in [8], this voltage is related to only one full bridge converter. This leads to restriction in the high voltage applications. 6. Simulation and experimental results

[9], [11], CHB3, & first algorithm

[8] & CHB2 [12] third algorithm

[10], [13] & CHB1 50

According to Eq. (56) the peak voltage of switches which used the first, second, and third proposed algorithms are obtained by following equations, respectively:

100

150

second algorithm

200 250 N step

300

350

400

Fig. 12. Variation of Nvariety versus Nstep for proposed topology with topologies presented in [8–13] and CHB.

To examine the performance of the proposed topology to generation desired output voltage waveform, a proposed multilevel based on the third proposed algorithm is simulated. The PSCAD/EMTDC software has been used for simulation. In the simulation, the switches have been assumed ideal. A typical single-phase proposed multilevel inverter based on third proposed algorithm with 19 voltage levels and a peak value of 220 V (Fig. 14) has been simulated. According to Section 4, for third proposed algorithm, a structure consisting of one basic unit with available IGBTs is desirable for a constant number of IGBTs. According to the peak value of output voltage the base value (1 pu) of dc voltage source is 24.44 V (Vdc = 24.44 V). The number of IGBTs and voltage sources is 12 and 5, respectively. The load is a series R-L with magnitudes R = 100  and L = 55 mH, respectively. There are several modulation strategies for multilevel inverters [18,19]. In this paper, the fundamental frequency switching technique has been used. The benefit

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156 Table 2 On switches look-up table for proposed multilevel inverter shown in Fig. 14. State

Fig. 14. 19-Level multilevel inverter with the minimum number of switches (according to the third method).

of the fundamental frequency switching method is its low switching frequency in comparison with the other control methods. In this work the fundamental frequency is 50 Hz. It must be considered that the calculation of optimal switching angles for different goals such as elimination of the selected harmonics and minimizing total harmonic distortion (THD) are not the objective of this paper. Table 2 shows the on switches lookup table. It is noticeable that there are different switching states for producing the zero voltage level and in Table 2; only one of them is presented. It is important to mention that the switch S1 is only on for producing the zero and vo, unit = 5pu voltage levels and in other levels it is off (as shown in Table 2). Of course for producing the zero voltage level the switch S1 can be off. Fig. 15 shows how the voltage steps are generated when the fore power sources of Fig. 14 are on and are off in a half period of output voltage. The next half period is the same as firs one. Also the on switches are shown in Fig. 15. Fig. 16 shows

1 2 3 . . . 10 11 . . . 18 19

vL [pu]

Switches states

(1 pu = 24.4 V)

S1

S2

S 2

···

T1

T 2

1 0 0 . . . 1 1 . . . 0 0

0 0 0 . . . 0 0 . . . 1 1

0 1 1 . . . 0 0 . . . 0 0

··· ··· ··· . . . ··· ··· . . . ··· ···

1 1 0 . . . 1 0 . . . 1 0

0 1 0 . . . 1 0 . . . 1 0

0 1 -1 . . . 5 -5 . . . 9 -9

Fig. 17. Simulation results of the output current (iL ).

Fig. 15. On and off power sources in Fig. 14.

Fig. 16. Simulation results of the base unit output voltage (vo,unit ) and the overall output voltage (vL ).

E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

155

Fig. 18. Experimental results of the base unit output voltage (vo,unit ) and the overall output voltage (vL ).

the base unit output voltage (vo,unit ) and the overall output voltage (vL ). Fig. 17 shows the inverter output current. As can be seen from the Fig. 17 the amplitude of the output current is 2.2 A. The Fourier series expansion of the stepped output voltages waveform of the multilevel inverter as shown in Fig. 16 is made up from a fundamental frequency sine wave and an infinite number of odd harmonics [20]. As can be seen from the waveforms, the output current is almost sinusoidal. Since the load of the converters is almost a low pass filter (R-L), the output current contains less high order harmonics than the output voltages. For this simulation, the THDs of the output voltage and current based on the simulation are 4.54% and 2.39%, respectively. To generate a desired output with the best quality waveform, the number of the voltage steps should be increased. To examine the performance of the proposed multilevel inverter, a single-phase 19-level multilevel inverter prototype is implemented based on the proposed topology shown in Fig. 14. The IGBTs of the prototype are BUP306D with internal anti-parallel diodes. The 89C52 microcontroller by ATMEL Company has been used to generate the switching patterns. Fig. 18 shows the base unit output voltage (vo,unit ) and the overall output voltage (vL ). Fig. 19 shows the inverter output current. The experimental results illustrate good agreement with simulation results. There is a small difference between the amplitudes of the simulation and experimental results due to the voltage drops on switches of the prototype. The experimental results show some distortion on the zero crossing. Because in the zero crossing level, the voltage sources are disconnected and only R-L load is connected

Table 3 Comparison of the number of sources, IGBTs, and output voltage steps. Topology

Algorithm

Proposed

First Second Third

CHB

Nsource

NIGBT

Nstep

6 6 8 10

18 16 20 24

125 81 319 1479

CHB1 CHB2 CHB3

5 5 5 6

20 20 20 24

11 63 243 729

[8]

Presented

6

22

53

[9]

Presented

4

24

49

[10]

Symmetrical

10

20

11

[11]

First Second Third

6 4 8

24 16 20

125 49 511

[12]

Presented

10 14

20 24

243 972

[13]

Symmetrical

8

20

17

to the circuit. The load current is supplied from inductor’s saved energy. As there is a limit on power (no power supply in zero crossing) and switching pattern there is some distortion on the zero crossing state. 7. Conclusion

Fig. 19. Experimental results of the output current (iL ).

In this paper, a new topology for the multilevel inverter has been proposed that is composed of the series connection of submultilevel inverters. Each submultilevel consists of a basic unit and a full bridge converter. Also, three algorithms to determine magnitudes of dc voltage sources have been proposed to produce all steps (odd and even) at the output voltage. The extended proposed topology was optimized for various objectives. This topology has been compared with presented topologies in [8–13], symmetrical CHB multilevel inverter and asymmetrical CHB multilevel inverters. Table 3 shows the number of sources, IGBTs, and output voltage steps in the proposed topology and algorithms, presented topologies in [8–13], and CHBs. So it is obvious that the total number of IGBTs used in proposed topology is less than other configurations. The operation and the performance of the third proposed algorithm and proposed topology have been simulated and experimentally verified on a single-phase 19-level multilevel inverter prototype.

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E. Babaei et al. / Electric Power Systems Research 103 (2013) 145–156

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