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A new dynamic gain control algorithm for speed enhancement of digital-phase locked loops (DPLLs)
ARTICLE IN PRESS
Signal Processing 86 (2006) 1426–1434 www.elsevier.com/locate/sigpro
A new dynamic gain control algorithm for speed enhancement of digital-phase locked loops (DPLLs) T. Banerjee, B.C. Sarkar Physics Department, Burdwan University, Burdwan 703104, India Received 7 April 2005; received in revised form 15 July 2005 Available online 1 September 2005
Abstract A dynamic gain modification algorithm of a class of DPLLs has been proposed to improve its transient characteristics and tracking behavior. In this technique, rather taking a time invariant gain, the gain of the loop digital filter is made a function of the sampled value of the signal at every sampling instant. It has been shown analytically as well as numerically that the new structure is faster than the conventional one in its acquisition time and at the same time, it has a broader acquisition range. r 2005 Elsevier B.V. All rights reserved. Keywords: Zero-crossing digital-phase locked loop (ZC-DPLL); Loop gain; Transient response, stability criteria
1. Introduction Digital-phase locked loops (DPLLs) are essential building blocks in modern coherent communication systems as carrier regenerators, frequency synthesizers, bit synchronizers, hard disc drives, modems, etc. [1,2]. A high-speed communication system demands that a DPLL should be able to reach the steady state as quickly as possible without degrading the stability behavior of the loop. For conventional DPLLs (CDPLLs), it has been observed that, for a given set of systems and signal parameters, in order to achieve a faster transient response, the loop gain should be taken lower than the maximum allowable range and thus the acquisition range of the loop is reduced. Thus, faster transient response and broader acquisition range cannot be simultaneously achieved in a CDPLL. Another way to Corresponding author. Tel.: +091 03422556478.
E-mail address: [email protected] (T. Banerjee).
achieve faster transient characteristics is to make the order of the loop higher, which will increase the system complexity and make the system, sensitive to initial conditions. Research is going on [3–8] to alleviate this problem and a few techniques have been reported in the literature to design a DPLL, which satisfies all the above-mentioned criteria. In this paper we propose a new dynamic gain modification algorithm for enhancing the speed of transient response of an analog input positive zerocrossing DPLL (ZC1-DPLL) keeping the stability characteristic and the order of the loop unchanged. The proposed modification extends the range of application of the loop when there is a frequency detuning between the incoming signal and reference signal, i.e. the acquisition range of the loop increases. For the dynamic gain modification purpose, the gain of the loop digital filter (LDF) of ZC1-DPLL is controlled by the sampled value of the input signal at every sampling instant determined by the loop digitally controlled oscillator
0165-1684/$ - see front matter r 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sigpro.2005.07.028
ARTICLE IN PRESS T. Banerjee, B.C. Sarkar / Signal Processing 86 (2006) 1426–1434
Nomenclature: oi (rad/s) Angular frequency of the strong signal sðtÞ o0 (rad/s) Angular nominal frequency of the DCO A0 (volt) Amplitude of the strong signal sðtÞ z (dimensionless) oi/o0 L0 (rad) 2p(z1) dðp; qÞ A metric defined as min (|pq|, 2p|pq|). p, qA (0,2p) fðkÞ (rad) Phase error at the kth instant (DCO). In the transient mode of operation, loopphase error changes at each sampling instant and thus a non-zero control signal will be generated. This signal modifies the gain of the loop at every instance, in a direction such that the loop goes to the steady state from its transient state in a rapid manner. At the steady state, the control signal will become constant or zero, depending upon the nature of the loop and input signal parameters and thus the loop gain would become time invariant. The stability criteria of modified gain controlled DPLL (GCDPLL) has been derived analytically. To compare the transient characteristics of the two structures namely the GCDPLL and CDPLL, a computational method has been adopted, which gives a stochastic picture of the transient behavior of the loops. The present paper is organizsed in the following way. Section 2 describes the proposed structure modification for first-order and second-order DPLL and formulates the system equations. In Section 3, an analysis for the stability behavior of the firstorder and second-order GCDPLL is reported. Section 4 deals with the transient characteristics of the CDPLL and GCDPLL. Section 5 presents the numerical simulation results. Finally, some concluding remarks have been offered in Section 6.
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f (rad) Steady-state-phase error (used in fixed point solution) K 0 (rad) Gain of the first-order loop. K 1 (rad) Gain of the proportional arm of the second-order loop. K 2 (rad) Gain of the integrating arm of the second-order loop. r (dimensionless) 1 þ K 2 =K 1 C (dimensionless) ¼ L0/K0z L (dimensionless) ¼ (C/1+mC) SUMðkÞ (rad) ¼ Sk1 sin fðiÞ, a state variable i
shown in Figs. 1b and c, respectively. In CDPLLs the gain of the LDF, G0 (for first-order DPLL in unit of s/V, and G 1 and G 2 (for second-order DPLL, both have unit of s/V) are time invariant. But, in our proposed technique, gain parameters G 0M , G 1M , and G 2M are made to vary with the sampled signal xðkÞ (volt) at the sampler output at each sampling instant k (k ¼ 0; 1; 2 :::). Thus, the proposed algorithm modifies the gain of the LDF by the following relation: G iM ¼ G i ð1 þ bxðkÞÞ,
(1)
2. System description and system equation formulation 2.1. Description of the gain modification technique for first- and second-order DPLL Fig. 1a shows the functional block diagram of the GCDPLL with dynamic gain control technique. Structures of first-order and second-order LDF are
Fig. 1. (a). Functional block diagram of a dynamic gain controlled DPLL (GCDPLL). GM represents the modified gain of the loop digital filter. (b) Loop digital filter (LDF) for a firstorder CDPLL and (c) LDF for a second-order CDPLL.
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where i ¼ 0 for first-order DPLL and i ¼ 1,2 for second-order DPLL. Here, b (volt1) is a parameter used to quantify the effect of the structure modification. In the transient mode of operation, xðkÞ changes at each sampling instant and thus the gain also changes. At the steady state of operation, depending upon signal and system parameters, xðkÞ becomes constant or zero, so the gain of the LDF returns to its time invariant nature. 2.2. System equation formulation
signal can be written as yðkÞ ¼ G 0 ½1 þ bxðkÞxðkÞ
(8)
and for a second-order GCDPLL, the same is given by yðkÞ ¼ ðG 1 þ G 2 Þ½1 þ bxðkÞxðkÞ þ G 2 ½1 þ bxðkÞA0 SUMðkÞ,
ð9Þ
where SUMðkÞ (rad) has been defined as SUMðkÞ ¼
k1 X
sin fðiÞ:
(10)
i¼0
Noise free and unmodulated input signal of amplitude A0 (volt) is written in terms of the angular frequency (o0 rad/s) of the DCO as, SðtÞ ¼ A0 sinðo0 t þ yðtÞÞ, where we make the substitution yðtÞ ¼ ðoi o0 Þt þ y0 . Here, oi (rad/s) is the angular frequency of the input signal and y0 (rad) is a constant-phase part. SðtÞ is sampled by the positive zero crossing edge of the DCO at time instants tðkÞ (s). The time elapsed between (k1)th and kth instants is given by TðkÞ ¼ tðkÞ tðk 1Þ; k ¼ 1; 2; . . .
(2)
The sampled value of SðtÞ at tðkÞ is given by xðkÞ ¼ sðtðkÞÞ,
(3)
the sequence of the samples {x(k)}, k ¼ 0,1, y is filtered by the LDF and the filtered version of the samples, {y(k)} (having a dimension of time), controls the period of the DCO at (k+1)th instant with the following algorithm [1]: Tðk þ 1Þ ¼ T yðkÞ,
(4)
where T ( ¼ 2p/o0) is the nominal period of the DCO. Also, in our present system, xðkÞ is used to control the gain of the LDF as mentioned in (1). Using (2) and (4) and taking tð0Þ ¼ 0, one can get the sampling instants tðkÞ as tðkÞ ¼ kT
k1 X
yðiÞ.
(5)
0
We define the phase error fðkÞ at the kth instant as fðkÞ ¼ yðkÞ o0
k1 X
yðiÞ,
(6)
0
which in turn gives fðk þ 1Þ ¼ fðkÞ þ L0 zo0 yðkÞ,
(7)
where z ¼ ðoi =o0 Þ is the normalized input frequency and L0 is substituted in place of 2pðz 1Þ. Now, for a first-order GCDPLL, DCO control
Using (8) in (7), one gets the phase-governing equation for the first-order GCDPLL as fðk þ 1Þ ¼ L0 þ fðkÞ zK 0 ½1 þ m sin fðkÞ sin fðkÞ,
ð11Þ
where K 0 ð¼ A0 o0 G 0 Þ (rad) is the loop gain of the first-order GCDPLL and mð¼ bA0 Þ (a dimensionless quantity) is the normalized gain modification parameter. (11) represents the system equation for first-order CDPLL when m ¼ 0. Also, the phase-governing equation of the second-order GCDPLL can be achieved using (9) and (10) in (7), which gives fðk þ 1Þ ¼L0 þ fðkÞ zK 1 rf1 þ m sin fðkÞg sin fðkÞ zK 2 f1 þ m sin fðkÞg SUMðkÞ,
SUMðk þ 1Þ ¼ SUMðkÞ þ sin fðkÞ.
ð12aÞ (12b)
Here, we make the following substitutions, K 1 ¼ A0 o0 G1 , K 2 ¼ A0 o0 G2 , and r ¼ 1 þ ðK 2 =K 1 Þ. r is an additional design parameter for second-order GCDPLL. (12) represents the system equation for second-order CDPLL when m ¼ 0. 3. Stability criteria of first- and second-order GCDPLL In this section we investigate the effect of dynamic gain modification algorithm on the stability behavior of the loop. 3.1. Stability analysis of first-order GCDPLL Stability analysis of first-order CDPLL is well documented in [9], which gives the stability condition as 0oK 0 o2,
(13a)
0oðK 0 zÞ2 L20 o4.
(13b)
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To study the stability condition of a GCDPLL we write (11) as a mapping equation fðk þ 1Þ ¼ gðfÞ and find for its solution around a fixed point f . Now, the condition for the convergence (local) to a stable fixed point is given by the Ostrowski’s theorem [9], which is 0 n g ðf Þo1. (14)
approximate of estimate of the value of m for which fastest convergence can be achieved.
For a phase step input (z ¼ 1, i.e L0 ¼ 0), f ¼ 2np (n ¼ 0,1,2 ..) gives the stable loop operation. So the condition of local convergence is given by
0ozK 1 o
j1 K 0 jo1, i:e: 0oK 0 o2.
(15) (15a)
(15a) is similar to (13a), i.e. for a phase step input, stability condition of a GCDPLL remains the same as that of a CDPLL. For a frequency step input (za1), steady-state-phase error can be derived by putting fðk þ 1Þ ¼ fðkÞ ¼ f in (11), which gives sin fn ð1 þ m sin fn Þ ¼ C,
(16)
where C is substituted in place of ðL0 =K 0 zÞ (a dimensionless quantity). Now, to avoid mathematical complexity we consider the steady-state-phase error f is much smaller than 1 rad (which is actually the case in practical situation) and thus taking ð1 þ m sin fn Þ1 ¼ ð1 m sin fn Þ in (16), we get sin fn ¼ L.
(17)
where L is substituted for ðC=1 þ mCÞ. Using (17) in (14), we can write pffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffi (18) 1 zK 0 ð 1 L2 þ 2mL 1 L2 Þo1, This leads to the condition of local convergence to a steady state for GCDPLL, which is given by 0o½ðzK 0 Þ2 L20 ð1 þ 2mLÞ2 o4.
(19)
(19) reduces to the stability condition for CDPLL (13b) for m ¼ 0. (19) shows that, an appropriate value of m, depending upon different K 0 and z, extends the stability zone of the loop. Now, the condition for fastest convergence for frequency step input (za1) can be predicted by making g0 ðfn Þ ¼ 0, which gives " # 1 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 . m¼ (20) 2L zK 0 1 L2 Since, we have done a linearized analysis, the value of m obtained using (20) is not exact. But it gives an
3.2. Stability analysis of second-order GCDPLL The condition of stability a second-order CDPLL is given by [9] 4 . 1þr
(21)
The stability criterion of second-order GCDPLL can be studied by examining the behavior of (12) around the steady-state-phase error value f . The Jacobian of the map (12) is given by JðXÞ ¼
1 zK 1 rðcos f þ m sin 2fÞ zK 2 m SUM cos f
cos f
zK 2 ð1 þ m sin fÞ
1
! ,
ð22Þ where, X ¼ ðfðk þ 1Þ SUMðk þ 1ÞÞT . Examining (12), one can see that, like a CDPLLs, for a secondorder GCDPLL the steady-state-phase error is always zero or a integral multiple of p and at the steady-state SUMðkÞ ¼ ðL0 =zK 2 Þ. Since fixed points around ð2n þ 1Þp would give unstable solutions (as in the case of CDPLL), the fixed points around Xn ¼ 2np are choosen to linearize (22) which gives ! 1 zK 1 r mL0 1 n JðX Þ ¼ . (23) zK 2 1 Considering the characteristic equation JðXn Þ Ilj ¼ 0; to find eigenvalues, we get l2 ½2 zK 1 r mL0 l þ ½1 zK 1 mL0 ¼ 0. (24) According to the Ostrowski’s theorem [9], in order to reach the steady locked state, the eigenvalues of JðXn Þ, denoted by li , must satisfy the condition jli jo1; i ¼ 1; 2: Deriving the eigen values of (23) from (24) and after some algebraic transformations, one can easily get the condition for which system would attain a stable steady state, 0ozK 1 o
ð4 2L0 mÞ . 1þr
(25)
(25) reduces to (21) for m ¼ 0. A suitable value of m extends the stability zone of the GCDPLL. It can also be concluded that for a fixed K 1 , z can be varied to a larger value indicating that GCDPLL has a larger acquisition range compare to CDPLL. Examining (23), we see that, for the phase step input
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(z ¼ 1) the steady-state parameter SUMðkÞ is zero (since in that case L0 ¼ 0); so the effect of m is absent in the linearized Jacobian JðX Þ and we can not get any idea about the condition for fastest convergence for phase step input. But for a frequency step input (za1, i.e. L0 a0), condition of fastest convergence can be achieved by making the spectral radius of the Jacobian i.e. the largest eigenvalue of JðX Þ to zero, which leads to the condition, m¼
1 zK 1 . L0
(26)
For a second-order DPLL optimum loop conditions are obtained for K 1 ¼ 1 and r ¼ 2 [1]. In our present system, we find an optimum value of m keeping these parameters unchanged for different values of z. (26) shows that m becomes independent of z for K 1 ¼ 1 and its value is a constant equals to 0.159. This is a very useful result in the sense that one can choose the same value of m for different values of the signal detuning. 4. Transient response of the first- and second-order GCDPLL To examine the transient response of the GCDPLL and CDPLL, we examine the convergence rate of the system difference Eq. (11) for a first-order GCDPLL; for a second-order GCDPLL we rewrite the system Eq. (12) in the following manner: fðk þ 1Þ ¼ L0 þ fðkÞ zK 1 rf1 þ m sin fðkÞg sin fðkÞ zK 2 f1 þ m sin fðkÞg
k1 X
sin fðiÞ.
i¼0
ð27Þ Although the linear analysis of the rate of convergence [9] gives a satisfactory result for a very small phase error, it does not reflect the actual transient characteristics for the whole set of possible initial conditions. In [10], an average convergence rate was computed by examining the contraction of phase space near the fixed point and size of the phase space. This method is reliable in the sense that, it incorporates the transient behavior of the loop for the entire range of initial conditions within the acquisition range and gives a stochastic picture of the convergence rate. In our present system, we will use the procedure of computing the stochastic average of the convergence rate. To compute the average convergence rate, we constitute a computationally
convenient metric [10] for our present system. We define the metric dðp; qÞ for the circle [0,2p] as dðp; qÞ ¼ minðjp qj; 2p jp qjÞ, p; q 2 ½0; 2p.
ð28Þ
It can be shown that dðp; qÞ satisfies all the properties of a metric. For our present system p is replaced by the initial phase error f and q is replaced by the steady-state-phase error f . Since, the convergence time depends on the initial condition of f, so, to take it into account for calculating average convergence rate, we compute a root mean square (rms) statistics for N 0 number of initial points, which gives the average number of iterations to reach a value f from an initial value f. The parameter quantifying the average convergence rate is given by vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u N0 u1 X RMSðkÞ ¼ t (29) dðfk;i ; fn Þ2 , N 0 i¼0 where, k is the number of iteration count. Less the value of k, better is the speed of convergence of the system. While dealing with (29), we have to put the proper values of f for phase step input and frequency step input for first- and second-order DPLL, as discussed earlier. The numerical simulation result using (29) has been shown in the next section. 5. Simulation results Numerical simulation study has been carried out with the help of the phase governing Eq. (11) (for the first-order case) and (12) (for the second-order case) and also by considering the hardware structure of the system given in Fig. 1. 5.1. Regarding the stability of GCDPLL To show the stable region of operation of the loop, we make use of the maping diagrams [11] of the first- and second-order DPLLs. These diagrams have been drawn by plotting the steady-state-phase values with different gain values of the loop. Fig. 2 shows the maping diagram of a first-order GCDPLL for a phase step input (z ¼ 1) and it clearly shows that the stable loop operation does not alter from that of a CDPLL. For a frequency step input (za1), GCDPLL shows larger stable zone of operation if we choose a proper value of m. Fig. 3 shows this situation with z ¼ 1:1.
ARTICLE IN PRESS T. Banerjee, B.C. Sarkar / Signal Processing 86 (2006) 1426–1434
For a second-order GCDPLL, maping diagrams are drawn with K 1 as a control parameter (with r ¼ 2, which is one of the optimum loop parameter). The loop operation has been studied taking fð0Þ as any value within a range p to p in the acquisition region and Sð0Þ ¼ 0. Also we choose the value for m ¼ 0:159 for GCDPLL as predicted earlier in (26). Fig. 4 shows that, for phase step input, the steady-state-phase error of GCDPLL and CDPLL bifurcates at the same value of K 1 . This means that two systems have the same stable zone of operation (0oK 1 zo1:33 ith r ¼ 2); this result supports the analytical prediction of (25). For a frequency step input (za1), a larger stable zone of operation is obtained for a GCDPLL than that of a CDPLL. This has been shown in Fig. 5 in r K 1 plane. Also, the acquisition range of second-order GCDPLL compare to CDPLL is plotted in Fig. 6, which shows that GCDPLL has a larger acquisition range than that of the CDPLL for frequency step input. These results are well in agreement with the analytical derivations of the earlier sections.
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Fig. 3. Mapping diagram of a first-order GCDPLL (m ¼ 0:25) and CDPLL in the face of a frequency step input (z ¼ 1:1).
5.2. Regarding the transient response of a GCDPLL Transient response of the first- and second-order DPLLs are studied by examining the RMSðkÞ values with the number of iterations (k) and also by investigating the real time behavior of the loopphase error. All possible values of system and signal
Fig. 4. Mapping diagram of a second GCDPLL (m ¼ 0:25) and CDPLL in the face of a phase step input (z ¼ 1, r ¼ 2).
Fig. 2. Mapping diagram of a first-order GCDPLL (m ¼ 0:35) and CDPLL in the face of a phase step input (z ¼ 1).
parameters have been chosen but more interests have been given on the larger acquisition range condition. Since for a phase step input linearize Jacobian method does not give any prediction about the optimum value of m for fastest convergence, we have to rely on the numerical searching; and it shows that fastest convergence is achieved for
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Fig. 5. Plot showing the stable zone of GCDPLL (m ¼ 0:159) and CDPLL in r K 1 plane (with z ¼ 1:32).
For a second-order GCDPLL, in the face of a phase step input, numerical study reveals that the fastest convergence occurs at m ¼ 0:25. Fig. 9a shows the comparison between the transient of CDPLLL and GCDPLL for a phase step input (with K 1 ¼ 1, r ¼ 2). For frequency step input, fastest convergence is achieved for the m value as predicted in (26). Fig. 9b shows the comparative transient response of GCDPLL and CDPLL with z ¼ 1:32 and corresponding value of m ( ¼ 0.159) obtained from (26) (taking K 1 ¼ 1, r ¼ 2). It can be seen that GCDPLL is much faster than CDPLL. Real time plots depicting the comparison of GCDPLL and CDPLL are shown in Figs. 10 and 11, which also confirms the enhancement of speed in GCDPLL. All the simulation results show that a GCDPLL can be made faster than a CDPLL by choosing a suitable value of m, as predicted analytically and numerically, without degrading the stability behavior or making the order of the loop higher. Further, for practical situation (e.g. condition for the frequency step input) GCDPLL enhance the speed of convergence and extends the stability range simultaneously, which clearly shows the superiority of GCDPLL over a CDPLL.
2.0 CDPLL RMS (k)
1.5
Fig. 6. Plot (z vs. K 1 ) showing that second-orders GCDPLL (m ¼ 0:159) has larger acquisition range compare to CDPLL for frequency step input (za1).
GCDPLL
1.0 0.5 0.0 0
(a)
10
30
20
RMS (k)
1.6
m ¼ 0:35. Fig. 7a shows the plot of RMSðkÞ with k for a first-order GCDPLL in the face of phase step input with (for z ¼ 1:1, K 0 ¼ 1:85). For frequency step input, fastest convergence occurs near the m ¼ 0:25 which is not exact but of the order of values derived analytically in (20). Fig. 7b shows this situation (for z ¼ 1:1, K 0 ¼ 1:85) and clearly indicates that GCDPLL has faster convergence characteristics than that of the CDPLL (i.e. GCDPLL takes less number of iteration step k than that of a CDPLL). Real time transient characteristics are shown in Fig. 8, which also supports this observation.
0.8
0.0 (b)
0
5
10 k
15
20
Fig. 7. RMSðkÞ versus number of iteration count (k) for a firstorder GCDPLL and CDPLL (m ¼ 0) for (a) z ¼ 1, K 0 ¼ 1:85, m ¼ 0:35 (b) z ¼ 1:1, K 0 ¼ 1:85, m ¼ 0:25. Note that GCDPLL takes less number of step (k) to reach the steady state compare to that of a CDPLL.
ARTICLE IN PRESS T. Banerjee, B.C. Sarkar / Signal Processing 86 (2006) 1426–1434
1.0
1433 CDPLL
0.5
3
GCDPLL
0.0
0.5
0.0 0
20
40
60
80
100
φ(k), rad
φ(k), rad
CDPLL
-0.5 12
16
20
24
28
0
1.0
φ(k), rad
GCDPLL 0.5
-3 0
5
10
0.0 0
20
40
60
80
100
k Fig. 8. Real time plot of the transient response of first-order GCDPLL (m ¼ 0:25) and CDPLL with z ¼ 1:1, K 0 ¼ 1:85 and initial phase is equal to 1 rad.
15 k
20
30
Fig. 10. Real time plot of the transient response of second-order GCDPLL (m ¼ 0:25) and CDPLL (with z ¼ 1, K 1 ¼ 1, r ¼ 2 and initial phase is equal to 2.5 rad). Inset shows the blow up of the same.
3
1.8
CDPLL
CDPLL
GCDPLL 1.2
φ(k), rad
RMS (k)
25
0.6
0
0.0 0
(a)
5
10
15
20
-3
0.8
3 φ(k), rad
RMS (k)
GCDPLL 0.4
0
-3 0
0.0 (b)
0
50
100
20
40
60 k
80
100
120
150
k Fig. 9. RMSðkÞ versus number of iteration count (k) for a second-order GCDPLL and CDPLL for (a) z ¼ 1, K 1 ¼ 1, r ¼ 2, m ¼ 0:25 (b) z ¼ 1:32, K 1 ¼ 1, r ¼ 2, m ¼ 0:159. Note that GCDPLL takes less number of step (k) to reach the steady state compare to that of a CDPLL.
6. Conclusion An algorithm for enhancing the speed of a class of DPLLs has been proposed. This algorithm also
Fig. 11. Real time plot of the transient response of second-order GCDPLL (m ¼ 0:159) and CDPLL (with z ¼ 1:32, K 1 ¼ 1, r ¼ 2 and initial phase is equal to 2.5 rad).
extends the acquisition range for frequency step input and does not affect the stability behavior for phase step input. Also it has been shown that transient behavior of DPLLs can be improved without increasing the order of the DPLLs. It has been established through analytical tools and numerical simulation studies that the GCDPLLs
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are superior to that of the CDPLLs in both transient and steady state of loop operation. Numerical simulation results are in well agreement with the analytical derivations. From practical aspects, this modification can be used in frequency synthesizers, modems, hard disc drives and other tracking devices where the systems demand a fast transition from a transient state to a steady state. Acknowledgement One of the authors (T. Banerjee) thankfully acknowledges the CSIR, India, for the financial support provided in carrying out this work. References [1] W.C. Lindsey, C.M. Chie, A survey of digital phase lock loops, Proc. IEEE. 69 (April 1981) 410–431. [2] M. Zoltowski, Some advances and refinements in digital phase locked loops (DPLLs), Signal Processing 81 (2001) 735–789. [3] T. Banerjee, B.C. Sarkar, Phase error dynamics of a class of DPLLs in presence of co channel interference, Signal Processing 85 (June 2005) 1139–1147.
[4] T. Banerjee, B.C. Sarkar, Phase error dynamics of a class of modified second order digital phase-locked loops in the background of co channel interference, Signal Processing 85 (August 2005) 1611–1622. [5] B.C. Sarkar, S. Chattopadhyay, Novel quick-response digital phase-locked loop, Electron. Lett. 24 (November 1988) 1263–1264. [6] Y. Tang, M. Ismail, S. Bibyk, A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers, Proceedings—IEEE Internat. Symp. Circuits Systems 4 (2002) IV/787–IV/790. [7] T.D. Chiueh, J.-B. Yang, J.-S. Wu, Design and implementation of a low-voltage fast-switching mixed-signal-controlled frequency synthesizer, IEEE Trans. Circuits Systems II: Analog Digital Signal Process. 48 (10) (2001) 961–971. [8] R. Kuppuswamy, K. Callahan, K. Wong, D. Ratchen, G. Taylor, On-die clock jitter detector for high speed microprocessors, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (CIRCUITS SYMP.), 2001, pp. 187–190. [9] H.C. Osborne, Stability analysis of an Nth power digital phase-locked loop—part II: second and third order DPLL’s, IEEE Trans. Commun. COM-28 (August 1980) 1355–1364. [10] G.M. Bernstein, M.A. Liberman, A.J. Lichtenberg, Nonlinear dynamics of a digital phase locked loop, IEEE Trans. Commun. 37 (October 1989) 1062–1070. [11] R.C. Hilborn, Chaos and Nonlinear Dynamics: an Introduction for Scientists and Engineers, Second edition, Oxford University press, Oxford, 2000.
Signal Processing 86 (2006) 1426–1434 www.elsevier.com/locate/sigpro
A new dynamic gain control algorithm for speed enhancement of digital-phase locked loops (DPLLs) T. Banerjee, B.C. Sarkar Physics Department, Burdwan University, Burdwan 703104, India Received 7 April 2005; received in revised form 15 July 2005 Available online 1 September 2005
Abstract A dynamic gain modification algorithm of a class of DPLLs has been proposed to improve its transient characteristics and tracking behavior. In this technique, rather taking a time invariant gain, the gain of the loop digital filter is made a function of the sampled value of the signal at every sampling instant. It has been shown analytically as well as numerically that the new structure is faster than the conventional one in its acquisition time and at the same time, it has a broader acquisition range. r 2005 Elsevier B.V. All rights reserved. Keywords: Zero-crossing digital-phase locked loop (ZC-DPLL); Loop gain; Transient response, stability criteria
1. Introduction Digital-phase locked loops (DPLLs) are essential building blocks in modern coherent communication systems as carrier regenerators, frequency synthesizers, bit synchronizers, hard disc drives, modems, etc. [1,2]. A high-speed communication system demands that a DPLL should be able to reach the steady state as quickly as possible without degrading the stability behavior of the loop. For conventional DPLLs (CDPLLs), it has been observed that, for a given set of systems and signal parameters, in order to achieve a faster transient response, the loop gain should be taken lower than the maximum allowable range and thus the acquisition range of the loop is reduced. Thus, faster transient response and broader acquisition range cannot be simultaneously achieved in a CDPLL. Another way to Corresponding author. Tel.: +091 03422556478.
E-mail address: [email protected] (T. Banerjee).
achieve faster transient characteristics is to make the order of the loop higher, which will increase the system complexity and make the system, sensitive to initial conditions. Research is going on [3–8] to alleviate this problem and a few techniques have been reported in the literature to design a DPLL, which satisfies all the above-mentioned criteria. In this paper we propose a new dynamic gain modification algorithm for enhancing the speed of transient response of an analog input positive zerocrossing DPLL (ZC1-DPLL) keeping the stability characteristic and the order of the loop unchanged. The proposed modification extends the range of application of the loop when there is a frequency detuning between the incoming signal and reference signal, i.e. the acquisition range of the loop increases. For the dynamic gain modification purpose, the gain of the loop digital filter (LDF) of ZC1-DPLL is controlled by the sampled value of the input signal at every sampling instant determined by the loop digitally controlled oscillator
0165-1684/$ - see front matter r 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sigpro.2005.07.028
ARTICLE IN PRESS T. Banerjee, B.C. Sarkar / Signal Processing 86 (2006) 1426–1434
Nomenclature: oi (rad/s) Angular frequency of the strong signal sðtÞ o0 (rad/s) Angular nominal frequency of the DCO A0 (volt) Amplitude of the strong signal sðtÞ z (dimensionless) oi/o0 L0 (rad) 2p(z1) dðp; qÞ A metric defined as min (|pq|, 2p|pq|). p, qA (0,2p) fðkÞ (rad) Phase error at the kth instant (DCO). In the transient mode of operation, loopphase error changes at each sampling instant and thus a non-zero control signal will be generated. This signal modifies the gain of the loop at every instance, in a direction such that the loop goes to the steady state from its transient state in a rapid manner. At the steady state, the control signal will become constant or zero, depending upon the nature of the loop and input signal parameters and thus the loop gain would become time invariant. The stability criteria of modified gain controlled DPLL (GCDPLL) has been derived analytically. To compare the transient characteristics of the two structures namely the GCDPLL and CDPLL, a computational method has been adopted, which gives a stochastic picture of the transient behavior of the loops. The present paper is organizsed in the following way. Section 2 describes the proposed structure modification for first-order and second-order DPLL and formulates the system equations. In Section 3, an analysis for the stability behavior of the firstorder and second-order GCDPLL is reported. Section 4 deals with the transient characteristics of the CDPLL and GCDPLL. Section 5 presents the numerical simulation results. Finally, some concluding remarks have been offered in Section 6.
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f (rad) Steady-state-phase error (used in fixed point solution) K 0 (rad) Gain of the first-order loop. K 1 (rad) Gain of the proportional arm of the second-order loop. K 2 (rad) Gain of the integrating arm of the second-order loop. r (dimensionless) 1 þ K 2 =K 1 C (dimensionless) ¼ L0/K0z L (dimensionless) ¼ (C/1+mC) SUMðkÞ (rad) ¼ Sk1 sin fðiÞ, a state variable i
shown in Figs. 1b and c, respectively. In CDPLLs the gain of the LDF, G0 (for first-order DPLL in unit of s/V, and G 1 and G 2 (for second-order DPLL, both have unit of s/V) are time invariant. But, in our proposed technique, gain parameters G 0M , G 1M , and G 2M are made to vary with the sampled signal xðkÞ (volt) at the sampler output at each sampling instant k (k ¼ 0; 1; 2 :::). Thus, the proposed algorithm modifies the gain of the LDF by the following relation: G iM ¼ G i ð1 þ bxðkÞÞ,
(1)
2. System description and system equation formulation 2.1. Description of the gain modification technique for first- and second-order DPLL Fig. 1a shows the functional block diagram of the GCDPLL with dynamic gain control technique. Structures of first-order and second-order LDF are
Fig. 1. (a). Functional block diagram of a dynamic gain controlled DPLL (GCDPLL). GM represents the modified gain of the loop digital filter. (b) Loop digital filter (LDF) for a firstorder CDPLL and (c) LDF for a second-order CDPLL.
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where i ¼ 0 for first-order DPLL and i ¼ 1,2 for second-order DPLL. Here, b (volt1) is a parameter used to quantify the effect of the structure modification. In the transient mode of operation, xðkÞ changes at each sampling instant and thus the gain also changes. At the steady state of operation, depending upon signal and system parameters, xðkÞ becomes constant or zero, so the gain of the LDF returns to its time invariant nature. 2.2. System equation formulation
signal can be written as yðkÞ ¼ G 0 ½1 þ bxðkÞxðkÞ
(8)
and for a second-order GCDPLL, the same is given by yðkÞ ¼ ðG 1 þ G 2 Þ½1 þ bxðkÞxðkÞ þ G 2 ½1 þ bxðkÞA0 SUMðkÞ,
ð9Þ
where SUMðkÞ (rad) has been defined as SUMðkÞ ¼
k1 X
sin fðiÞ:
(10)
i¼0
Noise free and unmodulated input signal of amplitude A0 (volt) is written in terms of the angular frequency (o0 rad/s) of the DCO as, SðtÞ ¼ A0 sinðo0 t þ yðtÞÞ, where we make the substitution yðtÞ ¼ ðoi o0 Þt þ y0 . Here, oi (rad/s) is the angular frequency of the input signal and y0 (rad) is a constant-phase part. SðtÞ is sampled by the positive zero crossing edge of the DCO at time instants tðkÞ (s). The time elapsed between (k1)th and kth instants is given by TðkÞ ¼ tðkÞ tðk 1Þ; k ¼ 1; 2; . . .
(2)
The sampled value of SðtÞ at tðkÞ is given by xðkÞ ¼ sðtðkÞÞ,
(3)
the sequence of the samples {x(k)}, k ¼ 0,1, y is filtered by the LDF and the filtered version of the samples, {y(k)} (having a dimension of time), controls the period of the DCO at (k+1)th instant with the following algorithm [1]: Tðk þ 1Þ ¼ T yðkÞ,
(4)
where T ( ¼ 2p/o0) is the nominal period of the DCO. Also, in our present system, xðkÞ is used to control the gain of the LDF as mentioned in (1). Using (2) and (4) and taking tð0Þ ¼ 0, one can get the sampling instants tðkÞ as tðkÞ ¼ kT
k1 X
yðiÞ.
(5)
0
We define the phase error fðkÞ at the kth instant as fðkÞ ¼ yðkÞ o0
k1 X
yðiÞ,
(6)
0
which in turn gives fðk þ 1Þ ¼ fðkÞ þ L0 zo0 yðkÞ,
(7)
where z ¼ ðoi =o0 Þ is the normalized input frequency and L0 is substituted in place of 2pðz 1Þ. Now, for a first-order GCDPLL, DCO control
Using (8) in (7), one gets the phase-governing equation for the first-order GCDPLL as fðk þ 1Þ ¼ L0 þ fðkÞ zK 0 ½1 þ m sin fðkÞ sin fðkÞ,
ð11Þ
where K 0 ð¼ A0 o0 G 0 Þ (rad) is the loop gain of the first-order GCDPLL and mð¼ bA0 Þ (a dimensionless quantity) is the normalized gain modification parameter. (11) represents the system equation for first-order CDPLL when m ¼ 0. Also, the phase-governing equation of the second-order GCDPLL can be achieved using (9) and (10) in (7), which gives fðk þ 1Þ ¼L0 þ fðkÞ zK 1 rf1 þ m sin fðkÞg sin fðkÞ zK 2 f1 þ m sin fðkÞg SUMðkÞ,
SUMðk þ 1Þ ¼ SUMðkÞ þ sin fðkÞ.
ð12aÞ (12b)
Here, we make the following substitutions, K 1 ¼ A0 o0 G1 , K 2 ¼ A0 o0 G2 , and r ¼ 1 þ ðK 2 =K 1 Þ. r is an additional design parameter for second-order GCDPLL. (12) represents the system equation for second-order CDPLL when m ¼ 0. 3. Stability criteria of first- and second-order GCDPLL In this section we investigate the effect of dynamic gain modification algorithm on the stability behavior of the loop. 3.1. Stability analysis of first-order GCDPLL Stability analysis of first-order CDPLL is well documented in [9], which gives the stability condition as 0oK 0 o2,
(13a)
0oðK 0 zÞ2 L20 o4.
(13b)
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To study the stability condition of a GCDPLL we write (11) as a mapping equation fðk þ 1Þ ¼ gðfÞ and find for its solution around a fixed point f . Now, the condition for the convergence (local) to a stable fixed point is given by the Ostrowski’s theorem [9], which is 0 n g ðf Þo1. (14)
approximate of estimate of the value of m for which fastest convergence can be achieved.
For a phase step input (z ¼ 1, i.e L0 ¼ 0), f ¼ 2np (n ¼ 0,1,2 ..) gives the stable loop operation. So the condition of local convergence is given by
0ozK 1 o
j1 K 0 jo1, i:e: 0oK 0 o2.
(15) (15a)
(15a) is similar to (13a), i.e. for a phase step input, stability condition of a GCDPLL remains the same as that of a CDPLL. For a frequency step input (za1), steady-state-phase error can be derived by putting fðk þ 1Þ ¼ fðkÞ ¼ f in (11), which gives sin fn ð1 þ m sin fn Þ ¼ C,
(16)
where C is substituted in place of ðL0 =K 0 zÞ (a dimensionless quantity). Now, to avoid mathematical complexity we consider the steady-state-phase error f is much smaller than 1 rad (which is actually the case in practical situation) and thus taking ð1 þ m sin fn Þ1 ¼ ð1 m sin fn Þ in (16), we get sin fn ¼ L.
(17)
where L is substituted for ðC=1 þ mCÞ. Using (17) in (14), we can write pffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffi (18) 1 zK 0 ð 1 L2 þ 2mL 1 L2 Þo1, This leads to the condition of local convergence to a steady state for GCDPLL, which is given by 0o½ðzK 0 Þ2 L20 ð1 þ 2mLÞ2 o4.
(19)
(19) reduces to the stability condition for CDPLL (13b) for m ¼ 0. (19) shows that, an appropriate value of m, depending upon different K 0 and z, extends the stability zone of the loop. Now, the condition for fastest convergence for frequency step input (za1) can be predicted by making g0 ðfn Þ ¼ 0, which gives " # 1 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 . m¼ (20) 2L zK 0 1 L2 Since, we have done a linearized analysis, the value of m obtained using (20) is not exact. But it gives an
3.2. Stability analysis of second-order GCDPLL The condition of stability a second-order CDPLL is given by [9] 4 . 1þr
(21)
The stability criterion of second-order GCDPLL can be studied by examining the behavior of (12) around the steady-state-phase error value f . The Jacobian of the map (12) is given by JðXÞ ¼
1 zK 1 rðcos f þ m sin 2fÞ zK 2 m SUM cos f
cos f
zK 2 ð1 þ m sin fÞ
1
! ,
ð22Þ where, X ¼ ðfðk þ 1Þ SUMðk þ 1ÞÞT . Examining (12), one can see that, like a CDPLLs, for a secondorder GCDPLL the steady-state-phase error is always zero or a integral multiple of p and at the steady-state SUMðkÞ ¼ ðL0 =zK 2 Þ. Since fixed points around ð2n þ 1Þp would give unstable solutions (as in the case of CDPLL), the fixed points around Xn ¼ 2np are choosen to linearize (22) which gives ! 1 zK 1 r mL0 1 n JðX Þ ¼ . (23) zK 2 1 Considering the characteristic equation JðXn Þ Ilj ¼ 0; to find eigenvalues, we get l2 ½2 zK 1 r mL0 l þ ½1 zK 1 mL0 ¼ 0. (24) According to the Ostrowski’s theorem [9], in order to reach the steady locked state, the eigenvalues of JðXn Þ, denoted by li , must satisfy the condition jli jo1; i ¼ 1; 2: Deriving the eigen values of (23) from (24) and after some algebraic transformations, one can easily get the condition for which system would attain a stable steady state, 0ozK 1 o
ð4 2L0 mÞ . 1þr
(25)
(25) reduces to (21) for m ¼ 0. A suitable value of m extends the stability zone of the GCDPLL. It can also be concluded that for a fixed K 1 , z can be varied to a larger value indicating that GCDPLL has a larger acquisition range compare to CDPLL. Examining (23), we see that, for the phase step input
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(z ¼ 1) the steady-state parameter SUMðkÞ is zero (since in that case L0 ¼ 0); so the effect of m is absent in the linearized Jacobian JðX Þ and we can not get any idea about the condition for fastest convergence for phase step input. But for a frequency step input (za1, i.e. L0 a0), condition of fastest convergence can be achieved by making the spectral radius of the Jacobian i.e. the largest eigenvalue of JðX Þ to zero, which leads to the condition, m¼
1 zK 1 . L0
(26)
For a second-order DPLL optimum loop conditions are obtained for K 1 ¼ 1 and r ¼ 2 [1]. In our present system, we find an optimum value of m keeping these parameters unchanged for different values of z. (26) shows that m becomes independent of z for K 1 ¼ 1 and its value is a constant equals to 0.159. This is a very useful result in the sense that one can choose the same value of m for different values of the signal detuning. 4. Transient response of the first- and second-order GCDPLL To examine the transient response of the GCDPLL and CDPLL, we examine the convergence rate of the system difference Eq. (11) for a first-order GCDPLL; for a second-order GCDPLL we rewrite the system Eq. (12) in the following manner: fðk þ 1Þ ¼ L0 þ fðkÞ zK 1 rf1 þ m sin fðkÞg sin fðkÞ zK 2 f1 þ m sin fðkÞg
k1 X
sin fðiÞ.
i¼0
ð27Þ Although the linear analysis of the rate of convergence [9] gives a satisfactory result for a very small phase error, it does not reflect the actual transient characteristics for the whole set of possible initial conditions. In [10], an average convergence rate was computed by examining the contraction of phase space near the fixed point and size of the phase space. This method is reliable in the sense that, it incorporates the transient behavior of the loop for the entire range of initial conditions within the acquisition range and gives a stochastic picture of the convergence rate. In our present system, we will use the procedure of computing the stochastic average of the convergence rate. To compute the average convergence rate, we constitute a computationally
convenient metric [10] for our present system. We define the metric dðp; qÞ for the circle [0,2p] as dðp; qÞ ¼ minðjp qj; 2p jp qjÞ, p; q 2 ½0; 2p.
ð28Þ
It can be shown that dðp; qÞ satisfies all the properties of a metric. For our present system p is replaced by the initial phase error f and q is replaced by the steady-state-phase error f . Since, the convergence time depends on the initial condition of f, so, to take it into account for calculating average convergence rate, we compute a root mean square (rms) statistics for N 0 number of initial points, which gives the average number of iterations to reach a value f from an initial value f. The parameter quantifying the average convergence rate is given by vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u N0 u1 X RMSðkÞ ¼ t (29) dðfk;i ; fn Þ2 , N 0 i¼0 where, k is the number of iteration count. Less the value of k, better is the speed of convergence of the system. While dealing with (29), we have to put the proper values of f for phase step input and frequency step input for first- and second-order DPLL, as discussed earlier. The numerical simulation result using (29) has been shown in the next section. 5. Simulation results Numerical simulation study has been carried out with the help of the phase governing Eq. (11) (for the first-order case) and (12) (for the second-order case) and also by considering the hardware structure of the system given in Fig. 1. 5.1. Regarding the stability of GCDPLL To show the stable region of operation of the loop, we make use of the maping diagrams [11] of the first- and second-order DPLLs. These diagrams have been drawn by plotting the steady-state-phase values with different gain values of the loop. Fig. 2 shows the maping diagram of a first-order GCDPLL for a phase step input (z ¼ 1) and it clearly shows that the stable loop operation does not alter from that of a CDPLL. For a frequency step input (za1), GCDPLL shows larger stable zone of operation if we choose a proper value of m. Fig. 3 shows this situation with z ¼ 1:1.
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For a second-order GCDPLL, maping diagrams are drawn with K 1 as a control parameter (with r ¼ 2, which is one of the optimum loop parameter). The loop operation has been studied taking fð0Þ as any value within a range p to p in the acquisition region and Sð0Þ ¼ 0. Also we choose the value for m ¼ 0:159 for GCDPLL as predicted earlier in (26). Fig. 4 shows that, for phase step input, the steady-state-phase error of GCDPLL and CDPLL bifurcates at the same value of K 1 . This means that two systems have the same stable zone of operation (0oK 1 zo1:33 ith r ¼ 2); this result supports the analytical prediction of (25). For a frequency step input (za1), a larger stable zone of operation is obtained for a GCDPLL than that of a CDPLL. This has been shown in Fig. 5 in r K 1 plane. Also, the acquisition range of second-order GCDPLL compare to CDPLL is plotted in Fig. 6, which shows that GCDPLL has a larger acquisition range than that of the CDPLL for frequency step input. These results are well in agreement with the analytical derivations of the earlier sections.
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Fig. 3. Mapping diagram of a first-order GCDPLL (m ¼ 0:25) and CDPLL in the face of a frequency step input (z ¼ 1:1).
5.2. Regarding the transient response of a GCDPLL Transient response of the first- and second-order DPLLs are studied by examining the RMSðkÞ values with the number of iterations (k) and also by investigating the real time behavior of the loopphase error. All possible values of system and signal
Fig. 4. Mapping diagram of a second GCDPLL (m ¼ 0:25) and CDPLL in the face of a phase step input (z ¼ 1, r ¼ 2).
Fig. 2. Mapping diagram of a first-order GCDPLL (m ¼ 0:35) and CDPLL in the face of a phase step input (z ¼ 1).
parameters have been chosen but more interests have been given on the larger acquisition range condition. Since for a phase step input linearize Jacobian method does not give any prediction about the optimum value of m for fastest convergence, we have to rely on the numerical searching; and it shows that fastest convergence is achieved for
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Fig. 5. Plot showing the stable zone of GCDPLL (m ¼ 0:159) and CDPLL in r K 1 plane (with z ¼ 1:32).
For a second-order GCDPLL, in the face of a phase step input, numerical study reveals that the fastest convergence occurs at m ¼ 0:25. Fig. 9a shows the comparison between the transient of CDPLLL and GCDPLL for a phase step input (with K 1 ¼ 1, r ¼ 2). For frequency step input, fastest convergence is achieved for the m value as predicted in (26). Fig. 9b shows the comparative transient response of GCDPLL and CDPLL with z ¼ 1:32 and corresponding value of m ( ¼ 0.159) obtained from (26) (taking K 1 ¼ 1, r ¼ 2). It can be seen that GCDPLL is much faster than CDPLL. Real time plots depicting the comparison of GCDPLL and CDPLL are shown in Figs. 10 and 11, which also confirms the enhancement of speed in GCDPLL. All the simulation results show that a GCDPLL can be made faster than a CDPLL by choosing a suitable value of m, as predicted analytically and numerically, without degrading the stability behavior or making the order of the loop higher. Further, for practical situation (e.g. condition for the frequency step input) GCDPLL enhance the speed of convergence and extends the stability range simultaneously, which clearly shows the superiority of GCDPLL over a CDPLL.
2.0 CDPLL RMS (k)
1.5
Fig. 6. Plot (z vs. K 1 ) showing that second-orders GCDPLL (m ¼ 0:159) has larger acquisition range compare to CDPLL for frequency step input (za1).
GCDPLL
1.0 0.5 0.0 0
(a)
10
30
20
RMS (k)
1.6
m ¼ 0:35. Fig. 7a shows the plot of RMSðkÞ with k for a first-order GCDPLL in the face of phase step input with (for z ¼ 1:1, K 0 ¼ 1:85). For frequency step input, fastest convergence occurs near the m ¼ 0:25 which is not exact but of the order of values derived analytically in (20). Fig. 7b shows this situation (for z ¼ 1:1, K 0 ¼ 1:85) and clearly indicates that GCDPLL has faster convergence characteristics than that of the CDPLL (i.e. GCDPLL takes less number of iteration step k than that of a CDPLL). Real time transient characteristics are shown in Fig. 8, which also supports this observation.
0.8
0.0 (b)
0
5
10 k
15
20
Fig. 7. RMSðkÞ versus number of iteration count (k) for a firstorder GCDPLL and CDPLL (m ¼ 0) for (a) z ¼ 1, K 0 ¼ 1:85, m ¼ 0:35 (b) z ¼ 1:1, K 0 ¼ 1:85, m ¼ 0:25. Note that GCDPLL takes less number of step (k) to reach the steady state compare to that of a CDPLL.
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1.0
1433 CDPLL
0.5
3
GCDPLL
0.0
0.5
0.0 0
20
40
60
80
100
φ(k), rad
φ(k), rad
CDPLL
-0.5 12
16
20
24
28
0
1.0
φ(k), rad
GCDPLL 0.5
-3 0
5
10
0.0 0
20
40
60
80
100
k Fig. 8. Real time plot of the transient response of first-order GCDPLL (m ¼ 0:25) and CDPLL with z ¼ 1:1, K 0 ¼ 1:85 and initial phase is equal to 1 rad.
15 k
20
30
Fig. 10. Real time plot of the transient response of second-order GCDPLL (m ¼ 0:25) and CDPLL (with z ¼ 1, K 1 ¼ 1, r ¼ 2 and initial phase is equal to 2.5 rad). Inset shows the blow up of the same.
3
1.8
CDPLL
CDPLL
GCDPLL 1.2
φ(k), rad
RMS (k)
25
0.6
0
0.0 0
(a)
5
10
15
20
-3
0.8
3 φ(k), rad
RMS (k)
GCDPLL 0.4
0
-3 0
0.0 (b)
0
50
100
20
40
60 k
80
100
120
150
k Fig. 9. RMSðkÞ versus number of iteration count (k) for a second-order GCDPLL and CDPLL for (a) z ¼ 1, K 1 ¼ 1, r ¼ 2, m ¼ 0:25 (b) z ¼ 1:32, K 1 ¼ 1, r ¼ 2, m ¼ 0:159. Note that GCDPLL takes less number of step (k) to reach the steady state compare to that of a CDPLL.
6. Conclusion An algorithm for enhancing the speed of a class of DPLLs has been proposed. This algorithm also
Fig. 11. Real time plot of the transient response of second-order GCDPLL (m ¼ 0:159) and CDPLL (with z ¼ 1:32, K 1 ¼ 1, r ¼ 2 and initial phase is equal to 2.5 rad).
extends the acquisition range for frequency step input and does not affect the stability behavior for phase step input. Also it has been shown that transient behavior of DPLLs can be improved without increasing the order of the DPLLs. It has been established through analytical tools and numerical simulation studies that the GCDPLLs
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are superior to that of the CDPLLs in both transient and steady state of loop operation. Numerical simulation results are in well agreement with the analytical derivations. From practical aspects, this modification can be used in frequency synthesizers, modems, hard disc drives and other tracking devices where the systems demand a fast transition from a transient state to a steady state. Acknowledgement One of the authors (T. Banerjee) thankfully acknowledges the CSIR, India, for the financial support provided in carrying out this work. References [1] W.C. Lindsey, C.M. Chie, A survey of digital phase lock loops, Proc. IEEE. 69 (April 1981) 410–431. [2] M. Zoltowski, Some advances and refinements in digital phase locked loops (DPLLs), Signal Processing 81 (2001) 735–789. [3] T. Banerjee, B.C. Sarkar, Phase error dynamics of a class of DPLLs in presence of co channel interference, Signal Processing 85 (June 2005) 1139–1147.
[4] T. Banerjee, B.C. Sarkar, Phase error dynamics of a class of modified second order digital phase-locked loops in the background of co channel interference, Signal Processing 85 (August 2005) 1611–1622. [5] B.C. Sarkar, S. Chattopadhyay, Novel quick-response digital phase-locked loop, Electron. Lett. 24 (November 1988) 1263–1264. [6] Y. Tang, M. Ismail, S. Bibyk, A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers, Proceedings—IEEE Internat. Symp. Circuits Systems 4 (2002) IV/787–IV/790. [7] T.D. Chiueh, J.-B. Yang, J.-S. Wu, Design and implementation of a low-voltage fast-switching mixed-signal-controlled frequency synthesizer, IEEE Trans. Circuits Systems II: Analog Digital Signal Process. 48 (10) (2001) 961–971. [8] R. Kuppuswamy, K. Callahan, K. Wong, D. Ratchen, G. Taylor, On-die clock jitter detector for high speed microprocessors, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (CIRCUITS SYMP.), 2001, pp. 187–190. [9] H.C. Osborne, Stability analysis of an Nth power digital phase-locked loop—part II: second and third order DPLL’s, IEEE Trans. Commun. COM-28 (August 1980) 1355–1364. [10] G.M. Bernstein, M.A. Liberman, A.J. Lichtenberg, Nonlinear dynamics of a digital phase locked loop, IEEE Trans. Commun. 37 (October 1989) 1062–1070. [11] R.C. Hilborn, Chaos and Nonlinear Dynamics: an Introduction for Scientists and Engineers, Second edition, Oxford University press, Oxford, 2000.