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A new high temperature multilayer capacitor with acrylate dielectrics
1038
World Abstracts on Microelectronics and Reliability 2. R E L I A B I L I T Y
OF
COMPONENTS,
A new high temperature multilayer capacitor with acrylate dielectrics. ANGELO YIALIZlS, GARY L. POWERS and DAVID G. SHAW. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 611 (1990). Polymer multilayer (PML) monolithic capacitors have been produced by a continuous high-speed vacuum process. The polymer dielectric is formulated by flash evaporating an acrylate monomer material onto a rotating drum and then cross linking it by electron beam irradiation. The resulting polymer is thermally stable at temperatures in excess of 300°C. The dielectric films are pin hole free with stable electric properties. The capacitor electrodes are vapor deposited aluminum that are thin enough to allow the capacitor to self-heal. The number of layers varies typically between 1000 and 5000 and the dielectric thickness between 0.3 and 1.0#m. The low dielectric thickness results in capacitor chips with high volumetric efficiency that can be surface mounted by conventional soldering techniques. This paper provides an overview of the vacuum process, chip cutting, termination, packaging, electrical characteristics, and general test methodology. Structural, optical and electronical properties of mixed dielectric films. R. THIELSCH, W. MEILING and E. GORING. Vacuum 41(4-6), 1147 (1990). Homogeneous and inhomogeneous mixed films of the type X-ZrO2(X = MgF:, SiO2) applicable to interference optics were deposited on heated and unheated substrates by coevaporation using separate electron-beam evaporators with closed-loop rate control and thickness monitoring by quartz crystal oscillators. Optical and structural properties of homogeneous mixed films have been studied by means of optical spectroscopy (uv, vis, ir), X-ray diffraction and RBS. The dependence of refraction index on film composition was compared with well-known mixing models. For deposition on unheated substrates the best agreement was obtained with the Lorentz-Lorenz model. On heated substrates an anomaly of refraction index dependent on SiO2-ZrO2 film composition can be interpreted as a packing density effect. Infrared-absorption bands at wavenumbers of 980 cm-~ and 910 cm-' refer to Si43-Zr bonds in the films. In MgF2-ZrO 2 mixed films, which were deposited on heated substrates, strong uv-vis absorption is observed. Further, the influence of the ZrO 2 volume fraction on the optical gap energy Eg has been studied. Thermally induced IC package cracking. DAviD SUHL. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 940 (1990). The presence of plastic package cracks due to the thermal stress of assembly procedures in low cost plastic packages represents a severe long term reliability hazard. It has been shown previously that the dominant cracking mechanism is moisture expansion due to thermal processing acting on concentrations of water vapor at the back surface of the die paddle (that part of the leadframe to which the silicon die is attached), and at the front surface of the silicon die. It is also known that the magnitude of the problem is dependent on the thermal gradient, built-in molding stress, plastic yield strength, and silicon die size. The methods are discussed which have demonstrated improved resistance to plastic package cracking. Each of these methods have separate advantages and disadvantages which are detailed and examined in terms of the overall manufacturability of the components. The problems encountered when trying to side step the thermal cracking problem by the use of sockets are discussed. Ceramic packages also suffer thermally induced cracks, including pin grid array (PGA) packages which only experience the relatively mild thermal exposure of standard wave soldering. The parameters involved in this phenomenon are detailed.
TUBES,
TRANSISTORS
AND
ICs
A comparison of copper and gold wire bonding on integrated circuit devices. SALIM. L. KHOURY et al. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 673 (1990). The development of a new assembly process involves a wide variety of issues which must be addressed. Using the current standard production gold wire process as a baseline, a comparative approach was used to develop new copper wire bond technology. Characterizations were made in the areas of assembly processes and material selection, electrical and thermal performance, intermetallic formation on Al and Al alloy bond pads, and reliability testing. An evaluation on die shear strength was done on bare copper, plated copper, thin silver plate, and standard silver plated leadframes. One and two-part silver filled epoxy die attach materials were used in this experiment with short and standard cure times. Temperature cycling and high temperature storage were used to further differentiate the variables and to give an indication of die bond reliability. Experiments were run to select proper materials (lead frame, bonding wire, and die attach) for copper bonded devices. Lead frames from several sources were tested as well as different surface treatments. Bonding wires were selected based on bond ability studies. Die attached materials were evaluated for process performance. Ball shear and wire pull testing showed that copper wire bond strength was greater than gold wire bond strength when bonds were made with 25.4 #m diameter wire. Ball shear results showed that copper ball bonds sheared at an average of 85-1 l0 gf, whereas gold ball bonds sheared at an average of 60-80 gf. Wire pull data indicated that copper wire pull strength averaged 11-13 gf, while gold wire pull strength averaged 8-10 gf. Analysis between copper and gold wire for various integrated circuit (IC) types were performed to evaluate electrical performance in relation to temperature, thermal transient response, input/output impedance, and capacitance. Different metallization structure, power dissipation, and metal alloys were employed. Three bond pad metallizations were compared to determine the effect of composition on the intermetallic growth in copper and gold ball bonds. Reliability testing such as temperature cycling, operating life and pressure temperature humidity under bias (PTHB) were used for this experiment. Results showed that Au/A1 intermetallic thickness was more than one order of magnitude greater than Cu/Al intermetallic thickness. As a result of this new process development, an extensive reliability qualification plan was defined. Tests indicated that no significant degradation occurred after 4000 h of operating life, 4000 cycles of temperature cycling, 2000 h of high temperature storage, 1000 cycles of thermal shock, 528 h of PTHB, 1000 h of temperature humidity under bias (THB), and 200 h of highly accelerated stress test (HAST).
A relational database for semiconductor device parametric data. JERY HARVEY and EUG~.NE DYATI~WTSKY. I E E E Trans. Semicond. Mfg 3(3), 136 (1990). Semiconductor device parametric test data collected by lot, wafer, and die, forms a hierarchical data structure that lends itself to two relational models, reflecting two data views. The two models may be integrated by a careful consideration of relationships, and the resultant structure is applicable to in-process data collection. The purpose of this paper is to discuss semiconductor device parametric data models from two viewpoints, and to develop a practical database based on the set-theoretic relational data model. Application of the developed model to semiconductor in-process and functional test data is also discussed.
World Abstracts on Microelectronics and Reliability 2. R E L I A B I L I T Y
OF
COMPONENTS,
A new high temperature multilayer capacitor with acrylate dielectrics. ANGELO YIALIZlS, GARY L. POWERS and DAVID G. SHAW. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 611 (1990). Polymer multilayer (PML) monolithic capacitors have been produced by a continuous high-speed vacuum process. The polymer dielectric is formulated by flash evaporating an acrylate monomer material onto a rotating drum and then cross linking it by electron beam irradiation. The resulting polymer is thermally stable at temperatures in excess of 300°C. The dielectric films are pin hole free with stable electric properties. The capacitor electrodes are vapor deposited aluminum that are thin enough to allow the capacitor to self-heal. The number of layers varies typically between 1000 and 5000 and the dielectric thickness between 0.3 and 1.0#m. The low dielectric thickness results in capacitor chips with high volumetric efficiency that can be surface mounted by conventional soldering techniques. This paper provides an overview of the vacuum process, chip cutting, termination, packaging, electrical characteristics, and general test methodology. Structural, optical and electronical properties of mixed dielectric films. R. THIELSCH, W. MEILING and E. GORING. Vacuum 41(4-6), 1147 (1990). Homogeneous and inhomogeneous mixed films of the type X-ZrO2(X = MgF:, SiO2) applicable to interference optics were deposited on heated and unheated substrates by coevaporation using separate electron-beam evaporators with closed-loop rate control and thickness monitoring by quartz crystal oscillators. Optical and structural properties of homogeneous mixed films have been studied by means of optical spectroscopy (uv, vis, ir), X-ray diffraction and RBS. The dependence of refraction index on film composition was compared with well-known mixing models. For deposition on unheated substrates the best agreement was obtained with the Lorentz-Lorenz model. On heated substrates an anomaly of refraction index dependent on SiO2-ZrO2 film composition can be interpreted as a packing density effect. Infrared-absorption bands at wavenumbers of 980 cm-~ and 910 cm-' refer to Si43-Zr bonds in the films. In MgF2-ZrO 2 mixed films, which were deposited on heated substrates, strong uv-vis absorption is observed. Further, the influence of the ZrO 2 volume fraction on the optical gap energy Eg has been studied. Thermally induced IC package cracking. DAviD SUHL. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 940 (1990). The presence of plastic package cracks due to the thermal stress of assembly procedures in low cost plastic packages represents a severe long term reliability hazard. It has been shown previously that the dominant cracking mechanism is moisture expansion due to thermal processing acting on concentrations of water vapor at the back surface of the die paddle (that part of the leadframe to which the silicon die is attached), and at the front surface of the silicon die. It is also known that the magnitude of the problem is dependent on the thermal gradient, built-in molding stress, plastic yield strength, and silicon die size. The methods are discussed which have demonstrated improved resistance to plastic package cracking. Each of these methods have separate advantages and disadvantages which are detailed and examined in terms of the overall manufacturability of the components. The problems encountered when trying to side step the thermal cracking problem by the use of sockets are discussed. Ceramic packages also suffer thermally induced cracks, including pin grid array (PGA) packages which only experience the relatively mild thermal exposure of standard wave soldering. The parameters involved in this phenomenon are detailed.
TUBES,
TRANSISTORS
AND
ICs
A comparison of copper and gold wire bonding on integrated circuit devices. SALIM. L. KHOURY et al. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 673 (1990). The development of a new assembly process involves a wide variety of issues which must be addressed. Using the current standard production gold wire process as a baseline, a comparative approach was used to develop new copper wire bond technology. Characterizations were made in the areas of assembly processes and material selection, electrical and thermal performance, intermetallic formation on Al and Al alloy bond pads, and reliability testing. An evaluation on die shear strength was done on bare copper, plated copper, thin silver plate, and standard silver plated leadframes. One and two-part silver filled epoxy die attach materials were used in this experiment with short and standard cure times. Temperature cycling and high temperature storage were used to further differentiate the variables and to give an indication of die bond reliability. Experiments were run to select proper materials (lead frame, bonding wire, and die attach) for copper bonded devices. Lead frames from several sources were tested as well as different surface treatments. Bonding wires were selected based on bond ability studies. Die attached materials were evaluated for process performance. Ball shear and wire pull testing showed that copper wire bond strength was greater than gold wire bond strength when bonds were made with 25.4 #m diameter wire. Ball shear results showed that copper ball bonds sheared at an average of 85-1 l0 gf, whereas gold ball bonds sheared at an average of 60-80 gf. Wire pull data indicated that copper wire pull strength averaged 11-13 gf, while gold wire pull strength averaged 8-10 gf. Analysis between copper and gold wire for various integrated circuit (IC) types were performed to evaluate electrical performance in relation to temperature, thermal transient response, input/output impedance, and capacitance. Different metallization structure, power dissipation, and metal alloys were employed. Three bond pad metallizations were compared to determine the effect of composition on the intermetallic growth in copper and gold ball bonds. Reliability testing such as temperature cycling, operating life and pressure temperature humidity under bias (PTHB) were used for this experiment. Results showed that Au/A1 intermetallic thickness was more than one order of magnitude greater than Cu/Al intermetallic thickness. As a result of this new process development, an extensive reliability qualification plan was defined. Tests indicated that no significant degradation occurred after 4000 h of operating life, 4000 cycles of temperature cycling, 2000 h of high temperature storage, 1000 cycles of thermal shock, 528 h of PTHB, 1000 h of temperature humidity under bias (THB), and 200 h of highly accelerated stress test (HAST).
A relational database for semiconductor device parametric data. JERY HARVEY and EUG~.NE DYATI~WTSKY. I E E E Trans. Semicond. Mfg 3(3), 136 (1990). Semiconductor device parametric test data collected by lot, wafer, and die, forms a hierarchical data structure that lends itself to two relational models, reflecting two data views. The two models may be integrated by a careful consideration of relationships, and the resultant structure is applicable to in-process data collection. The purpose of this paper is to discuss semiconductor device parametric data models from two viewpoints, and to develop a practical database based on the set-theoretic relational data model. Application of the developed model to semiconductor in-process and functional test data is also discussed.