- Email: [email protected]
High temperature characterization of high-κ dielectrics on SiC
ARTICLE IN PRESS
Materials Science in Semiconductor Processing 9 (2006) 1133–1136
High temperature characterization of high-k dielectrics on SiC M.H. Weng, R. Mahapatra, P. Tappin, B. Miao, S. Chattopadhyay, A.B. Horsfall, N.G. Wright School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle, NE1 7RU, UK Available online 22 November 2006
Abstract We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO2 as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 1C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 1C. The results show that at temperatures below 400 1C the capacitors are stable, with a density of interface traps of approximately 6 1011 cm2 eV1. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1 1013 cm2 eV1, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 1C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO2 layer above 300 1C. These results at high temperatures confirms the suitability of the Pd/TiO2/SiO2/SiC capacitor structure for stable operation in high temperature environments. r 2006 Elsevier Ltd. All rights reserved. Keywords: Silicon carbide; High-k; Temperature; Interface
1. Introduction Silicon carbide offers great opportunities for the development of electronic devices to operate at temperatures substantially above those possible using traditional silicon based electronics. The wide bandgap, high critical breakdown field and high electron saturation velocity have made this the semiconductor of choice for high temperature operation, and devices have been demonstrated operating at temperatures beyond 600 1C. Despite the exceptional material properties of silicon carCorresponding author.
E-mail address: [email protected] (A.B. Horsfall). 1369-8001/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mssp.2006.10.032
bide, the desire to fabricate MOSFETs requires the development of high quality, reliable dielectric layers, which can function as a gate oxide. Traditional SiO2 layers have two main disadvantages for use in these conditions. The lifetime for SiO2 has been shown to be severely reduced at temperatures above 300 1C [1]. The dielectric constant of SiO2 is only 3.9, which gives an electric field in the oxide which is higher than in the silicon carbide according to Gauss’ law E ox ¼
kSiC E SiC . kox
(1)
The high critical electric field in the silicon carbide (2.5 MV cm1) would give an unacceptably high
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
electric field in the oxide (6.2 MV cm1) which would also reduce the lifetime of the oxide. The use of high permittivity dielectric materials (high k) as gate dielectrics has received a great deal of attention in silicon technology, where the increase in physical thickness, maintaining the low equivalent thickness is enabling the reduction in device dimensions required to meet Moore’s Law. Recently, various high k dielectric materials have generated a lot of interest as alternative gate dielectrics for SiC-based metal–insulator–semiconductor (MIS) device applications [2,3]. The motivation for such studies is to find a higher dielectric constant replacement for SiO2 in metal–oxide–semiconductor (MOS) capacitors prepared on SiC, in order to take advantage of the higher breakdown voltage achievable with SiC as compared to Si. Most of the studies concern themselves with the behaviour of the insulator and its effect on the related devices at or near room temperature. In this study, we report the high temperature characteristics of TiO2/SiO2 high-k dielectric stack on 4H-SiC surfaces to satisfy the development of electronics for deployment in extreme environments.
2. Experimental Commercial, research grade N-type 4H-SiC wafers from Cree Inc with a 2.9 mm thick epilayer with a nitrogen doping concentration of 2.6 1016 cm3 were used to fabricate MIS capacitors. A conventional RCA clean was performed and the wafers were then dipped into a dilute HF solution to remove the native oxide from the SiC surface prior to oxidation. Thermal oxide of 25 nm thickness was grown at 1150 1C in dry O2 ambient prior to titanium (Ti) deposition. Titanium film of 50 nm thickness was deposited on SiO2/SiC layers by the thermal evaporation with a base pressure of 5 106 Torr, followed by thermal oxidation in dry O2 ambient at 800 1C to form the 75 nm thick TiO2 layer. Subsequently, 50 nm of palladium was deposited and patterned to complete the MIS capacitors. Electrical properties of the Pd/TiO2/SiO2/SiC gate dielectric stack over a temperature range of 100–650 1C were determined by measuring highfrequency capacitance–voltage (C–V) and current–voltage (I–V) characteristics using a HP4284 LCR meter and Keithley 2400 source-measure unit in conjunction with a computer controlled hot plate.
3. Results and discussion Fig. 1 exhibits the high frequency (1 MHz) capacitance–voltage (C–V) characteristics of the Pd/TiO2/SiO2/SiC MIS capacitor at temperatures between 100 and 600 1C. Notably, there is no change of the accumulation capacitance in the temperature range studied, indicating its suitability for operation at elevated temperatures. The effective oxide thickness is found to be 17.5 nm, which is thinner than the initial SiO2 layer and this suggests a reaction between the TiO2 and SiO2 during thermal oxidation of Ti. The existence of a SiTiCO based layer in between the TiO2 and the SiC has been confirmed by X-Ray Photoelectron Spectroscopy measurements [4]. The C–V curves shift towards the left along the voltage axis at relatively higher temperatures and this may be attributed to the combined effect of temperature dependent parameters of the semiconductor, such as the shift in Fermi level and variation of charge trapping characteristics at in the interfaces. At higher temperatures (T4400 1C) a hump in the capacitance is visible in the depletion region, which suggests the existence of another set of near interface traps (NITs) with different life time and capture crosssection that do not respond to the 1 MHz frequency at low temperatures. These NITs or ‘slow states’ are located close to the conduction band edge and have a strong influence on the mobility of carriers in the inversion layer [5]. At 600 1C, the accumulation capacitance of the stack shows a small decrease, suggesting that this represents the upper operating
220 200 180 Capacitance (pF)
1134
160 140 120 100°C 200°C 300°C 400°C 500°C 600°C
100 80 60 40 20 0 -1
0
1
2
3
4
5
Gate Voltage (V) Fig. 1. High-frequency (1 MHz) capacitance–voltage characteristics of MIS capacitors on SiC at different temperatures.
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
Conductance (µS)
240 220 200 180 160 140 120 100 80 60 40 20 0
100°C 200°C 300°C 400°C 500°C 600°C
-2
-1
0
2 1 Gate Voltage (V)
3
4
5
Fig. 2. High-frequency (1 MHz) conductance–voltage characteristics at different temperatures.
1013 Density of Interface Traps (cm2 eV-1)
condition for the capacitor in air. Other work with Pd contacts to silicon carbide devices suggests that this limitation is linked to the oxidation of the Pd contact and the upper operating temperature may be increased by selecting a more oxidation resistant material, such as platinum [6]. Fig. 2 shows the corresponding the high frequency (1 MHz) conductance–voltage (G–V) characteristics of the Pd/TiO2/SiO2/SiC MIS capacitor. The data shows the existence of two distinct conductance peaks related to the interface traps, one located at approximately 1.5 V and another at 2.5 V which appears for temperatures above 400 1C. The movement of the peak at 1.5 V with temperature is consistent with the shifting of the C– V curves at higher temperatures. The second peak at 2.5 V may be attributed to ‘slow states’ and is also observed in the C– V characteristics at high temperatures, as shown in Fig. 1. This second peak is thought to be linked to the existence of another set of interface states with different activation energy and capture cross-section and that are activated at higher temperature. The existence of two different peaks also suggests that there may be discrete patches with different activation energies rather continuous distribution of interface states are present in the Pd/TiO2/SiO2/SiC MIS system. The higher value of the conductance peaks indicates higher interface state density which has been extracted in Fig. 3. From the C– V and G– V characteristics at 1 MHz, the interface state density at the interface of the dielectric stack and the silicon carbide has
1135
1012
1011 0
100 200 300 400 500 600 700 Temperature (°C)
Fig. 3. The distribution of interface state density (Dit) as a function of elevated temperatures.
been calculated using the Hill–Coleman method [7]; Dit ¼
ð2=q AÞ ðG max =wÞ , ðG max =w:C ox Þ2 þ ð1 C m =C ox Þ2
(2)
where q is the electronic charge, A is the sample area, w is the angular frequency, Cox is the oxide capacitance, Gmax is the maximum conductance in G– V plot with its corresponding capacitance (Cm). The distribution of the density of interface states (Dit) is observed in the two trends shown in Fig. 3. For temperatures below 500 1C, the density of interface states at midgap are found to be 6.0 1011 cm2 eV1, which are consistent results reported in the literature [8–10] for SiO2 and high k dielectric films on 4H silicon carbide. The density of states is insensitive to the variation of temperature over this range, which is expected from the invariance in C– V characteristics. At temperatures above 500 1C, interface state density at midgap increases, reaching 2 1012 cm2 eV1 at 650 1C. It is also noted that the second peaks which appear in the G– V curves at higher temperatures may be used to give a density of interface states, with a value of 2 1013 cm2 eV1. This is similar to the density of interface states close to the conduction band edge in the 4H silicon carbide— SiO2 system [11], the so-called ‘slow states’ [5] and we propose that these states are dominating the characteristics of the interface at high temperatures. The current versus voltage characteristics have been measured to study the breakdown field of the dielectric stack films at different temperatures. The variation of breakdown voltage as a function of temperature is shown in Fig. 4. The effective breakdown field is calculated to be 9 MV/cm at
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
1136
in extreme environments is presented. We show for the first time, that the use of high k dielectric films is suitable for use in temperatures up to 600 1C. However, at high temperatures, the influence of a second set of interface traps, which may be located close to the conduction band edge of the silicon carbide dominate the C– V and G– V characteristics.
Breakdown Voltage (V)
17 15 13 11 9 7 5 3
References
1 0
100
200
300
400
500
Temperature (°C) Fig. 4. Breakdown voltage of the MIS capacitor as a function of temperatures.
temperatures below 100 1C. As the temperature is increased, the breakdown voltage reduces monotonically with a strong dependence up to 300 1C and after that it is found to be almost constant at 2.2 MV cm1 when the temperature is increased to 500 1C. With the reduction in oxide quality at temperatures above 300 1C, we suggest that the low temperature breakdown voltage is determined by the electric field in the SiO2, whilst above 300 1C, the electric field in the TiO2 film defines the breakdown voltage. 4. Conclusions The temperature stability of a Pd/TiO2/SiO2/SiC dielectric stack for use in electronics for deployment
[1] Anthony CJ, Jones AJ, Uren MJ. Mater Sci Eng 1999;62:460. [2] Pe´rez-Toma´s A, Mestres N, Godignon P, Montserrat J, Milla´n J. Appl Surf Sci, in press. [3] Wolborski M, Bakowski M, Pore V, Ritala M, Leskela¨ M, Scho¨ner A, et al. Mat Sci Forum 2005;483–485:701. [4] Mahapatra R, Poolamai N, Chattopadhyay S, Wright NG, Chakraborty AK, Coleman KS, et al. Appl Phys Lett 2006;88:072910. [5] Rudenko TE, Osiyuk IN, Tyagulski IP, O´lafsson HO¨, Sveinbjo¨rnsson EO¨. Solid-State Electron 2005;49:545. [6] Hunter GW, Neudeck PG, Chen L-y, Knight D, Liu CC, Wu QH. Mat Sci Forum 1998;264–268:1093. [7] Hill WA, Coleman CC. Solid State Electron 1980; 23:987. [8] Fukuda K, Kato M, Kojima K, Senzaki J. Appl Phys Lett 2004;84:2088. [9] Gao KY, Seyller Th, Ley L, Ciobanu F, Pensl G, Tadich A, et al. Appl Phys Lett 2003;83:1830. [10] Dhar S, Song YW, Feldman LC, Isaacs-Smith T, Tin CC, Williams JR, et al. Appl Phys Lett 2004;84:498. [11] Afanas’ev VV, Ciobanu F, Pensl G, Stresmans A. In: Choyke WJ, Matsunami H, Pensl G, editors. Silicon carbide recent major advances. Berlin: Springer; 2004.
Materials Science in Semiconductor Processing 9 (2006) 1133–1136
High temperature characterization of high-k dielectrics on SiC M.H. Weng, R. Mahapatra, P. Tappin, B. Miao, S. Chattopadhyay, A.B. Horsfall, N.G. Wright School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle, NE1 7RU, UK Available online 22 November 2006
Abstract We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO2 as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 1C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 1C. The results show that at temperatures below 400 1C the capacitors are stable, with a density of interface traps of approximately 6 1011 cm2 eV1. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1 1013 cm2 eV1, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 1C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO2 layer above 300 1C. These results at high temperatures confirms the suitability of the Pd/TiO2/SiO2/SiC capacitor structure for stable operation in high temperature environments. r 2006 Elsevier Ltd. All rights reserved. Keywords: Silicon carbide; High-k; Temperature; Interface
1. Introduction Silicon carbide offers great opportunities for the development of electronic devices to operate at temperatures substantially above those possible using traditional silicon based electronics. The wide bandgap, high critical breakdown field and high electron saturation velocity have made this the semiconductor of choice for high temperature operation, and devices have been demonstrated operating at temperatures beyond 600 1C. Despite the exceptional material properties of silicon carCorresponding author.
E-mail address: [email protected] (A.B. Horsfall). 1369-8001/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mssp.2006.10.032
bide, the desire to fabricate MOSFETs requires the development of high quality, reliable dielectric layers, which can function as a gate oxide. Traditional SiO2 layers have two main disadvantages for use in these conditions. The lifetime for SiO2 has been shown to be severely reduced at temperatures above 300 1C [1]. The dielectric constant of SiO2 is only 3.9, which gives an electric field in the oxide which is higher than in the silicon carbide according to Gauss’ law E ox ¼
kSiC E SiC . kox
(1)
The high critical electric field in the silicon carbide (2.5 MV cm1) would give an unacceptably high
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
electric field in the oxide (6.2 MV cm1) which would also reduce the lifetime of the oxide. The use of high permittivity dielectric materials (high k) as gate dielectrics has received a great deal of attention in silicon technology, where the increase in physical thickness, maintaining the low equivalent thickness is enabling the reduction in device dimensions required to meet Moore’s Law. Recently, various high k dielectric materials have generated a lot of interest as alternative gate dielectrics for SiC-based metal–insulator–semiconductor (MIS) device applications [2,3]. The motivation for such studies is to find a higher dielectric constant replacement for SiO2 in metal–oxide–semiconductor (MOS) capacitors prepared on SiC, in order to take advantage of the higher breakdown voltage achievable with SiC as compared to Si. Most of the studies concern themselves with the behaviour of the insulator and its effect on the related devices at or near room temperature. In this study, we report the high temperature characteristics of TiO2/SiO2 high-k dielectric stack on 4H-SiC surfaces to satisfy the development of electronics for deployment in extreme environments.
2. Experimental Commercial, research grade N-type 4H-SiC wafers from Cree Inc with a 2.9 mm thick epilayer with a nitrogen doping concentration of 2.6 1016 cm3 were used to fabricate MIS capacitors. A conventional RCA clean was performed and the wafers were then dipped into a dilute HF solution to remove the native oxide from the SiC surface prior to oxidation. Thermal oxide of 25 nm thickness was grown at 1150 1C in dry O2 ambient prior to titanium (Ti) deposition. Titanium film of 50 nm thickness was deposited on SiO2/SiC layers by the thermal evaporation with a base pressure of 5 106 Torr, followed by thermal oxidation in dry O2 ambient at 800 1C to form the 75 nm thick TiO2 layer. Subsequently, 50 nm of palladium was deposited and patterned to complete the MIS capacitors. Electrical properties of the Pd/TiO2/SiO2/SiC gate dielectric stack over a temperature range of 100–650 1C were determined by measuring highfrequency capacitance–voltage (C–V) and current–voltage (I–V) characteristics using a HP4284 LCR meter and Keithley 2400 source-measure unit in conjunction with a computer controlled hot plate.
3. Results and discussion Fig. 1 exhibits the high frequency (1 MHz) capacitance–voltage (C–V) characteristics of the Pd/TiO2/SiO2/SiC MIS capacitor at temperatures between 100 and 600 1C. Notably, there is no change of the accumulation capacitance in the temperature range studied, indicating its suitability for operation at elevated temperatures. The effective oxide thickness is found to be 17.5 nm, which is thinner than the initial SiO2 layer and this suggests a reaction between the TiO2 and SiO2 during thermal oxidation of Ti. The existence of a SiTiCO based layer in between the TiO2 and the SiC has been confirmed by X-Ray Photoelectron Spectroscopy measurements [4]. The C–V curves shift towards the left along the voltage axis at relatively higher temperatures and this may be attributed to the combined effect of temperature dependent parameters of the semiconductor, such as the shift in Fermi level and variation of charge trapping characteristics at in the interfaces. At higher temperatures (T4400 1C) a hump in the capacitance is visible in the depletion region, which suggests the existence of another set of near interface traps (NITs) with different life time and capture crosssection that do not respond to the 1 MHz frequency at low temperatures. These NITs or ‘slow states’ are located close to the conduction band edge and have a strong influence on the mobility of carriers in the inversion layer [5]. At 600 1C, the accumulation capacitance of the stack shows a small decrease, suggesting that this represents the upper operating
220 200 180 Capacitance (pF)
1134
160 140 120 100°C 200°C 300°C 400°C 500°C 600°C
100 80 60 40 20 0 -1
0
1
2
3
4
5
Gate Voltage (V) Fig. 1. High-frequency (1 MHz) capacitance–voltage characteristics of MIS capacitors on SiC at different temperatures.
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
Conductance (µS)
240 220 200 180 160 140 120 100 80 60 40 20 0
100°C 200°C 300°C 400°C 500°C 600°C
-2
-1
0
2 1 Gate Voltage (V)
3
4
5
Fig. 2. High-frequency (1 MHz) conductance–voltage characteristics at different temperatures.
1013 Density of Interface Traps (cm2 eV-1)
condition for the capacitor in air. Other work with Pd contacts to silicon carbide devices suggests that this limitation is linked to the oxidation of the Pd contact and the upper operating temperature may be increased by selecting a more oxidation resistant material, such as platinum [6]. Fig. 2 shows the corresponding the high frequency (1 MHz) conductance–voltage (G–V) characteristics of the Pd/TiO2/SiO2/SiC MIS capacitor. The data shows the existence of two distinct conductance peaks related to the interface traps, one located at approximately 1.5 V and another at 2.5 V which appears for temperatures above 400 1C. The movement of the peak at 1.5 V with temperature is consistent with the shifting of the C– V curves at higher temperatures. The second peak at 2.5 V may be attributed to ‘slow states’ and is also observed in the C– V characteristics at high temperatures, as shown in Fig. 1. This second peak is thought to be linked to the existence of another set of interface states with different activation energy and capture cross-section and that are activated at higher temperature. The existence of two different peaks also suggests that there may be discrete patches with different activation energies rather continuous distribution of interface states are present in the Pd/TiO2/SiO2/SiC MIS system. The higher value of the conductance peaks indicates higher interface state density which has been extracted in Fig. 3. From the C– V and G– V characteristics at 1 MHz, the interface state density at the interface of the dielectric stack and the silicon carbide has
1135
1012
1011 0
100 200 300 400 500 600 700 Temperature (°C)
Fig. 3. The distribution of interface state density (Dit) as a function of elevated temperatures.
been calculated using the Hill–Coleman method [7]; Dit ¼
ð2=q AÞ ðG max =wÞ , ðG max =w:C ox Þ2 þ ð1 C m =C ox Þ2
(2)
where q is the electronic charge, A is the sample area, w is the angular frequency, Cox is the oxide capacitance, Gmax is the maximum conductance in G– V plot with its corresponding capacitance (Cm). The distribution of the density of interface states (Dit) is observed in the two trends shown in Fig. 3. For temperatures below 500 1C, the density of interface states at midgap are found to be 6.0 1011 cm2 eV1, which are consistent results reported in the literature [8–10] for SiO2 and high k dielectric films on 4H silicon carbide. The density of states is insensitive to the variation of temperature over this range, which is expected from the invariance in C– V characteristics. At temperatures above 500 1C, interface state density at midgap increases, reaching 2 1012 cm2 eV1 at 650 1C. It is also noted that the second peaks which appear in the G– V curves at higher temperatures may be used to give a density of interface states, with a value of 2 1013 cm2 eV1. This is similar to the density of interface states close to the conduction band edge in the 4H silicon carbide— SiO2 system [11], the so-called ‘slow states’ [5] and we propose that these states are dominating the characteristics of the interface at high temperatures. The current versus voltage characteristics have been measured to study the breakdown field of the dielectric stack films at different temperatures. The variation of breakdown voltage as a function of temperature is shown in Fig. 4. The effective breakdown field is calculated to be 9 MV/cm at
ARTICLE IN PRESS M.H. Weng et al. / Materials Science in Semiconductor Processing 9 (2006) 1133–1136
1136
in extreme environments is presented. We show for the first time, that the use of high k dielectric films is suitable for use in temperatures up to 600 1C. However, at high temperatures, the influence of a second set of interface traps, which may be located close to the conduction band edge of the silicon carbide dominate the C– V and G– V characteristics.
Breakdown Voltage (V)
17 15 13 11 9 7 5 3
References
1 0
100
200
300
400
500
Temperature (°C) Fig. 4. Breakdown voltage of the MIS capacitor as a function of temperatures.
temperatures below 100 1C. As the temperature is increased, the breakdown voltage reduces monotonically with a strong dependence up to 300 1C and after that it is found to be almost constant at 2.2 MV cm1 when the temperature is increased to 500 1C. With the reduction in oxide quality at temperatures above 300 1C, we suggest that the low temperature breakdown voltage is determined by the electric field in the SiO2, whilst above 300 1C, the electric field in the TiO2 film defines the breakdown voltage. 4. Conclusions The temperature stability of a Pd/TiO2/SiO2/SiC dielectric stack for use in electronics for deployment
[1] Anthony CJ, Jones AJ, Uren MJ. Mater Sci Eng 1999;62:460. [2] Pe´rez-Toma´s A, Mestres N, Godignon P, Montserrat J, Milla´n J. Appl Surf Sci, in press. [3] Wolborski M, Bakowski M, Pore V, Ritala M, Leskela¨ M, Scho¨ner A, et al. Mat Sci Forum 2005;483–485:701. [4] Mahapatra R, Poolamai N, Chattopadhyay S, Wright NG, Chakraborty AK, Coleman KS, et al. Appl Phys Lett 2006;88:072910. [5] Rudenko TE, Osiyuk IN, Tyagulski IP, O´lafsson HO¨, Sveinbjo¨rnsson EO¨. Solid-State Electron 2005;49:545. [6] Hunter GW, Neudeck PG, Chen L-y, Knight D, Liu CC, Wu QH. Mat Sci Forum 1998;264–268:1093. [7] Hill WA, Coleman CC. Solid State Electron 1980; 23:987. [8] Fukuda K, Kato M, Kojima K, Senzaki J. Appl Phys Lett 2004;84:2088. [9] Gao KY, Seyller Th, Ley L, Ciobanu F, Pensl G, Tadich A, et al. Appl Phys Lett 2003;83:1830. [10] Dhar S, Song YW, Feldman LC, Isaacs-Smith T, Tin CC, Williams JR, et al. Appl Phys Lett 2004;84:498. [11] Afanas’ev VV, Ciobanu F, Pensl G, Stresmans A. In: Choyke WJ, Matsunami H, Pensl G, editors. Silicon carbide recent major advances. Berlin: Springer; 2004.