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High temperature characterization of normally-on 4H-SiC junction field-effect transistor
Superlattices and Microstructures xxx (2016) 1e5
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
High temperature characterization of normally-on 4H-SiC junction field-effect transistor Yimeng Zhang a, *, Meiyan Tang a, Qingwen Song b, Xiaoyan Tang a, Hongliang Lv a, Sicheng Liu a a
School of Microelectronics, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China b School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 28 December 2015 Received in revised form 28 March 2016 Accepted 1 April 2016 Available online xxx
SiC JFETs are considered to be the most promising high-temperature switches. In this paper, the electro-thermal simulation is conducted to investigate the performance and junction temperature of SiC normally-on JFET. The current density will degrade by more than 30% due to the self-heating effect even at room temperature. For a given device, the increase of the gate voltage can help to improve the current density. But the most efficient way to improve the high temperature performance of SiC JFETs is to optimize the structure parameters in design. When the channel width increases from 1.6 mm to 2 mm or the driftlayer width decreases from 14 mm to 7 mm at 300 K, the current handling ability can increase to double or treble even at a small bias. In this case, the junction temperature variation is less than 5 K, which will greatly reduce the device size and improve the reliability. © 2016 Elsevier Ltd. All rights reserved.
Keywords: SiC JFET high temperature self-heating junction temperature critical voltag
1. Introduction SiC material has a wider bandgap and a higher thermal conductivity comparing with Si, which makes it unparalleled in high temperature applications [1,2]. Among all the SiC devices, SiC JFETs are considered to be the most promising hightemperature switches due to high channel mobility and free of gate oxide [3,4]. In the near future, SiC power devices, especially SiC JFETs, will be widely applied in the electrical systems operated in high temperature above 300 C, such as hybrid electric vehicles. Currently, the junction temperature of commercial SiC power devices are generally less than 250 C, which is far away from the intrinsic temperature of SiC material (>800 C). The temperature inside the device will be gradually increased when SiC JFETs actually work. This so-called self-heating effect can result in the performance degradation of SiC JFETs and even lead to device thermal runaway when the junction temperature reaches a certain level. There exist two different failure mechanisms of SiC JFET [5]. One is the junction temperature rising beyond intrinsic temperature of SiC material, at which the intrinsic carrier concentration can be comparable with the doping concentration, leading to the current to increase dramatically. A positive feedback is set up and hence results in the thermal runaway. The other failure mechanism is that the temperature exceeds the temperature limit of ohmic contact
* Corresponding author. E-mail address: [email protected] (Y. Zhang). http://dx.doi.org/10.1016/j.spmi.2016.04.001 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
2
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
metal or passivation/packaging materials used to fabricate the power device, which may cause the device failure in much lower temperature [6]. In this paper, the electro-thermal simulation is conducted by using a commercial TCAD simulator. The results are discussed in detail to explain the impact of gate biases and structure parameters (channel width and the drift layer width) on the junction temperature and the current handling capability of SiC JFET.
2. Self-heating effects and junction temperature analysis The cell structure of the SiC normally-on JFET used in the simulation is shown in Fig. 1, which has a propriety trenchedand-implanted vertical channel structure. In the simulation, the electrodes for gate, source and drain are ideal ohmic contacts, and the drift layer thickness is 9.5 mm with doping concentration of 6.5 1015. The simulated results of Jds-Vds considering with and without self-heating are plotted in Fig. 2(a). The current density seriously degrades and the junction temperature rises as forward voltage (Vds) increasing comparing with the situation without self-heating. This is because the Ron increases with the elevated junction temperature due to the decrease of electron mobility. The difference △J between two Jds-Vds curves becomes bigger as Vds increasing. At Vds ¼ 19.6 V, the current degradation caused by the self-heating effect reaches to 30% and the junction temperature rises to 431.2 K, which means the performance and stability of SiC JFET are seriously degraded. An interesting phenomenon can be seen from Fig. 2(a) and (b). The current density will reach a maximum value with at a certain condition called critical condition/point here, corresponding to a critical drain-source voltage (Vds_c) of 19.6 V, a maximum current density (Jds_c) of 614.8 A/cm2 and a critical junction temperature (Tj_c) of 431.2 K. The Vds in conduction mode should not exceed Vds_c above which the current handling capability, the power consumption and the junction temperature will all degrade as well. The Tj-Vds curve in Fig. 2(a) shows that the Tj always rises with Vds increasing. If only SiC material is considered regardless of other materials, it can be predicted that the intrinsic carrier concentration of SiC JFET will reach a comparable magnitude with the doping concentration as voltage increases to a certain value. In other words, a positive feedback mentioned above happens. In this case, the conduction loss and the dissipation power can not achieve an equilibrium, finally leading to the device thermal runaway. There are two points need to be emphasized here. First, the critical point where current density reaches maximum value is not the failure point. The positive feedback does not occur near the critical point in nature, unless the critical junction temperature is close to the intrinsic temperature of SiC and causes the current density to increase. Second, this paper does not advocate the critical point for the optimum operating point, even though the device is able to achieve maximum current capability at this point [7]. The reason is that the corresponding critical voltage drop is up to 19.6 V, leading to a considerable conduction loss. Fig. 3 shows the internal temperature distribution of SiC normally-on JFET operated at critical condition. The temperature distribution in JFET is nonuniform and the highest temperature is about 431.2 K at Y ¼ 2.4 mm where the juncture of the channel region and drift region is located. It can be seen from Fig. 3 that the high temperature region (from source electrode to about Y ¼ 2.4 mm) is very close to the metal used to form the front-side ohmic contact and overlay in a real SiC JFET, which is crucial to reliable operation. Therefore, the metal materials with high thermal stability should be chosen for high junction temperature applications.
Fig. 1. Cell structure of the SiC normally-on vertical JFET.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
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Fig. 2. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET at Ta ¼ 300 K, qj-a ¼ 8 K/W and Vgs ¼ 0 V.
Fig. 3. The internal temperature distribution of the SiC normally-on JFET under conditions of Ta ¼ 300 K, qj-a ¼ 8 K/W, Vgs ¼ 0 V and Vds ¼ 19.6 V.
3. Effect of gate bias on the characteristics and junction temperature In Fig. 4(a), the Jds and Tj against Vds curves of the JFET in different gate biases (Vgs) are plotted, considering the self-heating effect. The critical points shown in Table 1 indicate that Jds_c is varied by about 24%e26% if the gate voltage of 1 V is changed, and both the Vds_c and Tj_c are reduced. The three points of A, B and C in Fig. 4(a) and (b) show that at the same current density of 450 A/cm2, the Vds are 2.1 V, 3.5 V and 12.0 V and theTj are 310.5 K, 318 K and 359 K, corresponding to the gate voltage of 1 V, 0 V and 1 V, respectively, which demonstrates that the Vds and Tj can be both decreased by increasing the gate bias. This is because the channel opening of the device is narrower at lower gate voltage. Then the on-resistance becomes larger, resulting in the increase of the drain-source voltage drop and conduction power loss at the same current density. More severe temperature rise inside the device further increases the on-resistance. That is why the Vds will be more serious if reducing the gate voltage. The results also indicate the JFET at the higher gate bias is less prone to thermal failure owing to the lower conduction loss and junction temperature. So, on the one hand, for a given device, it is effective to lower the junction temperature by increasing the gate voltage at the same current. On the other hand, as shown in Fig. 4(b), the current handling capability of the device can be improved by rising the gate voltage at the same junction temperature, so the area of the JFET can be designed more small to reduce the cost. It should be noted that JFET device is controlled by a pn junction gate. The excessive Vgs (~3 V) will make pn junction into the forward conduction, causing a large gate leakage current [8,9]. So the applied gate bias is better lower than 3 V when SiC JFET working. Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
4
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
Fig. 4. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET with Ta ¼ 300 K and qj-a ¼ 8 K/W.
Table 1 The critical values of SiC JFET with Ta ¼ 300 K and qj-a ¼ 8 K/W. Vgs/V
Jds_max/A cm2
Vds_c/K
Tj_c/K
1 0 1
763.7 614.8 486.2
14.7 19.6 31.3
422.3 431.2 467.5
4. Impact of structure parameters on performance and junction temperature The channel width, the drift layer thickness and cell-area (Wdrift L) are the key parameters in the structure design of SiC JFETs, which will directly affect the on-resistance and the current density. This paper focuses on effect of the channel width (Wch) and drift layer width (Wdrift) on the JFET performance, fixing the same doping and drift layer thickness. The cell structure of the SiC JFET is shown in Fig. 1. At the same conditions of Vgs ¼ 0 V, Ta ¼ 300 K and qj-a ¼ 8 K/W, the overall current level of the device can be improved by increasing the Wch or decreasing Wdrift. It can be seen from the critical value in Table 2, the Jds_max will increase by 350.6 A/cm2 and the Vds_c is greatly reduced if the channel width has an increment of 0.4 mm. Meanwhile, the Tj_c will be decreased by about 63 K, which is beneficial to the thermal stability of the device. While cutting down the drift layer width from 14 mm to 7 mm, the variation of Tj_c is small, but the Jds_max and the Vds_c have a great improvement. As shown in Fig. 5(a), at Vds ¼ 2 V, the current density of the device rises from 120 A/cm2 to 343 A/cm2, almost triple, when Wch is increased from 1.6 mm to 2 mm. And the current density can also increase more than double from 168 A/cm2 to 343 A/ cm2 as Wdrift reduces from 14 mm to 7 mm. The junction temperature variations in these two cases are less than 5 K. Thus in the design of the JFET, the current density can be significantly improved even at a small bias, by reasonable increase of Wch and decrease of Wdrift. Thereby the area and the cost of the device can be reduced. It should be noted that although the increase of Wch helps reduce device size and lower the power loss and the junction temperature, the threshold voltage alters significantly as well. Then it needs more negative gate voltage to turn off the device and meet the corresponding blocking voltage. Therefore, it is required to consider the different requirements and applications to find the optimal structure parameters when designing the JFET. 5. Conclusion Based on the electro-thermal simulation of the SiC JFET, the thermal stability and forward performance of the device in different gate biases, ambient temperatures, cooling conditions and structure parameters have been analyzed in detail. The Table 2 The critical values of SiC JFET with different structure parameters at Ta ¼ 300 K and Vgs ¼ 0 V. Wch/mm
Wdrift/mm
Jds_max/A cm2
Vds_c/V
Tj_c/K
2
7 14 7
614.8 363.4 264.2
19.6 33.8 66.8
431.2 437.2 494.6
1.6
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
5
Fig. 5. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET with different structure parameters at Vgs ¼ 0 V, Ta ¼ 300 K and qj-a ¼ 8 K/W.
results reveal that even at room temperature, the degradation of the current density seriously may up to 30% due to the selfheating effect. The Vds in conduction mode should not exceed the critical voltage Vds_c above which the device performances will all become worse. For a given device, the maximum current density can be improved if the gate voltage is increased, which means the performance and the reliability of SiC JFETs can be improved. A more efficient way to improve the high temperature performance of SiC JFETs is to adjust the design of structure. The current handling ability of the device can increase to double or treble even at a small bias and the junction temperature variation is less than 5 K, which greatly reduces the device size and improves the reliability of the device. Acknowledgement Authors would like to appreciate the support of National Natural Science Foundation of China (Grant No. 61372015). References [1] R. Mousa, D. Planson, et al., Modeling and high temperature characterization of SiC-JFET, in: PESC 2008, IEEE, 2008, pp. 3111e3117. [2] E. Platania, Z. Chen, F. Chimento, et al., A physics-based model for a SiC JFET accounting for electric-field-dependent mobility, IEEE Trans. Ind. Appl. 47 (2011) 199e211. [3] P. Alexandrov, J. Zhang, X. Li, et al., Demonstration of first 10 kV, 130 mU cm2 normally-off 4H-SiC trenched-and-implanted vertical junction field-effect transistor, Electron. Lett. 39 (2003) 1860e1861. [4] J.H. Zhao, P. Alexandrov, J. Zhang, et al., Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET, IEEE Electron Device Lett. 25 (2004) 474e476. [5] K. Sheng, Maximum junction temperatures of SiC power devices, IEEE Trans. Electron Devices 56 (2009) 337e342. [6] X. Li, A. Bhalla, P. Alexandrov, et al., Study of SiC vertical JFET behavior during unclamped inductive switching, in: APEC 2014, IEEE, 2014, pp. 2588e2592. [7] B. Wrzecionko, J. Biela, J.W. Kolar, SiC power semiconductors in HEVs: influence of junction temperature on power density, chip utilization and efficiency, in: IECON'09, IEEE, 2009, pp. 3834e3841. [8] Y. Li, P. Alexandrov, J.H. Zhao, 1.88-1650-V normally on 4H-SiC TI-VJFET, IEEE Trans. Electron Devices 55 (2008) 1880e1886. [9] R. Siemieniec, U. Kirchner, The 1200V direct-driven SiC JFET power switch, in: EPE 2011, IEEE, 2011, pp. 1e10.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
High temperature characterization of normally-on 4H-SiC junction field-effect transistor Yimeng Zhang a, *, Meiyan Tang a, Qingwen Song b, Xiaoyan Tang a, Hongliang Lv a, Sicheng Liu a a
School of Microelectronics, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China b School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 28 December 2015 Received in revised form 28 March 2016 Accepted 1 April 2016 Available online xxx
SiC JFETs are considered to be the most promising high-temperature switches. In this paper, the electro-thermal simulation is conducted to investigate the performance and junction temperature of SiC normally-on JFET. The current density will degrade by more than 30% due to the self-heating effect even at room temperature. For a given device, the increase of the gate voltage can help to improve the current density. But the most efficient way to improve the high temperature performance of SiC JFETs is to optimize the structure parameters in design. When the channel width increases from 1.6 mm to 2 mm or the driftlayer width decreases from 14 mm to 7 mm at 300 K, the current handling ability can increase to double or treble even at a small bias. In this case, the junction temperature variation is less than 5 K, which will greatly reduce the device size and improve the reliability. © 2016 Elsevier Ltd. All rights reserved.
Keywords: SiC JFET high temperature self-heating junction temperature critical voltag
1. Introduction SiC material has a wider bandgap and a higher thermal conductivity comparing with Si, which makes it unparalleled in high temperature applications [1,2]. Among all the SiC devices, SiC JFETs are considered to be the most promising hightemperature switches due to high channel mobility and free of gate oxide [3,4]. In the near future, SiC power devices, especially SiC JFETs, will be widely applied in the electrical systems operated in high temperature above 300 C, such as hybrid electric vehicles. Currently, the junction temperature of commercial SiC power devices are generally less than 250 C, which is far away from the intrinsic temperature of SiC material (>800 C). The temperature inside the device will be gradually increased when SiC JFETs actually work. This so-called self-heating effect can result in the performance degradation of SiC JFETs and even lead to device thermal runaway when the junction temperature reaches a certain level. There exist two different failure mechanisms of SiC JFET [5]. One is the junction temperature rising beyond intrinsic temperature of SiC material, at which the intrinsic carrier concentration can be comparable with the doping concentration, leading to the current to increase dramatically. A positive feedback is set up and hence results in the thermal runaway. The other failure mechanism is that the temperature exceeds the temperature limit of ohmic contact
* Corresponding author. E-mail address: [email protected] (Y. Zhang). http://dx.doi.org/10.1016/j.spmi.2016.04.001 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
2
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
metal or passivation/packaging materials used to fabricate the power device, which may cause the device failure in much lower temperature [6]. In this paper, the electro-thermal simulation is conducted by using a commercial TCAD simulator. The results are discussed in detail to explain the impact of gate biases and structure parameters (channel width and the drift layer width) on the junction temperature and the current handling capability of SiC JFET.
2. Self-heating effects and junction temperature analysis The cell structure of the SiC normally-on JFET used in the simulation is shown in Fig. 1, which has a propriety trenchedand-implanted vertical channel structure. In the simulation, the electrodes for gate, source and drain are ideal ohmic contacts, and the drift layer thickness is 9.5 mm with doping concentration of 6.5 1015. The simulated results of Jds-Vds considering with and without self-heating are plotted in Fig. 2(a). The current density seriously degrades and the junction temperature rises as forward voltage (Vds) increasing comparing with the situation without self-heating. This is because the Ron increases with the elevated junction temperature due to the decrease of electron mobility. The difference △J between two Jds-Vds curves becomes bigger as Vds increasing. At Vds ¼ 19.6 V, the current degradation caused by the self-heating effect reaches to 30% and the junction temperature rises to 431.2 K, which means the performance and stability of SiC JFET are seriously degraded. An interesting phenomenon can be seen from Fig. 2(a) and (b). The current density will reach a maximum value with at a certain condition called critical condition/point here, corresponding to a critical drain-source voltage (Vds_c) of 19.6 V, a maximum current density (Jds_c) of 614.8 A/cm2 and a critical junction temperature (Tj_c) of 431.2 K. The Vds in conduction mode should not exceed Vds_c above which the current handling capability, the power consumption and the junction temperature will all degrade as well. The Tj-Vds curve in Fig. 2(a) shows that the Tj always rises with Vds increasing. If only SiC material is considered regardless of other materials, it can be predicted that the intrinsic carrier concentration of SiC JFET will reach a comparable magnitude with the doping concentration as voltage increases to a certain value. In other words, a positive feedback mentioned above happens. In this case, the conduction loss and the dissipation power can not achieve an equilibrium, finally leading to the device thermal runaway. There are two points need to be emphasized here. First, the critical point where current density reaches maximum value is not the failure point. The positive feedback does not occur near the critical point in nature, unless the critical junction temperature is close to the intrinsic temperature of SiC and causes the current density to increase. Second, this paper does not advocate the critical point for the optimum operating point, even though the device is able to achieve maximum current capability at this point [7]. The reason is that the corresponding critical voltage drop is up to 19.6 V, leading to a considerable conduction loss. Fig. 3 shows the internal temperature distribution of SiC normally-on JFET operated at critical condition. The temperature distribution in JFET is nonuniform and the highest temperature is about 431.2 K at Y ¼ 2.4 mm where the juncture of the channel region and drift region is located. It can be seen from Fig. 3 that the high temperature region (from source electrode to about Y ¼ 2.4 mm) is very close to the metal used to form the front-side ohmic contact and overlay in a real SiC JFET, which is crucial to reliable operation. Therefore, the metal materials with high thermal stability should be chosen for high junction temperature applications.
Fig. 1. Cell structure of the SiC normally-on vertical JFET.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
3
Fig. 2. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET at Ta ¼ 300 K, qj-a ¼ 8 K/W and Vgs ¼ 0 V.
Fig. 3. The internal temperature distribution of the SiC normally-on JFET under conditions of Ta ¼ 300 K, qj-a ¼ 8 K/W, Vgs ¼ 0 V and Vds ¼ 19.6 V.
3. Effect of gate bias on the characteristics and junction temperature In Fig. 4(a), the Jds and Tj against Vds curves of the JFET in different gate biases (Vgs) are plotted, considering the self-heating effect. The critical points shown in Table 1 indicate that Jds_c is varied by about 24%e26% if the gate voltage of 1 V is changed, and both the Vds_c and Tj_c are reduced. The three points of A, B and C in Fig. 4(a) and (b) show that at the same current density of 450 A/cm2, the Vds are 2.1 V, 3.5 V and 12.0 V and theTj are 310.5 K, 318 K and 359 K, corresponding to the gate voltage of 1 V, 0 V and 1 V, respectively, which demonstrates that the Vds and Tj can be both decreased by increasing the gate bias. This is because the channel opening of the device is narrower at lower gate voltage. Then the on-resistance becomes larger, resulting in the increase of the drain-source voltage drop and conduction power loss at the same current density. More severe temperature rise inside the device further increases the on-resistance. That is why the Vds will be more serious if reducing the gate voltage. The results also indicate the JFET at the higher gate bias is less prone to thermal failure owing to the lower conduction loss and junction temperature. So, on the one hand, for a given device, it is effective to lower the junction temperature by increasing the gate voltage at the same current. On the other hand, as shown in Fig. 4(b), the current handling capability of the device can be improved by rising the gate voltage at the same junction temperature, so the area of the JFET can be designed more small to reduce the cost. It should be noted that JFET device is controlled by a pn junction gate. The excessive Vgs (~3 V) will make pn junction into the forward conduction, causing a large gate leakage current [8,9]. So the applied gate bias is better lower than 3 V when SiC JFET working. Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
4
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Fig. 4. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET with Ta ¼ 300 K and qj-a ¼ 8 K/W.
Table 1 The critical values of SiC JFET with Ta ¼ 300 K and qj-a ¼ 8 K/W. Vgs/V
Jds_max/A cm2
Vds_c/K
Tj_c/K
1 0 1
763.7 614.8 486.2
14.7 19.6 31.3
422.3 431.2 467.5
4. Impact of structure parameters on performance and junction temperature The channel width, the drift layer thickness and cell-area (Wdrift L) are the key parameters in the structure design of SiC JFETs, which will directly affect the on-resistance and the current density. This paper focuses on effect of the channel width (Wch) and drift layer width (Wdrift) on the JFET performance, fixing the same doping and drift layer thickness. The cell structure of the SiC JFET is shown in Fig. 1. At the same conditions of Vgs ¼ 0 V, Ta ¼ 300 K and qj-a ¼ 8 K/W, the overall current level of the device can be improved by increasing the Wch or decreasing Wdrift. It can be seen from the critical value in Table 2, the Jds_max will increase by 350.6 A/cm2 and the Vds_c is greatly reduced if the channel width has an increment of 0.4 mm. Meanwhile, the Tj_c will be decreased by about 63 K, which is beneficial to the thermal stability of the device. While cutting down the drift layer width from 14 mm to 7 mm, the variation of Tj_c is small, but the Jds_max and the Vds_c have a great improvement. As shown in Fig. 5(a), at Vds ¼ 2 V, the current density of the device rises from 120 A/cm2 to 343 A/cm2, almost triple, when Wch is increased from 1.6 mm to 2 mm. And the current density can also increase more than double from 168 A/cm2 to 343 A/ cm2 as Wdrift reduces from 14 mm to 7 mm. The junction temperature variations in these two cases are less than 5 K. Thus in the design of the JFET, the current density can be significantly improved even at a small bias, by reasonable increase of Wch and decrease of Wdrift. Thereby the area and the cost of the device can be reduced. It should be noted that although the increase of Wch helps reduce device size and lower the power loss and the junction temperature, the threshold voltage alters significantly as well. Then it needs more negative gate voltage to turn off the device and meet the corresponding blocking voltage. Therefore, it is required to consider the different requirements and applications to find the optimal structure parameters when designing the JFET. 5. Conclusion Based on the electro-thermal simulation of the SiC JFET, the thermal stability and forward performance of the device in different gate biases, ambient temperatures, cooling conditions and structure parameters have been analyzed in detail. The Table 2 The critical values of SiC JFET with different structure parameters at Ta ¼ 300 K and Vgs ¼ 0 V. Wch/mm
Wdrift/mm
Jds_max/A cm2
Vds_c/V
Tj_c/K
2
7 14 7
614.8 363.4 264.2
19.6 33.8 66.8
431.2 437.2 494.6
1.6
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001
Y. Zhang et al. / Superlattices and Microstructures xxx (2016) 1e5
5
Fig. 5. (a) The Jds-Vds curve, Tj-Vds curve and (b) the Jds-Tj curve of the normally-on SiC JFET with different structure parameters at Vgs ¼ 0 V, Ta ¼ 300 K and qj-a ¼ 8 K/W.
results reveal that even at room temperature, the degradation of the current density seriously may up to 30% due to the selfheating effect. The Vds in conduction mode should not exceed the critical voltage Vds_c above which the device performances will all become worse. For a given device, the maximum current density can be improved if the gate voltage is increased, which means the performance and the reliability of SiC JFETs can be improved. A more efficient way to improve the high temperature performance of SiC JFETs is to adjust the design of structure. The current handling ability of the device can increase to double or treble even at a small bias and the junction temperature variation is less than 5 K, which greatly reduces the device size and improves the reliability of the device. Acknowledgement Authors would like to appreciate the support of National Natural Science Foundation of China (Grant No. 61372015). References [1] R. Mousa, D. Planson, et al., Modeling and high temperature characterization of SiC-JFET, in: PESC 2008, IEEE, 2008, pp. 3111e3117. [2] E. Platania, Z. Chen, F. Chimento, et al., A physics-based model for a SiC JFET accounting for electric-field-dependent mobility, IEEE Trans. Ind. Appl. 47 (2011) 199e211. [3] P. Alexandrov, J. Zhang, X. Li, et al., Demonstration of first 10 kV, 130 mU cm2 normally-off 4H-SiC trenched-and-implanted vertical junction field-effect transistor, Electron. Lett. 39 (2003) 1860e1861. [4] J.H. Zhao, P. Alexandrov, J. Zhang, et al., Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET, IEEE Electron Device Lett. 25 (2004) 474e476. [5] K. Sheng, Maximum junction temperatures of SiC power devices, IEEE Trans. Electron Devices 56 (2009) 337e342. [6] X. Li, A. Bhalla, P. Alexandrov, et al., Study of SiC vertical JFET behavior during unclamped inductive switching, in: APEC 2014, IEEE, 2014, pp. 2588e2592. [7] B. Wrzecionko, J. Biela, J.W. Kolar, SiC power semiconductors in HEVs: influence of junction temperature on power density, chip utilization and efficiency, in: IECON'09, IEEE, 2009, pp. 3834e3841. [8] Y. Li, P. Alexandrov, J.H. Zhao, 1.88-1650-V normally on 4H-SiC TI-VJFET, IEEE Trans. Electron Devices 55 (2008) 1880e1886. [9] R. Siemieniec, U. Kirchner, The 1200V direct-driven SiC JFET power switch, in: EPE 2011, IEEE, 2011, pp. 1e10.
Please cite this article in press as: Y. Zhang et al., High temperature characterization of normally-on 4H-SiC junction field-effect transistor, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.04.001