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Drain-source capacity of junction field effect transistor
Solid-Stare
Elecrronic~,
1972, Vol. 15, pp. 325-327.
Pergamon Press.
Printed
inGreatBritain
DRAIN-SOURCE CAPACITY OF JUNCTION FIELD EFFECT TRANSISTOR M. MISRA and H. C. PRASAD Department of Physics, University of Gorakhpur, Gorakhpur, U.P., India (Keceived
15 March
197
I ; in revisedform
9 August
197
1)
Using the two region physical model due to Grebene and Ghandi and also by taking into account the effect of carrier drift velocity saturation, a physical theory of drain-source capacitance of JFET has been developed. The theoretical analysis leads to the following relation for CdS, Abstract-
z=ln
(57/&a)+In (V,,+V,,-V,)
INTRODUCTION drain-source capacity is an important parameter in the electrical characteristics[l] of JFETs. This capacity (i.e. C,) arises due to charges between drain and source when the channel is completely depleted and differs from the usual p-n junction capacitances. As yet there exists no physical theory for the Cds. The present paper, therefore, is intended to develop an adequate physical theory for Cdn by taking into consideration two region physical model of JFET due to Grebene and Ghandi[2] and also by taking into account the carrier drift velocity saturation effect [3,4]. A simple relation has been developed in terms of I’,,, and electric field (E,,) existing between the channel. Experimental results show a good conformity with the proposed physical theory and they provide an indirect method for evaluation of EW THE
PHYSICAL MODEL OF J FET The theoretical analysis, undertaken here to analyse the characteristics, takes into consideration a p-channel FET structure with parallel gate regions and abrupt-abrupt [5] impurity profile for channel to gate junctions. It is assumed that gate regions are heavily doped so that the gate channel space-charge layer spreads predominantly into the channel. The characteristics of the FET are analysed by treating the device channel as made up of only one region for the pre-pinched mode operation and of two separate regions namely, the gradual channel region from the source electrode to the pinch-off point (Region I) and the depleted region from the pinch-off point to the drain elec-
trode (Region 11) along the channel for pinch-off mode operation. Figures l(a) and (b) show the schematic diagram of the channel depletion layer for p-channel FET in pre-pinch mode and in pinchmode operation respectively. The physical and structural parameters and the two regions (Region I and Region II) are also defined in Fig. l(b). Region I can be very well approximated in terms of the gradual channel model [5.6]. Therefore, the depletion layer profile, in this region, can be obtained by solving the one dimensional Poisson’s equation based on the gradual channel approximation[S-71. But in Region II the gradual channel approximation fails to explain the properties of field effect devices in pinch-off mode and therefore the two dimensional Poisson’s equation[2,8] has to be solved to find out the behaviour of depleted region near the drain and the effect of carrier drift velocity saturation[3,4] being a dominant factor in determining the dimension of Region II, has also to be taken into consideration. It is apparent from the Fig. l(b) that the drain-gate region of the channel is almost completely depleted beyond the pinch-off and as such it introduces a capacity (C,) between the drain and source. THEORETICAL ANALYSIS In the prepinch-off region, the channel of JFET behaves essentially .as a resistor. But where as, beyond the pinch-off the drain-gate region of the channel is almost completely depleted and as such it introduces a capacity (C,,) between the drain and source. In view of the physical model presented in the Fig. l(b), the capacitative behaviour of 325
M. MISRA and H. C. PRASAD
326
_ 1 _ sI
Gate
4 Depleted L* (region-
L 2
Gradual
channel II
)
YY
GS
channel
Fig. 2. Lumped model of JFET in pinch-off region. sistivity of the geometrical and JFET, given in be readily shown of 50 kfi. Thus, beyond pinch-off mation.
-p-channel
(b)
Pinch-off
region
Depleted
channel
Gate Gradual
channel
channel respectively. Using the physical parameters[2] of the Table 1, from equation (1) it can that R,,, is roughly of the order the lumped model of the channel condition is a fairly good approxi-
Table 1. Assumed values of geometrical and physical parameters appropriate to symmetrical silicon p-channel JFET Parameters
(a)
Pre
pinch-off
Fig. 1. Schematic
junction
field
the channel, which might be due to the Region II, can be represented in terms of the lumped parameters as shown in Fig. 2. In Fig. 2, RCL,, RrL2, Cd8 and C& represent the resistance of the channel in Region I, the resistance of thin residual channel in Region II (arising due to the carrier drift velocity saturation), the capacity between the source and drain and parasitic shunt capacitance respectively. Physically R,.,,, can be thought as leakage resistance associated with the capacitor Cd,%. The resistance of the residual channel (RCLI) can be obtained from the relation, R
,I&
r’2 where,
(1)
26,
St and p are residual
thickness[2]
and re-
Unit
3.0 x 10’” cm-” 6.0 x 10” cm. set’ kV/cm 30.0 V 2.0 25.0 km 4.5 km 1.2 pm
region
diagram of p-channel effect transistor.
Value
In order to obtain an expression for the drainsource capacity (C,,), an accurate determination of depleted region width (L,), as shown in Fig. 1(b), is required. The depleted region width can be obtained if the potential distribution in Region 11 is determined. This can be achieved by solving the two dimensional Poisson’s equation with appropriate boundary conditions which leads to the following expression [2] for L,, L2 = z
. sinh-r (xVd,,/2a&,)
where, I/,,= Vds+ I’,$-- V,, (V, Since, the total cross-sectional region is 2aZ cm”, therefore, tween drain to source, arising
(2)
is pinch-off voltage). area of the depleted the capacitance bedue to the depleted
DRAIN-SOURCE
CAPACITY
layer of width LB, will be given by the relation, Cds =
E
.2aZ/L,
?WZ = sinh-’ (rrV&a&,)
.
(3)
By expending the hyperbolic function and retaining only one term of the expansion (because other terms except first term are negligibly small since rVdp/2aEo is of the order of 5 or more) one gets, (4) or F
ds
= In ( rr/aEO) + In V,,
(5)
Equation (5) shows that the reciprocal of the channel capacitance varies linearly with log of the drain-source or gate-source voltage. RESULTS AND DISCUSSIONS The measurement of Cd8 has been done by resonance method[9] at the frequency 200 kclsec using Muirhead variable air condenser type A-41 1-B having an accuracy of 0.26pF. Since JFET is built in a wrap around structure, hence it has an appreciable parasitic shunt capacitance. An exact value of CdS was then obtained by subtracting the parasitic shunt capacitance (which is of the order of 1.0 pF). Data obtained experimentally on silicon p-channel JFET 2N2386 : 5239 has been indicated in Fig. 3 as l/Cd, vs. log,, V,, plot at V,, = 2V.
OF
327
JFET
It is clear from the plot that l/Cd, vs. log,, V,,, is linear. This linearity of plot clearly demonstrates the validity of relation (5). In order to check the physical model, as described for Cm, it was decided to compare the experimentally evaluated values of Z and E, with that obtained by other method[2]. From the slope of the plot the value of Z was found to be of the order of 0.69 cm which is in good agreement with the theoretical value. Using this value and the design data appropriate to silicon p-channel JFET (shown in Table 1) the value of E,, evaluated from the intercept of the plot on l/Cd, axis, comes to be of the order of 32.9 kV/cm. This value of E, is comparable to the value 30.0 kV/cm, obtained from the dynamic drain resistance measurement method by Grebene and Ghandhi. Thus the two region physical model of JFET, proposed by Grebene and Ghandhi, provides not only correct explanation of Z-V characteristics of JFET in saturation region but also provides a physical basis for the interpretation of the nature of c*.
authors are thankful to Prof. D. Sharma for providing laboratory facilities. They are also grateful to Dr. S. Chandra and Sri K. Tripathi for useful discussions. One of them, H. C. Prasad, is thankful to the Council of Scientific and Industrial Research (India), New Delhi for the award of a Senior Research Fellowship.
Acknowledgements-The
REFERENCES 1. B. Down, Electronics, 55, 14 (1964). 2. A. B. Grebene and S. K. Ghandhi, Solid-St. Electron.
12,573 (1969). 3. J. Grosvalet et al., Solid-St. Electron. 6,65 (1963). 4. L. J. Sevin Jr., FieldEflect Transisror, p. 65, McGrawHill, New York (1965). 5. W. Shockley, Proc. Instn. Radio Engrs. 40, 1365
(1952).
Fig.
3. Drain-source voltage dependence channel silicon JFET type 2N2386:
of Cda of p5239.
6. G. C. Dacey and I. M. Ross, Bell. SW. tech. J. 34. 1149 (1955) 7. S. M. Sze, Physics of Semiconductor Devices, p. 345, John Wiley, New York (1969). 8. S. Y. Wu and C. T. Sah, Solid-St. Electron. 10, 593 (1967). 9. F. J. Biondi (Editor), Transistor Technology, Vol. III, p. 356. Van Nostrand, New York (1958).
Elecrronic~,
1972, Vol. 15, pp. 325-327.
Pergamon Press.
Printed
inGreatBritain
DRAIN-SOURCE CAPACITY OF JUNCTION FIELD EFFECT TRANSISTOR M. MISRA and H. C. PRASAD Department of Physics, University of Gorakhpur, Gorakhpur, U.P., India (Keceived
15 March
197
I ; in revisedform
9 August
197
1)
Using the two region physical model due to Grebene and Ghandi and also by taking into account the effect of carrier drift velocity saturation, a physical theory of drain-source capacitance of JFET has been developed. The theoretical analysis leads to the following relation for CdS, Abstract-
z=ln
(57/&a)+In (V,,+V,,-V,)
INTRODUCTION drain-source capacity is an important parameter in the electrical characteristics[l] of JFETs. This capacity (i.e. C,) arises due to charges between drain and source when the channel is completely depleted and differs from the usual p-n junction capacitances. As yet there exists no physical theory for the Cds. The present paper, therefore, is intended to develop an adequate physical theory for Cdn by taking into consideration two region physical model of JFET due to Grebene and Ghandi[2] and also by taking into account the carrier drift velocity saturation effect [3,4]. A simple relation has been developed in terms of I’,,, and electric field (E,,) existing between the channel. Experimental results show a good conformity with the proposed physical theory and they provide an indirect method for evaluation of EW THE
PHYSICAL MODEL OF J FET The theoretical analysis, undertaken here to analyse the characteristics, takes into consideration a p-channel FET structure with parallel gate regions and abrupt-abrupt [5] impurity profile for channel to gate junctions. It is assumed that gate regions are heavily doped so that the gate channel space-charge layer spreads predominantly into the channel. The characteristics of the FET are analysed by treating the device channel as made up of only one region for the pre-pinched mode operation and of two separate regions namely, the gradual channel region from the source electrode to the pinch-off point (Region I) and the depleted region from the pinch-off point to the drain elec-
trode (Region 11) along the channel for pinch-off mode operation. Figures l(a) and (b) show the schematic diagram of the channel depletion layer for p-channel FET in pre-pinch mode and in pinchmode operation respectively. The physical and structural parameters and the two regions (Region I and Region II) are also defined in Fig. l(b). Region I can be very well approximated in terms of the gradual channel model [5.6]. Therefore, the depletion layer profile, in this region, can be obtained by solving the one dimensional Poisson’s equation based on the gradual channel approximation[S-71. But in Region II the gradual channel approximation fails to explain the properties of field effect devices in pinch-off mode and therefore the two dimensional Poisson’s equation[2,8] has to be solved to find out the behaviour of depleted region near the drain and the effect of carrier drift velocity saturation[3,4] being a dominant factor in determining the dimension of Region II, has also to be taken into consideration. It is apparent from the Fig. l(b) that the drain-gate region of the channel is almost completely depleted beyond the pinch-off and as such it introduces a capacity (C,) between the drain and source. THEORETICAL ANALYSIS In the prepinch-off region, the channel of JFET behaves essentially .as a resistor. But where as, beyond the pinch-off the drain-gate region of the channel is almost completely depleted and as such it introduces a capacity (C,,) between the drain and source. In view of the physical model presented in the Fig. l(b), the capacitative behaviour of 325
M. MISRA and H. C. PRASAD
326
_ 1 _ sI
Gate
4 Depleted L* (region-
L 2
Gradual
channel II
)
YY
GS
channel
Fig. 2. Lumped model of JFET in pinch-off region. sistivity of the geometrical and JFET, given in be readily shown of 50 kfi. Thus, beyond pinch-off mation.
-p-channel
(b)
Pinch-off
region
Depleted
channel
Gate Gradual
channel
channel respectively. Using the physical parameters[2] of the Table 1, from equation (1) it can that R,,, is roughly of the order the lumped model of the channel condition is a fairly good approxi-
Table 1. Assumed values of geometrical and physical parameters appropriate to symmetrical silicon p-channel JFET Parameters
(a)
Pre
pinch-off
Fig. 1. Schematic
junction
field
the channel, which might be due to the Region II, can be represented in terms of the lumped parameters as shown in Fig. 2. In Fig. 2, RCL,, RrL2, Cd8 and C& represent the resistance of the channel in Region I, the resistance of thin residual channel in Region II (arising due to the carrier drift velocity saturation), the capacity between the source and drain and parasitic shunt capacitance respectively. Physically R,.,,, can be thought as leakage resistance associated with the capacitor Cd,%. The resistance of the residual channel (RCLI) can be obtained from the relation, R
,I&
r’2 where,
(1)
26,
St and p are residual
thickness[2]
and re-
Unit
3.0 x 10’” cm-” 6.0 x 10” cm. set’ kV/cm 30.0 V 2.0 25.0 km 4.5 km 1.2 pm
region
diagram of p-channel effect transistor.
Value
In order to obtain an expression for the drainsource capacity (C,,), an accurate determination of depleted region width (L,), as shown in Fig. 1(b), is required. The depleted region width can be obtained if the potential distribution in Region 11 is determined. This can be achieved by solving the two dimensional Poisson’s equation with appropriate boundary conditions which leads to the following expression [2] for L,, L2 = z
. sinh-r (xVd,,/2a&,)
where, I/,,= Vds+ I’,$-- V,, (V, Since, the total cross-sectional region is 2aZ cm”, therefore, tween drain to source, arising
(2)
is pinch-off voltage). area of the depleted the capacitance bedue to the depleted
DRAIN-SOURCE
CAPACITY
layer of width LB, will be given by the relation, Cds =
E
.2aZ/L,
?WZ = sinh-’ (rrV&a&,)
.
(3)
By expending the hyperbolic function and retaining only one term of the expansion (because other terms except first term are negligibly small since rVdp/2aEo is of the order of 5 or more) one gets, (4) or F
ds
= In ( rr/aEO) + In V,,
(5)
Equation (5) shows that the reciprocal of the channel capacitance varies linearly with log of the drain-source or gate-source voltage. RESULTS AND DISCUSSIONS The measurement of Cd8 has been done by resonance method[9] at the frequency 200 kclsec using Muirhead variable air condenser type A-41 1-B having an accuracy of 0.26pF. Since JFET is built in a wrap around structure, hence it has an appreciable parasitic shunt capacitance. An exact value of CdS was then obtained by subtracting the parasitic shunt capacitance (which is of the order of 1.0 pF). Data obtained experimentally on silicon p-channel JFET 2N2386 : 5239 has been indicated in Fig. 3 as l/Cd, vs. log,, V,, plot at V,, = 2V.
OF
327
JFET
It is clear from the plot that l/Cd, vs. log,, V,,, is linear. This linearity of plot clearly demonstrates the validity of relation (5). In order to check the physical model, as described for Cm, it was decided to compare the experimentally evaluated values of Z and E, with that obtained by other method[2]. From the slope of the plot the value of Z was found to be of the order of 0.69 cm which is in good agreement with the theoretical value. Using this value and the design data appropriate to silicon p-channel JFET (shown in Table 1) the value of E,, evaluated from the intercept of the plot on l/Cd, axis, comes to be of the order of 32.9 kV/cm. This value of E, is comparable to the value 30.0 kV/cm, obtained from the dynamic drain resistance measurement method by Grebene and Ghandhi. Thus the two region physical model of JFET, proposed by Grebene and Ghandhi, provides not only correct explanation of Z-V characteristics of JFET in saturation region but also provides a physical basis for the interpretation of the nature of c*.
authors are thankful to Prof. D. Sharma for providing laboratory facilities. They are also grateful to Dr. S. Chandra and Sri K. Tripathi for useful discussions. One of them, H. C. Prasad, is thankful to the Council of Scientific and Industrial Research (India), New Delhi for the award of a Senior Research Fellowship.
Acknowledgements-The
REFERENCES 1. B. Down, Electronics, 55, 14 (1964). 2. A. B. Grebene and S. K. Ghandhi, Solid-St. Electron.
12,573 (1969). 3. J. Grosvalet et al., Solid-St. Electron. 6,65 (1963). 4. L. J. Sevin Jr., FieldEflect Transisror, p. 65, McGrawHill, New York (1965). 5. W. Shockley, Proc. Instn. Radio Engrs. 40, 1365
(1952).
Fig.
3. Drain-source voltage dependence channel silicon JFET type 2N2386:
of Cda of p5239.
6. G. C. Dacey and I. M. Ross, Bell. SW. tech. J. 34. 1149 (1955) 7. S. M. Sze, Physics of Semiconductor Devices, p. 345, John Wiley, New York (1969). 8. S. Y. Wu and C. T. Sah, Solid-St. Electron. 10, 593 (1967). 9. F. J. Biondi (Editor), Transistor Technology, Vol. III, p. 356. Van Nostrand, New York (1958).