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A new hot-carrier induced degradation mode under low gate and drain bias stresses in n-channel MOSFETs
Microelectronic Engineering 22 (1993) 289-292 Elsevier
289
A New Hot-Carrier Induced Degradation Bias Stresses in N-channel MOSFETs
Mode under Low Gate and Drain
Masakazu Shimaya, Shigeo Ogawa, and Noboru Shiono LSI Laboratories, Nippon Telegraph and Telephone Corporation Morinosato Wakamiya 3-1, Atsugi, Kanagawa, Japan Experimental evidence is presented for an enhanced hot-carrier induced degradation mode in submicron n-channel MOSFETs. Its feature is that remarkable lifetime shortening occurs at a gate bias of near threshold voltage and at drain biases lower than 5 V, rather than at the gate bias of maximum substrate current condition. Significant interface trap generation without apparent hole trapping is found to be responsible for degradation enhancement under these bias conditions. 1. INTRODUCTION Hot-carrier induced degradation of MOSFETs is still a significant reliability constraint for scaled CMOS devices. It is well known that maximum degradation occurs at a bias stress that corresponds to the peak substrate current condition for n-channel MOSFETs[l]. Under this stress condition, it is considered that the origin of degradation is the interface trap generation near the drain edge for a conventional single drain MOSFET[2]. It is also suggested that the transconductance (gm) degradation caused by the electron trapping in the side wall oxide is the main degradation mode for LDD MOSFET[3]. These results were mainly obtained by the acceleration test where drain biases were above 5 V. Recently, submicron MOSFETs for 3.3 V operation have been developed to reduce the power dissipation and hot-carrier effects. It is not clear whether the above mentioned degradation characteristics occur in these devices. We found that maximum degradation occurs at a gate bias near threshold voltage and at a lower drain bias in submicron n-channel MOSFETs for 3.3 V operation. This paper presents experimental evidence for this newly observed degradation mode through stress tests with various biases, and discusses a mechanism for degradation enhancement using charge pumping measurements. 2. EXPERIMENTAL We used N-channel MOSFETs with a conventional single drain and an LDD ( lightly doped drain ) structure. Samples were fabricated by 0.8 pm and 0.5 urn CMOS technologies. Table 1 shows typical MOSFET structure parameters. The MOSFETs were stressed at various Table 1 Typical MOSFET structure parameters
Drain structure Gate oxide thickness, Tox Channel length Channel width, Practical power supply voltage
(nm) Lp @m) Wp (pm)
0167-9317/93/$06.00
(V)
Sample A
Sample B
Single
Single
LDD
LDD
15 0.7-0.8 16
0.:-10.8 51
0.71-0.8 51
O.ZO.6 20
3.3
3.3
5.0
3.3
Sample C
Sample D
0 1993 - Elsevier Science Publishers B.V. All rights reserved.
M. Shimaya et al. I Stresses in n-channel MOSFET’s
290
DC biases at room temperature, where the drain voltage was varied under a constant gate bias. Two gate bias conditions ( a hole injection bias of VG = Vr + 0.41/and a maximum substrate (ZSUS_~) current condition of VG = I%/3 - Vo/2 ) were mainly selected. Device degradation was evaluated by monitoring the VT shift and the maximum gm change measured at a drain voltage of 0.1 V. Interface trap generation was evaluated by charge pumping measurements [4]. The amplitude of the gate pulse was 4 V, the pulse period was 3 pet, and the rising and falling times were 100 nsec.
3. RESULTS AND DISCUSSION 3.1. Degradation mode under low gate and low drain bias We observed that maximum degradation occurs below the gate bias of the I~u,z-~~ condition under a drain bias of less than 5 V in n-channel MOSFETs for 3.3 V operation. Figure 1 shows Vr shifts at different stress gate voltage for sample D. It is clearly shown 20 Sample D that the maximum VT shift occurs below the gate bias of the IsUB_marcondition. Moreover, Vo = 5.0 V. 200 min. gate voltage for peak degradation shifts 15 towards low bias when the stress drain voltage decreases. Figure 2(a) shows the ; lifetime, defined as the time to reach a 10 mV 5 VT shift, as a function of the normalized g losubstrate current at a gate bias of VT t 0.4 V 5 and at a gate bias for the Isu~-,,,~ condition. i Significant lifetime reduction was observed at 5a gate bias of VT + 0.4 V for the 3.3 V devices (A, B and D), while not for the 5 V device (C). The difference between the lifetime at a gate bias of VT t 0.4 V and that at the IsuB_~~ condition becomes larger as the 0 1 2 3 4 5 substrate current decreases. This means that k W) degradation enhancement becomes significant Fig. 1 VT shifts and IsdWp as a function of at a lower drain bias stress. Similar results stress gate voltage for sample D. were also observed for gm degradation, as shown in Fig.2(b). I
lo5
.
“..‘I
.
4
lo4 IS z
. ‘,““I
lo*
“.‘.I
VT Shift 10 mV
,
I
gm degradation
I
10 %
lo4 r
:ond.i
B Id
lo3 :
lo2 r
lo2 7
E ;
._ cl 10’
10’ ;
v,= VT+ 0.4 v
;
k’
VG=VT+0.4V
1000 1
10
Isub/Wp (PA/pm) (a) VT shift Fig. 2
Relationship between device lifetime condition and ‘vG= VT + 0.4 V.
&biWp
(PA/pm)
(b) gm degradation and IsmwP for the maximum Is~
291
M. Shimaya et al. I Stresses in n-channel MOSFLT’s
3.2. Interface trap generation
Figure 3 shows the increase in charge pumping current (AZcp) for sample A, measured at a stress time that coincides with the lifetime of V-r shift for this sample. At VG = Vr + 0.4 P’, the rising edge of the AZcpcurve shifts toward the negative pulse base voltage VLe. Similar results were also obtained for other 3.3 V devices (B and D). This shift indicates that positive charges are created by hole trapping in the gate oxide [5]. The negative VLe shift becomes smaller as the drain bias decreases. This suggests that hole trapping in the oxide is reduced and that only interface traps are generated with decreasing drain bias. Trapped holes have been known to compensate for the influence of interface traps on VT shift[5]. We also found that the interface traps increase more rapidly at a Vr + 0.4 I’bias than bias. Therefore, interface trap at a ZSCJEJ-~~~ generation without apparent hole trapping at a Vr t 0.4 T/bias and a low drain bias is responsible for degradation enhancement.
5
.
I
Sample
A
I
’
0 v,
’
= v,
+ Isub-max
-6
-5
-4
-3 -2 Vbase (V)
I
+ 0.4 v cond.
-1
0
Fig. 3 hlcp
characteristics as a function of stress drain voltage after stress test, where the VTshift reaches 10 mV.
3.3. Evidence for the simultaneous iqjection of hot-hole and hot-electron A step stress test, where the drain bias was changed from 5.5 V to 4.6 V at a constant gate bias of Vr t 0.4 V, was performed. Figure 4 shows the AIcp change during the step DC stress test for Sample A. A negative Vbase shift, which was generated during the first step stress, decreased during the second step. This proves that the trapped hole was eliminated during low drain stress. This elimination can be attributed to neutralization caused by the electron injection that occurs during low drain stress. This is because hole detrapping was not observed during gate bias only or drain bias only stress. Figure 5 shows AZcp lifetime plots as a function of ZS&ZD. AIcp lifetime is defined as the stress time at which the AIcp increases to about 2~10-~’ A/pm. Two types of linear curves with different slope can be recognized. A slope of -5.5 is derived at Vc = Vr t 0.4 V, and a slope of -3.0 for the ZS~B_~~condition. These values suggest that hot-hole injection and hot-electron injection are responsible for 1oy
-6
-5
-4
-3 Vbase (V)
-2
Fig. 4 Change of AIcp characteristics
stress test at VG = VT + 0.4 v.
-1
0
“..I
.
Icp-max
. ‘.“‘I
change
20 PA/pm
.
‘j
0.10
0.01 lsubtld
after a step
Fig. 5 Zcp lifetime plots as a function of &.&ID for the ISVS_- condition and VG = VT t 0.4 V.
292
M. Shimaya et al. I Stresses in n-channel MOSFE?“.~
interface trap generation, respectively[5][6][7]. These slopes remain constant, regardless of the I,us/ID value which changes with stress drain bias. This suggests that hot-holes are still injected into the gate oxide at low drain bias, while hole-trapping in the gate oxide is reduced with a decrease in drain voltage, as shown in Fig.4. As a result, it can be supposed that hot-holes and hot-electrons are injected together into the channel region near the drain edge under a stress of VC = Vr + 0.4 vwith low drain voltage. Gate Electrode
3.4. Model for the simultaneous injection Enhanced degradation was observed when hot-holes were injected into the gate oxide followed by hotelectrons injections (5][8]. The degradation mode shown in our work also seems to be attributed to this effect. In our case, hot-hole and hot-electron are injected together at low gate and low drain bias. Figure 6 shows a model of simultaneous injection. At high drain voltage, since the direction of the vertical electrical field is towards the substrate, only hot-hole injection occurs at the channel region near the drain edge. With decreasing drain voltage, the vertical field direction changes towards the gate electrode at the drain edge and the position of the hole injection shifts into the drain region. On the other hand, the probability of electron injection increases. As a result, hot-electrons and hot-holes are injected together at the same region near the drain edge. 4. SUMMARY
1
H”‘” In]ecllon Gate Orlde
NP-S”bStralt?
“-
(a)High
N+ Drain
Dram Ems
Gate Electrode
1
Fig. 6 Schematic diagram of hot-hole and hot-electron injection region.
A new hot-carrier degradation mode has been observed under stress conditions of low gate and low drain voltage, where the lifetime of device degradation is significantly shortened. This new mode can be attributed to a generation of interface traps without positive charges caused by a simultaneous injection of hot-holes and hot-electrons. Therefore, device lifetimes of submicron devices for use in 3.3 V operation should be determined from the stress test at a gate bias of near threshold and at a drain bias lower than 5 V, instead of conventional ISLIB-~~bias stress tests. ACKNOWLEDGMENT The authors would like to thank Dr. A. Iwata for his continuous encouragement throughout this work. They also would like to thank the project team 4 for their sample preparation. REFERENCES Takeda, N. Suzuki, and T. Hagiwara, IEDM Tech. Dig., 1983. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, IEEE Trans. Electron [;IE.B.Devices, vol. 37, p.744, 1990. F.-C. Hus and H. R. Grinolds, IEEE Electron Device Letters, vol. EDL-5, p.71, 1984. Groeseneken, H. E. Maes, N. Beltran, and R. F. DeKeersmaecker, IEEE Trans. [i]G.Electron Devices, vol. 31, p.42, 1984. [51 P. Heremans,
R. Bellens, G. Groeseneken, and H. E. Maes, IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988. [61P. Heremans, G. Bosch, R. Bellens, G. Groeseneken, H. E. Maes, IEEE Trans. Electron Devices, ~01.37, p.980, 1990. [71 C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, IEEE Trans. Electron Devices, vol. 32, p.375, 1985. PI B. S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benecchi, A. Bravis, K. R. Mistry, and A. Boudou, IEEE Trans. Electron Devices, vol. 37, p. 1869, 1990.
289
A New Hot-Carrier Induced Degradation Bias Stresses in N-channel MOSFETs
Mode under Low Gate and Drain
Masakazu Shimaya, Shigeo Ogawa, and Noboru Shiono LSI Laboratories, Nippon Telegraph and Telephone Corporation Morinosato Wakamiya 3-1, Atsugi, Kanagawa, Japan Experimental evidence is presented for an enhanced hot-carrier induced degradation mode in submicron n-channel MOSFETs. Its feature is that remarkable lifetime shortening occurs at a gate bias of near threshold voltage and at drain biases lower than 5 V, rather than at the gate bias of maximum substrate current condition. Significant interface trap generation without apparent hole trapping is found to be responsible for degradation enhancement under these bias conditions. 1. INTRODUCTION Hot-carrier induced degradation of MOSFETs is still a significant reliability constraint for scaled CMOS devices. It is well known that maximum degradation occurs at a bias stress that corresponds to the peak substrate current condition for n-channel MOSFETs[l]. Under this stress condition, it is considered that the origin of degradation is the interface trap generation near the drain edge for a conventional single drain MOSFET[2]. It is also suggested that the transconductance (gm) degradation caused by the electron trapping in the side wall oxide is the main degradation mode for LDD MOSFET[3]. These results were mainly obtained by the acceleration test where drain biases were above 5 V. Recently, submicron MOSFETs for 3.3 V operation have been developed to reduce the power dissipation and hot-carrier effects. It is not clear whether the above mentioned degradation characteristics occur in these devices. We found that maximum degradation occurs at a gate bias near threshold voltage and at a lower drain bias in submicron n-channel MOSFETs for 3.3 V operation. This paper presents experimental evidence for this newly observed degradation mode through stress tests with various biases, and discusses a mechanism for degradation enhancement using charge pumping measurements. 2. EXPERIMENTAL We used N-channel MOSFETs with a conventional single drain and an LDD ( lightly doped drain ) structure. Samples were fabricated by 0.8 pm and 0.5 urn CMOS technologies. Table 1 shows typical MOSFET structure parameters. The MOSFETs were stressed at various Table 1 Typical MOSFET structure parameters
Drain structure Gate oxide thickness, Tox Channel length Channel width, Practical power supply voltage
(nm) Lp @m) Wp (pm)
0167-9317/93/$06.00
(V)
Sample A
Sample B
Single
Single
LDD
LDD
15 0.7-0.8 16
0.:-10.8 51
0.71-0.8 51
O.ZO.6 20
3.3
3.3
5.0
3.3
Sample C
Sample D
0 1993 - Elsevier Science Publishers B.V. All rights reserved.
M. Shimaya et al. I Stresses in n-channel MOSFET’s
290
DC biases at room temperature, where the drain voltage was varied under a constant gate bias. Two gate bias conditions ( a hole injection bias of VG = Vr + 0.41/and a maximum substrate (ZSUS_~) current condition of VG = I%/3 - Vo/2 ) were mainly selected. Device degradation was evaluated by monitoring the VT shift and the maximum gm change measured at a drain voltage of 0.1 V. Interface trap generation was evaluated by charge pumping measurements [4]. The amplitude of the gate pulse was 4 V, the pulse period was 3 pet, and the rising and falling times were 100 nsec.
3. RESULTS AND DISCUSSION 3.1. Degradation mode under low gate and low drain bias We observed that maximum degradation occurs below the gate bias of the I~u,z-~~ condition under a drain bias of less than 5 V in n-channel MOSFETs for 3.3 V operation. Figure 1 shows Vr shifts at different stress gate voltage for sample D. It is clearly shown 20 Sample D that the maximum VT shift occurs below the gate bias of the IsUB_marcondition. Moreover, Vo = 5.0 V. 200 min. gate voltage for peak degradation shifts 15 towards low bias when the stress drain voltage decreases. Figure 2(a) shows the ; lifetime, defined as the time to reach a 10 mV 5 VT shift, as a function of the normalized g losubstrate current at a gate bias of VT t 0.4 V 5 and at a gate bias for the Isu~-,,,~ condition. i Significant lifetime reduction was observed at 5a gate bias of VT + 0.4 V for the 3.3 V devices (A, B and D), while not for the 5 V device (C). The difference between the lifetime at a gate bias of VT t 0.4 V and that at the IsuB_~~ condition becomes larger as the 0 1 2 3 4 5 substrate current decreases. This means that k W) degradation enhancement becomes significant Fig. 1 VT shifts and IsdWp as a function of at a lower drain bias stress. Similar results stress gate voltage for sample D. were also observed for gm degradation, as shown in Fig.2(b). I
lo5
.
“..‘I
.
4
lo4 IS z
. ‘,““I
lo*
“.‘.I
VT Shift 10 mV
,
I
gm degradation
I
10 %
lo4 r
:ond.i
B Id
lo3 :
lo2 r
lo2 7
E ;
._ cl 10’
10’ ;
v,= VT+ 0.4 v
;
k’
VG=VT+0.4V
1000 1
10
Isub/Wp (PA/pm) (a) VT shift Fig. 2
Relationship between device lifetime condition and ‘vG= VT + 0.4 V.
&biWp
(PA/pm)
(b) gm degradation and IsmwP for the maximum Is~
291
M. Shimaya et al. I Stresses in n-channel MOSFLT’s
3.2. Interface trap generation
Figure 3 shows the increase in charge pumping current (AZcp) for sample A, measured at a stress time that coincides with the lifetime of V-r shift for this sample. At VG = Vr + 0.4 P’, the rising edge of the AZcpcurve shifts toward the negative pulse base voltage VLe. Similar results were also obtained for other 3.3 V devices (B and D). This shift indicates that positive charges are created by hole trapping in the gate oxide [5]. The negative VLe shift becomes smaller as the drain bias decreases. This suggests that hole trapping in the oxide is reduced and that only interface traps are generated with decreasing drain bias. Trapped holes have been known to compensate for the influence of interface traps on VT shift[5]. We also found that the interface traps increase more rapidly at a Vr + 0.4 I’bias than bias. Therefore, interface trap at a ZSCJEJ-~~~ generation without apparent hole trapping at a Vr t 0.4 T/bias and a low drain bias is responsible for degradation enhancement.
5
.
I
Sample
A
I
’
0 v,
’
= v,
+ Isub-max
-6
-5
-4
-3 -2 Vbase (V)
I
+ 0.4 v cond.
-1
0
Fig. 3 hlcp
characteristics as a function of stress drain voltage after stress test, where the VTshift reaches 10 mV.
3.3. Evidence for the simultaneous iqjection of hot-hole and hot-electron A step stress test, where the drain bias was changed from 5.5 V to 4.6 V at a constant gate bias of Vr t 0.4 V, was performed. Figure 4 shows the AIcp change during the step DC stress test for Sample A. A negative Vbase shift, which was generated during the first step stress, decreased during the second step. This proves that the trapped hole was eliminated during low drain stress. This elimination can be attributed to neutralization caused by the electron injection that occurs during low drain stress. This is because hole detrapping was not observed during gate bias only or drain bias only stress. Figure 5 shows AZcp lifetime plots as a function of ZS&ZD. AIcp lifetime is defined as the stress time at which the AIcp increases to about 2~10-~’ A/pm. Two types of linear curves with different slope can be recognized. A slope of -5.5 is derived at Vc = Vr t 0.4 V, and a slope of -3.0 for the ZS~B_~~condition. These values suggest that hot-hole injection and hot-electron injection are responsible for 1oy
-6
-5
-4
-3 Vbase (V)
-2
Fig. 4 Change of AIcp characteristics
stress test at VG = VT + 0.4 v.
-1
0
“..I
.
Icp-max
. ‘.“‘I
change
20 PA/pm
.
‘j
0.10
0.01 lsubtld
after a step
Fig. 5 Zcp lifetime plots as a function of &.&ID for the ISVS_- condition and VG = VT t 0.4 V.
292
M. Shimaya et al. I Stresses in n-channel MOSFE?“.~
interface trap generation, respectively[5][6][7]. These slopes remain constant, regardless of the I,us/ID value which changes with stress drain bias. This suggests that hot-holes are still injected into the gate oxide at low drain bias, while hole-trapping in the gate oxide is reduced with a decrease in drain voltage, as shown in Fig.4. As a result, it can be supposed that hot-holes and hot-electrons are injected together into the channel region near the drain edge under a stress of VC = Vr + 0.4 vwith low drain voltage. Gate Electrode
3.4. Model for the simultaneous injection Enhanced degradation was observed when hot-holes were injected into the gate oxide followed by hotelectrons injections (5][8]. The degradation mode shown in our work also seems to be attributed to this effect. In our case, hot-hole and hot-electron are injected together at low gate and low drain bias. Figure 6 shows a model of simultaneous injection. At high drain voltage, since the direction of the vertical electrical field is towards the substrate, only hot-hole injection occurs at the channel region near the drain edge. With decreasing drain voltage, the vertical field direction changes towards the gate electrode at the drain edge and the position of the hole injection shifts into the drain region. On the other hand, the probability of electron injection increases. As a result, hot-electrons and hot-holes are injected together at the same region near the drain edge. 4. SUMMARY
1
H”‘” In]ecllon Gate Orlde
NP-S”bStralt?
“-
(a)High
N+ Drain
Dram Ems
Gate Electrode
1
Fig. 6 Schematic diagram of hot-hole and hot-electron injection region.
A new hot-carrier degradation mode has been observed under stress conditions of low gate and low drain voltage, where the lifetime of device degradation is significantly shortened. This new mode can be attributed to a generation of interface traps without positive charges caused by a simultaneous injection of hot-holes and hot-electrons. Therefore, device lifetimes of submicron devices for use in 3.3 V operation should be determined from the stress test at a gate bias of near threshold and at a drain bias lower than 5 V, instead of conventional ISLIB-~~bias stress tests. ACKNOWLEDGMENT The authors would like to thank Dr. A. Iwata for his continuous encouragement throughout this work. They also would like to thank the project team 4 for their sample preparation. REFERENCES Takeda, N. Suzuki, and T. Hagiwara, IEDM Tech. Dig., 1983. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, IEEE Trans. Electron [;IE.B.Devices, vol. 37, p.744, 1990. F.-C. Hus and H. R. Grinolds, IEEE Electron Device Letters, vol. EDL-5, p.71, 1984. Groeseneken, H. E. Maes, N. Beltran, and R. F. DeKeersmaecker, IEEE Trans. [i]G.Electron Devices, vol. 31, p.42, 1984. [51 P. Heremans,
R. Bellens, G. Groeseneken, and H. E. Maes, IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988. [61P. Heremans, G. Bosch, R. Bellens, G. Groeseneken, H. E. Maes, IEEE Trans. Electron Devices, ~01.37, p.980, 1990. [71 C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, IEEE Trans. Electron Devices, vol. 32, p.375, 1985. PI B. S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benecchi, A. Bravis, K. R. Mistry, and A. Boudou, IEEE Trans. Electron Devices, vol. 37, p. 1869, 1990.