A new method for evaluation of mis structure insulation films

Microelectronics and Reliability

Pergamon Press 1971. Vol. 10, pp. 105-114.

Printed in Great Britain

A NEW M E T H O D FOR EVALUATION OF MIS S T R U C T U R E I N S U L A T I O N FILMS* O. BENES and A. CERN~' TESLA Radio Communications Research Institute, Prague, Czechoslovakia Abstract--To evaluate the purity of MIS (metal-insulator-semiconductor) structure dielectric films, a new method was used which employs the slow charging of a measuring capacitor. In SiO~ layers impurities were found, having activation energies of 0.3 ; 0.45 ; 0.6 eV at concentrations of 1 10n to 5.10 x4 atoms/cm2. The results are given for SiOa+P20~, SiO2+SisN4 and SiaN 4 films. Furthermore, the results are given of an application of dielectric films to preparation of transistors and MOS integrated circuits in TESLA Radio Communications Research Institute. THE transistors

and M O S (metal-oxide-semiconductor) integrated circuits represent one of the recent successes of semiconductor physics which have been put into production. Their unique properties and simple manufacturing methods recommend them for wider application. T h e most significant growth can be recorded in the case of M O S ICs (integrated circuits) designed for computer logic and memory systems and automatic control equipment. When introducing the M O S IC production, a special problem of the M O S component technology must be successfully solved in addition to common planar production problems. It is the quality of SiO 2 insulation film. T h e impurities occurring inside of the insulation film could, even at inobservable concentration, substantially affect the properties of M O S components T o solve this problem suitable measuring equipment should be available for inspection of the produced insulation films. In our laboratory a method was developed for this purpose which employs the slow charging of a measuring capacitor. MEASURING OF THE PROPERTIES OF IMPURITIES IN THE INSULATION FILM

T o study the properties of impurities in the insulation film, the simplest structure--a M I S

capacitor--was chosen, comprising a silicon base, insulation film and metal electrode. Investigating the physical processes in the insulation film from the viewpoint of the applied voltage and the current in the outer circuit, we find that the moving ions of various impurities in the dielectric contribute to the outer current in the same manner as series resistance-capacitance combinations connected in parallel. T h e number and mobility of ions affect the current waveform and value. If we charge a capacitor with a suitably chosen voltage waveform, the charging current waveform is pulse-shaped with a characteristic maximum lm. T h e value of lm and its position on the time axis (given by the delay time tin) permits the parameters to be determined of an equivalent circuit for the capacitor (capacitance C, series resistance R). For an exponential voltage waveform

u(t) = U [ 1 - - e x p ( - - t / T ) ]

(1)

where U is the constant, t the time, T the time constant, the charging current is given by

i(t) -

U "re R T--"re [exp(--t/T)--exp(t/"rc)]

(2)

where "re = RC. T h e equation (2) is plotted in Fig. 1. Thus the physical processes in SiO2 film, acting * Reprinted from T E S L A Electronics, No. 1, pp. 3-10 (1970). under the effect of the applied voltage, could be in 105

106

O. B E N E S and A. (~ERNY ~X

I..,

~

i/k

I

R

S

c

0 ~tm

Ls

@@

t

X

X

r o

Fro. 1. Charging current through R and C series combination by a voltage waveform u(t) = U[1--exp

(-- t/T)].

O

(b)

ta)

FIG. 2. A model of the situation in SiO2 film.

principle simulated by means of a series connected capacitance C and resistance R. T o determine their values the current response for the exponential voltage pulse can be used. The real situation inside the film is not simple, however, and its accurate description would be difficult. Therefore we chose for the first approximation a simplified model, which provided acceptable values. The basic structure, used for our calculations, is a plate capacitor having electrodes of the area S and the dielectric of thickness d (see Fig. 2). If there are some moving electrical charges between the electrodes, an induced current can appear in the outer circuit of the capacitor, its value being

~U In, : - S 7 q(0).

. [1--exp (--tm/ T)] {1-- -~ [tm+ T(e-t
d

U -----tm-"'exp t tm/l) xj

(6)

Sq(O) [1--exp (--tm/T)] Im = tm+ T[exp (--tin~T)--1]

(7)

0

where 8(t) is the density of the induced current, and j(x, t) is the density of the current between electrodes. Introducing several simplifying assumptions, a single-valued relation between the amplitude (Ira) and the time delay (tin) of current pulses and basic physical characteristics of impurities in the dielectric film can be found, m If the moving charge carriers are uniformly distributed in the film, the following relations are valid: d2 _

UT tin~T+ 2 exp (--tm/T) -I- exp (tin~T)--3'

(4)

The measurement of properties of impurities in the dielectric films was done in the temperature range of 20-340°C, and this also permitted the activation energy of impurities to be determined simultaneously with the mobility and concentration. The evaluation was done under the assumption of Fig. 2(b). For calculations of impurity concentration another assumption was made, i.e. that the atoms of impurities were once ionized. At first, the single SiO,2 films were measured. Figure 3 shows a typical current response of the

A NEW METHOD FOR EVALUATION OF MIS STRUCTURE I N S U L A T I O N FILMS

107

The SiO 2 films prepared by thermal oxidation of silicon under absolutely pure conditions did not Iml show any impurities at temperatures up to 200°C (the measuring sensitivity is about 1"1011 atoms per cm2), as seen in Fig. 6. The effect of SiOs stabilization by means of 2O phosphorous glass, as it is known from literature, is apparent in the measurement of the sample S-18 (given in Fig. 7). The impurity concentration in [m 2 stabilized film is less than the threshold of the 7 measuring method. The SiO 2 film is not, as is well known, an ideal 1( dielectric for MOS components. Therefore other types of dielectrics were studied. Up to now the properties of a combined SiOs+Si3N4 film (Fig. 8) and homogeneous SisN ~films (Fig. 9) were investigated. The last sample (S-21) does not show any impurities up to 320°C. SO t [s~ 100 The preparation technology of pure dielectric FIG. 3. Current pulse of S-9 sample at 245°C; Ira1 and films was used for transistors and mainly for Ira2 correspond to carriers with activation energies of MOS-type logic IC series, as will be mentioned 0'33 and 0'6 eV. below. measuring capacitor using SiO 2 dielectric prepared by thermal oxidation of silicon. The current maxima I,nt and Iraa are caused by two types of current carriers (having an activation energy of 0.33 and 0.6 eV). The graphs of current maxima Ira1 and Ira2 and also of the time delay trnl and tin2 vs. reciprocal temperature are displayed in Fig. 4. The values Irac and tmc are related to the purely electrostatic capacitance of the measuring capacitor. From the above measurements the curves given in Fig. 5 were calculated, using equations (6), (7). The slope of the lines of mobility tL determines activation energy. The impurity concentration N is in practice independent of temperature variation. The results of measurements are given in Table 1.

M O S TRANSISTORS The experiments with M O S technology began on single M O S transistorsutilizingn-type channels.T o compare various production modifications, differing in threshold voltage, it was found suitable to use a standard drain-source voltage VDs = 20 V and to choose the gate bias Vas so that the drain current is Io = 1 m A . Under these conditions, the transconductance S--as a main transistor characteristic--wasmeasured at I kHz and, furthermore, the necessary gate bias Vas, which gave information about the value of chargc in SiO a. From these values the threshold voltage VTt can be calculated:

Table 1. Sample No.

Composition

Dielectric thickness

CA) S-9 S-17 S-18 S -20 S-21

SiOa Pure SiO2 SiOz + P2Os SiO~+ SisN, Si3N,

2000 2000 2000 1000+4000 3000

Activation energy of impurities (eV)

Impurity concentration (atoms/cm')

0.33; 0.6

2.1012; 5.10TM 1"1011 ~1.1011

108

(). B E N E S a n d A. CERN~" .<

I

E S-9

÷.'N

I

t,

$9 104o

¢.x r

10-,~

x..x2..

~

i

4-

i

tal Pe

V.

i

IO.L=

10.2

x

•.~.

'

l

,X'-

!

i

q~.~ lm2

i

~2

I

10-t= 10-12

•

i [

~ •.

~

\

10-t~-

10'3 tm 2

z

.~,.~ ,+

X

10 tmi

fl

-+ x

z

o "x + +

I o~

4 /

• • I" " • l N

i

E

~

i -I"

"-,o

r.~÷ °'"

I 260

.180 140

100

60

T[°C]

FIG. 4. Current maxima Im and time shifts tm vs. temperature for the S-9 sample (SiO2 2000 A): index 1, the impurity of 0"33 eV; index 2, the impurity of 0'6 eV; index C, static capacitance. Voltage polarity on Si: positive = "x" (dot-dash line), negative = " + " (broken line) and "o" (full line).

+: II Q

=

I0'2

1 340

x o

I.ID..• le4

tmc

2 °•

t I 300

~. '-I,

.... .

N I

o -.°

220 180

140

100

60 T [oC]

FIG. 5. Concentration N and mobility Iz of charge carriers in SiO2 for the S-9 sample: index 1, the impurity of 0.33 eV; index 2, the impurity, of 0'6 eV.

A NEW METHOD FOR EVALUATION OF MIS STRUCTURE I N S U L A T I O N FILMS

109

o(+)(--)

(-X+)O S-18

S-17 E

I0-))

•

.:'~:

.......

~___~==-

==

~,t" ~'J - ~ - " ~ ' . . . .

_ _ . . ~ . . . . . _~.___~

mmmm

10 ) o

.

<

z E

-

....

100 340

260 220 180 140

100

60

20

10o

T [°C]

FIG. 6. Current maxima Im and time shifts tm vs, perature for the S-17 sample (SiO= 2000 A). 21o

VT 1 = VGS-- ='~=,

tern=

300

220 180 140

.103

60

20.

T [oc] FIG. 7. C u r r e n t m a x i m a Im and time shifts tm vs. t e m perature for the S-18 sample (SiO~ 1900 A+P=Ob).

(8)

The threshold voltage V~2 was measured next, It is defined as a gate voltage for which the transconductance equals I ~A per V (at VDs = + 2 0 V). This way of measuring the threshold voltage was found better than the ordinary collector current cut-off method. It provides a correct value of threshold voltage without respect to the leakage (i.e. not controlled by gate) drain current and, moreover, it permits this leakage current to be

measured simply. The drain leakage current is usually caused by an inversion film on the silicon surface under SiO 2 out of the gate area. The difference between the threshold voltages measured and calculated by (8) then gives information about an extension of the transistor's transfer characteristic, caused by a non-uniformity of the value of threshold voltage in different sections of the channel.

I10

O. B E N E S and A. C E R N Y

104o

~(+)0 _E -

(--)(+)(4 S21

<

~,

S-20

E

A

-~. .......

"_._.~...~._~

104 , 10-1]

~_

......

~j

90

40 20 -r [o c ]

10 10'

A

..... x ...... E

~

::

/

10 10 0 300

220 180 140

100

60

20 T [°C]

Flo. 8. Current maxima Im and time shifts tra vs. temperature for the S-20 sample (SIO2 1000 A-t-SiaN4 400 A).

In this way, by using two measurements, a series of values can be obtained which are important from the viewpoint of evaluating the technology as well as for the practical application of M O S transistors. The samples of MOB transistors, made in our laboratory, had a rectangular channel of p - and n-types, and a circular channel of n-type only. The size of the rectangular channel was 15× 200 ~tm, the circular one had an internal diameter of 100 tzm and an external diameter of 120 txm. T h e SiO~. film thickness under the gate was about 0.1 [~m. A review of the most important transistor parameters is given in Table 2. The total gate

340

240 190

140

FIO. 9. Current maxima Im and time shifts t,, vs. temperature for the S-21 sample (SiaN4 3000 A).

capacitance C O and the transfer capacitance CoD were measured at 1 MHz. The main area of practical application of single M O S transistors, especially the circular channel samples, were the accessory amplifiers for the operation amplifiers zero correction in analog computers. Remarkable results were obtained in the Research Institute of Mathematical Machines in its applications, t2) For example, the correction part of an operation amplifier with a gain of 5000, in which a M O S transistor from our laboratory was used as a chopper, showed a temperature drift of the order of 0.01 ~tV/°C and the long-term instability was about 1 ~V during 1000 hr of operation.(a)

A NEW METHOD

FOR EVALUATION

OF MIS STRUCTURE

INSULATION

FILMS

111

laboratory sample is given in Fig. 10. The circuit employs three active MOS transistors and one as a load resistance. The circuit shows inverted product V = A B C function. The B and C gates can

MOS LOGIC INTEGRATED CIRCUITS

Experience with the manufacture of single MOS transistors allowed us to begin with work on MOS ICs. A schematic diagram of our first

Table 2. Operating point

Transistor design

Transconductance S(v,A/V)

IID [ = 1 m A

Gate voltage Vo(V)

I VD I = 20 V S = 1 t~/V

T h r e s h o l d voltage (V)

I VD I = 0"1 V

Gate voltage Va(V) R~ = 5 k n Rk = 1 M o

--1.52 --4"55

Capacitance Cc0(pF) R~ = 5 kt2 R~ = 1 M n

1.7 1.7

2.0 1'8

Capacitance Ca~(pF) Re = 5 kn Rk = 1 M~

0.33 0.15

0"67 0.14

O\,'

oW

J

Z Fig. 10. Schematic diagram of a t h r e e - i n p u t product gate.

calculated measured

550

Rectangular p-channel

I V a I = 20 V

Channel resistance

Bo

Circular n-channel

233 0.2

--14.2

-- 3.4 --4.0

-- 7.1 --6"2 --10'0 --5-6

be set aside by grounding the lead W and the circuit becomes an inverter: V = A. The channels of active transistors measure 10×150t~m, SiO~ thickness under gates is about 0.1 t~m. The complete circuit was mounted into a TO-5 case with eight leads. In addition to ordinary p-type channels, this circuit was also made with n-type channels. This made possible the comparison of the switching properties of both types. The results are reviewed in Table 3. The better switching parameters of the n-type channel circuit are caused mainly by higher mobility of electrons as compared to holes. A more detailed theoretical analysis is presented in Ref. (4). The condition of reliably blocked transistors, considering a reserve of appropriate noise immunity at logic zero voltage on the input, requires a positive threshold voltage at the n-type channel transistor, while with common production technique the threshold voltage is negative. The manufacturing difficulties in obtaining a reproducible threshold voltage lower the practical implication

112

O. B E N E S and A. (~ERNY Table 3. Switching time (nsec) Opening

Closing

Gate current (~A)

Type of channel p conductance n

97+11 66 -+13

5200_+800 50__+5 990 -+40 260 _+50

Ratio ofp and n values

1'5 (1 "1--2)

3.8 (2-5--6"3)

4'6 (4--5)

Switching times measured at [ U E [ = +20 V and ] UR I = +30 V by 15 V input pulse; the circuit connected as an inverter. The times were read from the respective pulse edge to the point, where the output voltage approaches 90 per cent of a steady value. The circuit was loaded with 10 M~/5 pF probe.

of the improvement of switching properties of n-type channel circuits. Therefore our next work was focused firstly on the circuits with p-type channels. Based on experience with the first modification, other types of M O S circuits were designed and manufactured. T h e first universal circuit is a fourinput gate, connected according to Fig. 11. This is a chain of four active M O S transistors, both ends of which are transistor-loaded. Lead-outs among transistors in the chain permit various interconnections. A single circuit can be connected as an inverter, two-input to four-input inverted product, two-input to four-input inverted sum, various combinations of inverted sums and products and, finally, as a buffer. T h e interconnection of a larger n u m b e r of circuits offers wide possibilities.

Table 4.

Ro

] OV

Parameter

Min.

Input (V) logic "0" logic "1"

-- 10

Output (V) logic "0" logic ' T '

--11

OW

Max. -3

Logic gain

Ao

Typical

--1

--2

5

Max. operating frequency (kHz)

300

OX

RI I Ii

O¥ V@

oo

OZ WO

I 1

& FIo. 11. Schematic diagram of a universal four-input gate.

BO

A

I[]

Ii

o V"

0 At 0 Wt

0 B'

Fie,. 12. Schematic diagram of an R-S flip-flop.

FIG. 14. Structure

FIG. 16. Structure

of a triple two-input inverted sum gate.

of an experimental

one-bit

shift register. facing Page 112

A NEW METHOD FOR EVALUATION OF MIS STRUCTURE INSULATION FILMS The second universal circuit is an R - S flip-flop, connected according to Fig. 12. Its function can be realized by interconnecting two four-input gates, but we decided to build a separate circuit. As it is a basic element for counters, memories and shift registers, it is suitable to have the flip-flop in one capsule. The principal parameters of universal circuits are given in Table 4. They are only tentative values, whose precise definition and completion will be possible only after a large number of circuits are measured. The switching delays of circuits in an inverter configuration with nominal supply voltages UE=--20V and / - J R = - - 3 0 V vary around 200 nsec when the active transistor is opened and 2-3 lzsec when closed. The current, flowing through the circuit at opening, is approx. 200 tzA. Increasing the gate voltage UR of the loading transistor to --35 or --40 V, the closing time delay can be reduced to less than 1 t~sec. The current flowing through the circuit would then increase to approx. 600 F.A. The universal circuits are suitable particularly for experiments. As regards practical employment in instruments there is a disadvantage in the fact that all the transistors in a universal circuit could be rarely exploited. An excessive number of universal circuits is then required for the realization of a more complicated function. The increased parasitic capacitance of a large number of connections is sometimes disturbing, in addition to causing certain economic problems. Therefore a number of simpler circuits mounted in one housing seems to be more advantageous in practical applications. Instead of one universal gate, three two-input or two three-input gates with common ground and supply leads can be placed into a 12-lead encapsulation. The gates could be of sum, product or combined type, their outputs either direct or inverted, with a buffer or without it. The assortment of necessary gates grows, as compared with a single universal gate. Several special gates, however, are satisfactory for practical applications, which provide a maximum encapsulation saving or are used most often. The universal gate may be left for other functions or replaced by other functions; these are contained in the series. In our view, the completion of a universal gate by a triple two-inpnt inverted sum NOR gate (Fig. 13) would save approx. 50 per cent capsules with circuits in

O'4.

113

0 V

o" lk -!LoB~ A2j . v

-!.LoB

-!.1

A~

_L Fta. 13. Schematic diagram of a triple two-input inverted sum gate.

logical systems design. The appearance of a triple NOR gate is shown in Fig. 14. According to customer requirements, the series of simple circuits could be completed by other logical functions or a J - K flip-flop. Recently the customer interest is concentrated mainly on more complicated memory MOS circuits as, for example, various shift registers (static or dynamic) and counters. To gain some experience in this area and to confirm principal relations in the technology, topology and electrical parameters, an experimental circuit was manufactured according to the schematic in Fig. 15. The circuit represents one bit of a shift register. The separated gate leads

RI

I E

R2

TT AO Z

6V'

FIG. 15. Schematic diagram of an experimental one-bit shift register.

114

~

BENE~q and A. CERNS"

of coupling transistors permit the clock pulses to be applied in various combinations and thus simulate the conditions for storage and shift of information in various types of static and/or dynamic shift registers. A view of the circuit is apparent from the photograph in Fig. 16. For practical applications we prepare the design of a 5-bit static shift register with a series input and parallel outputs. CONCLUSION

The p-type channel transistors are more suitable for use in logic integrated circuits because their characteristics ensure good noise immunity. To approve the principal properties of logic circuits and to find the application possibilities, a series of ICs was prepared. The first member of this series is a universal four-input NAND circuit, it is designed so that by suitably interconnecting the outcoming leads, other simple logical functions may be obtained. The other members of this series are an R - S flip-flop, a triple two-input NOR gate and an experimental circuit of a one-bit shift register. The circuits are driven by clock pulses with a frequency of up to 0.3 MHz. The economical and technical advantages of MOS ICs are most apparent in larger systems. Therefore we intend to extend substantially the logic circuit series by multibit shift registers, reversible counters, multiplexes, etc.

The special technology problem of MOS comp o n e n t s - t h e preparation of perfect dielectric films--was solved by means of the new method using "slow charging of the measuring capacitor". The sensitivity of this method approaches 1011 electrically active impurity atoms per cm 2. It is assumed that the compensation of the unwanted current caused by a purely electrostatic capacitance of the measuring capacitor would double the sensitivity of this method. The SiO2, SiO2+P205, SiO2-t-Si3N 4 and Si3N 4 dielectric films have been consecutively studied. REFERENCES The smallest concentration of active impurities 1. O. B~NE~ and A. (~E~q, The influence of the SiO~ was recorded for SiO 2 films which were processed structure on the properties of a MOS system. Wiss. in phosphorous atmosphere and for pure Si3N 4 Z. Elektrotech. 11, No. 9, 213 (1968). films. 2. J. DosraL, Analysis of the capacitance error of a The knowledge gained by the study of dielectric MOSFET chopper modulator. Electron. Engng 39, No. 476, 640 (1967). films was used in the development of transistors and MOS ICs. Several variants of n-type channel 3. J. DOSTAL,A switching modulator using a field-effect transistor. (Splnacl moduhltor s tranzistorem [izen3~m transistors were manufactured. Good parameters polem.) Proc. Seminar M O S Structure Semiconductor were achieved for the circular channel design, Components, pp. 51-87, Prague (1968). which also proved well as chopper. In the correc4. O. BEN~ and A. ~EaN~',A comparison of MOS logic tion amplifier employing this transistor, 1 ~V per integrated circuits with p-type and n-type channels. 1000 hr of operation was achieved for long-term XV Rassegna Int. Electron. Nucl., Rome, Part B-l, stability. pp. 134-142, April (1968).