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A new test structure for misregistration evaluation
687
Microelectronic Engineering 11 (1990) 687-691 Elsevier Science Publishers B.V.
A NEW TEST STRUCTURE FOR MISREGISTRATION N.N Kundu, K.I.
EVALUATION
Arshak, B Lane: J.Geane$ and S.N. Gupta*
Department of Electronics & Computer Engineering University of Limerick Limerick, Ireland inalog Devices B.V. Limerick, Ireland * Central Elec. Engg. Res. Inst. Pilani, India
Misalignment of patterns between different masking layers of integrated circuit is becoming a limiting factor in achieving higher density circuits. A single test structure has been designed and develooed to measure the amount of misalionment between various masking levels in CMOS/NMOS technology. Measurement is done The test structure can be implemented in the mask set electrically. of normal VLSI circuits as drop-in to evaluate misalignment of any combination of layers in the whole fabrication sequence.
1.
INTRODUCTION
In high density VLSI circuits, lithographic requirements are becoming more and more stringent. Very high resolution capability of modern lithography equipment can be utilized only if alignment accuracy and overlay are also improved proportionately. Regular monitoring of misalignment at various stages of fabrication is important in integrated circuit manufacturing. Various test structures for misalignment measurement have been proposed earlier(l-3). Most of these are suitable for measuring misalignment only between two selected layers for which it is designed. Consequently they can not be used to monitor misalignment of different masking levels of regular devices by putting it as process validation drop-in. Such limitation is not present in the new structure described in this paper.
2.
NEW ALIGNMENT TEST STRUCTURE
The new alignment test structure is based mainly on the principle of alignment resistor. The technique involves defining different taps of a resistor by various masking levels of fabrication process steps. The positional alignment of each tap will indicate the alignment error of the level that created it. The main resistor is formed by implantation during source/drain formation. A single structure can measure misalignment between combinations of levels of complex CMOS/NMOS technology. The resistance between different taps can be measured accurately by an automatic measurement system. Thus a large amount of data can be collected quickly for statistical analysis to quantify the contributions of various factors responsible for the misalignment. The integrated test structure can be looked upon as a series of resistors arranged symmetrically, in pair around a polysilicon area, similar to the gate
0167-9317/90/$3.50 0 1990, Elsevier Science Publishers B.V.
688
N.N.Kunduet al. I Misregistration evaluation test structure
area of a MOS transistor, although no active device is formed. Fabrication steps are same as that of normal CMOS/NMOS process. Each resistor in the symmetrical pair is placed on either side of the poly as shown is fig. I. Both resistors are designed to have equal values. Upon misalignment only lengths of the resistors change by an equal and opposite amount and consequently resistance values change, This difference is a measure of misalignment. Taps formed at various stages of fabrication are used for misalignment measurement of different combination of layers. As an example, for estimation of misalignment between poly and active area, voltages Vl between pads 5,6 and V2 between pads 8,9 are measured. Misregistration is proportional to the difference of Vl and V2. All voltages are measured using Kelvin four point probe method to minimize contact resistance by passing a constant current through pads 1 and 13. The present structure is designed to measure misregistration between following major masking levels: 1. 2. 3. 4.
Active area and Poly Poly and contact Contact and metal Contact and active area
As no special processing sequence is required for the fabrication of this test structure, this device can be used in the normal mask set as drop-in. The alignment accuracies in different levels can be measured easily. 3.
THEORY
If a current 'I' passes through the resistors then voltages, Vl and V2, developed across the left side and the right side resistors can be represented by Vl= I *!J * (L + Ax)/h’ V2 = I * P: * (L - AX)/W
...... . . . . . .
$1
Where x is the misalignment,P is the sheet resistivity of the conducting layer, L & W are the designed Length and width of the resistor respectively. From eqn. (1) & (2) it can be shown that the misalignment (ax) is given by the equation Ax = 0.5 * (Vl - V2) * (W/I*Ps)
.. .. . . (3)
The misalignment is not sensitive to the variation in window dimension that may arise due to process variations. As such variation will affect both the resistors equally thus cancelling each other. From equation (3) it is evident that the measurement of sheet resistivity of the conducting layer is required In this test structure sheet resistivity is for computation of misalignment. measured by adding two extra resistors at the extreme ends of the structure. Normally, local sheet resistivity measurement requires an extra test pattern. The factor, width/ (current * sheet resistivity) for determining the resistance Therefore this is common to all resistors and is unaffected by misalignment. measurement is required only once for each set of measurements in any one location. The factor is determined by measuring two voltages across two resistors(pads 2&3 and 11&12) located at extreme ends of the structure. across Lengths Ll & L2 are designed to be unequal. If V3 & V4 are voltages Ll & L2 respectively then width (current * sheet res.)
Ll - L2 zz !13 - v4
. .. . . .
(4)
N.N. Kundu et al. I Misregistration evaluation test structure
689
This eliminates the local sheet resistivity measurement which also helps in faster data collection by reducing number of measurements steps. 4.
RESULTS AND DISCUSSION
Fabrication of the test structure was carried out using standard CMOS process. Cannon FP501 proximity printer was used for lithography. After fabrication all measurements were done using a Keithley automatic parametric measurement system. Four-point Kelvin method has been used for the resistance measurement to avoid errors which might arise due to undesirable contact resistances. Before each set of voltage measurement a proper value of current that was to be passed in this method, was selected. This was to avoid errors in voltages (Vl and/or V2) that might have caused by ohmic heating, free carrier generation in certain type of material or due to noise(4), As all the resistors are formed in a single conducting layer only one current value is required to be selected for each location of measurements for all levels. Figures (2-4) show the measured misalignment vector maps. The combination of layers chosen are: poly/diffusion, diffusion/contact and contact/metal respectively. A similar structure, with slanted poly area instead of usual rectangular shape, was also fabricated along with the structure just described. The variation of resistance due to misalignment in this case is logarithmic. This is an advantage specially when the amount of misalignment is small. Fig.5 shows the measured output voltages from both straight and slanted structures. The slanted structure gives higher output and is thus preferable for small misalignments.
5.
CONCLUSION
A new test structure for accurate evaluation of misalignment between different levels in fine geometry VLSI circuit fabrication process has been presented. The structure can be incorporated in normal mask set as process evaluation drop-in. It has following advantages: * * * *
Capable of measuring misalignment between various combinations of two levels by a single structure. Good sensitivity for higher accuracy. Local sheet resistivity measurement is not required. Less number of measurement steps needed in each measurement for faster data collection.
ACKNOWLEDGEMENTS The authors thank all members of staff of NMRC, Cork for their help in carrying out the experimental work.
REFERENCES (1) (2)
T.J. Russel and A. Maxwel, "A production compatible micro-electronic test pattern for evaluating photo mask misalignment." NBS special publication no. 400-51, 1979. D.S. Perloff, "A four point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers" IEEE Journal of Solid State Circuits, Vol SC-13, No 4, pp. 436-444, 1978.
690
(3)
(4)
N.N. Kundu et al. I Misregistration evaluation test structure
I.J. Stemp, K.H. Nicholas and H.E. Brookman "Automatic Measurement and Analysis of Misalignments in Integrated Circuit Processing". Proceedings of the Conference on Microcircuit Engineering '79, Aachen, pp. 290-299, 1979. C.M. Cork, "Off-line photolithographic parameter extraction using electrical test structure" Proc. IEEE Int. Conference on Microelectronic test structures, Vol. 2, no. 1, pp. 7-14, March 1989.
Fig 1 Layout of Misalignment Test Structure
Fig 2 Vector Map (Diff/Contact)
Microelectronic Engineering 11 (1990) 687-691 Elsevier Science Publishers B.V.
A NEW TEST STRUCTURE FOR MISREGISTRATION N.N Kundu, K.I.
EVALUATION
Arshak, B Lane: J.Geane$ and S.N. Gupta*
Department of Electronics & Computer Engineering University of Limerick Limerick, Ireland inalog Devices B.V. Limerick, Ireland * Central Elec. Engg. Res. Inst. Pilani, India
Misalignment of patterns between different masking layers of integrated circuit is becoming a limiting factor in achieving higher density circuits. A single test structure has been designed and develooed to measure the amount of misalionment between various masking levels in CMOS/NMOS technology. Measurement is done The test structure can be implemented in the mask set electrically. of normal VLSI circuits as drop-in to evaluate misalignment of any combination of layers in the whole fabrication sequence.
1.
INTRODUCTION
In high density VLSI circuits, lithographic requirements are becoming more and more stringent. Very high resolution capability of modern lithography equipment can be utilized only if alignment accuracy and overlay are also improved proportionately. Regular monitoring of misalignment at various stages of fabrication is important in integrated circuit manufacturing. Various test structures for misalignment measurement have been proposed earlier(l-3). Most of these are suitable for measuring misalignment only between two selected layers for which it is designed. Consequently they can not be used to monitor misalignment of different masking levels of regular devices by putting it as process validation drop-in. Such limitation is not present in the new structure described in this paper.
2.
NEW ALIGNMENT TEST STRUCTURE
The new alignment test structure is based mainly on the principle of alignment resistor. The technique involves defining different taps of a resistor by various masking levels of fabrication process steps. The positional alignment of each tap will indicate the alignment error of the level that created it. The main resistor is formed by implantation during source/drain formation. A single structure can measure misalignment between combinations of levels of complex CMOS/NMOS technology. The resistance between different taps can be measured accurately by an automatic measurement system. Thus a large amount of data can be collected quickly for statistical analysis to quantify the contributions of various factors responsible for the misalignment. The integrated test structure can be looked upon as a series of resistors arranged symmetrically, in pair around a polysilicon area, similar to the gate
0167-9317/90/$3.50 0 1990, Elsevier Science Publishers B.V.
688
N.N.Kunduet al. I Misregistration evaluation test structure
area of a MOS transistor, although no active device is formed. Fabrication steps are same as that of normal CMOS/NMOS process. Each resistor in the symmetrical pair is placed on either side of the poly as shown is fig. I. Both resistors are designed to have equal values. Upon misalignment only lengths of the resistors change by an equal and opposite amount and consequently resistance values change, This difference is a measure of misalignment. Taps formed at various stages of fabrication are used for misalignment measurement of different combination of layers. As an example, for estimation of misalignment between poly and active area, voltages Vl between pads 5,6 and V2 between pads 8,9 are measured. Misregistration is proportional to the difference of Vl and V2. All voltages are measured using Kelvin four point probe method to minimize contact resistance by passing a constant current through pads 1 and 13. The present structure is designed to measure misregistration between following major masking levels: 1. 2. 3. 4.
Active area and Poly Poly and contact Contact and metal Contact and active area
As no special processing sequence is required for the fabrication of this test structure, this device can be used in the normal mask set as drop-in. The alignment accuracies in different levels can be measured easily. 3.
THEORY
If a current 'I' passes through the resistors then voltages, Vl and V2, developed across the left side and the right side resistors can be represented by Vl= I *!J * (L + Ax)/h’ V2 = I * P: * (L - AX)/W
...... . . . . . .
$1
Where x is the misalignment,P is the sheet resistivity of the conducting layer, L & W are the designed Length and width of the resistor respectively. From eqn. (1) & (2) it can be shown that the misalignment (ax) is given by the equation Ax = 0.5 * (Vl - V2) * (W/I*Ps)
.. .. . . (3)
The misalignment is not sensitive to the variation in window dimension that may arise due to process variations. As such variation will affect both the resistors equally thus cancelling each other. From equation (3) it is evident that the measurement of sheet resistivity of the conducting layer is required In this test structure sheet resistivity is for computation of misalignment. measured by adding two extra resistors at the extreme ends of the structure. Normally, local sheet resistivity measurement requires an extra test pattern. The factor, width/ (current * sheet resistivity) for determining the resistance Therefore this is common to all resistors and is unaffected by misalignment. measurement is required only once for each set of measurements in any one location. The factor is determined by measuring two voltages across two resistors(pads 2&3 and 11&12) located at extreme ends of the structure. across Lengths Ll & L2 are designed to be unequal. If V3 & V4 are voltages Ll & L2 respectively then width (current * sheet res.)
Ll - L2 zz !13 - v4
. .. . . .
(4)
N.N. Kundu et al. I Misregistration evaluation test structure
689
This eliminates the local sheet resistivity measurement which also helps in faster data collection by reducing number of measurements steps. 4.
RESULTS AND DISCUSSION
Fabrication of the test structure was carried out using standard CMOS process. Cannon FP501 proximity printer was used for lithography. After fabrication all measurements were done using a Keithley automatic parametric measurement system. Four-point Kelvin method has been used for the resistance measurement to avoid errors which might arise due to undesirable contact resistances. Before each set of voltage measurement a proper value of current that was to be passed in this method, was selected. This was to avoid errors in voltages (Vl and/or V2) that might have caused by ohmic heating, free carrier generation in certain type of material or due to noise(4), As all the resistors are formed in a single conducting layer only one current value is required to be selected for each location of measurements for all levels. Figures (2-4) show the measured misalignment vector maps. The combination of layers chosen are: poly/diffusion, diffusion/contact and contact/metal respectively. A similar structure, with slanted poly area instead of usual rectangular shape, was also fabricated along with the structure just described. The variation of resistance due to misalignment in this case is logarithmic. This is an advantage specially when the amount of misalignment is small. Fig.5 shows the measured output voltages from both straight and slanted structures. The slanted structure gives higher output and is thus preferable for small misalignments.
5.
CONCLUSION
A new test structure for accurate evaluation of misalignment between different levels in fine geometry VLSI circuit fabrication process has been presented. The structure can be incorporated in normal mask set as process evaluation drop-in. It has following advantages: * * * *
Capable of measuring misalignment between various combinations of two levels by a single structure. Good sensitivity for higher accuracy. Local sheet resistivity measurement is not required. Less number of measurement steps needed in each measurement for faster data collection.
ACKNOWLEDGEMENTS The authors thank all members of staff of NMRC, Cork for their help in carrying out the experimental work.
REFERENCES (1) (2)
T.J. Russel and A. Maxwel, "A production compatible micro-electronic test pattern for evaluating photo mask misalignment." NBS special publication no. 400-51, 1979. D.S. Perloff, "A four point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers" IEEE Journal of Solid State Circuits, Vol SC-13, No 4, pp. 436-444, 1978.
690
(3)
(4)
N.N. Kundu et al. I Misregistration evaluation test structure
I.J. Stemp, K.H. Nicholas and H.E. Brookman "Automatic Measurement and Analysis of Misalignments in Integrated Circuit Processing". Proceedings of the Conference on Microcircuit Engineering '79, Aachen, pp. 290-299, 1979. C.M. Cork, "Off-line photolithographic parameter extraction using electrical test structure" Proc. IEEE Int. Conference on Microelectronic test structures, Vol. 2, no. 1, pp. 7-14, March 1989.
Fig 1 Layout of Misalignment Test Structure
Fig 2 Vector Map (Diff/Contact)