A new serial system for CAMAC

Interfaces in C o m p u t i n g , 3 (1985) 143 - 152

143

A NEW S E R I A L S Y S T E M F O R C A M A C * D. HORELICK and L. PAFFRATH S t a n d f o r d L i n e a r A c c e l e r a t o r Center, P.O. B o x 4349, S t a n f o r d , CA 9 4 3 0 5 (U.S.A.)

(Received February 7, 1985)

Summary A new high speed serial CAMAC system developed at Stanford Linear Accelerator Center for general use in c o n t r o l systems and experimental applications is described in this paper. The line p r o t o c o l on which the system is based will be described, followed by the serial branch driver and CAMAC crate controller which support this protocol. The serial branch driver contains an assortment of scan modes particularly useful for data gathering in experiments.

1. I n t r o d u c t i o n A new high speed serial crate controller (SCC) and serial branch driver (SBD) for CAMAC have been designed at Stanford Linear Accelerator Center (SLAC). This system is based on (1) standard RS-422A differential line drivers and receivers, (2) up to 16 crates on a twisted-pair party line, (3) selfclocking biphase encoded line signals, (4) single-master multiple-slave line control, (5) separate twisted pair for p r o m p t L signals, (6) response after every c o m m a n d (system handshake), (7) no parity (for use in limiteddistance k n o w n environments) and (8) versatility and simplicity in the SCC, with more c o m p l e x scanning algorithms in the SBD. With a bit rate of 5 Mbits s - l , the overall serial line transaction time is 11 psec for 16-bit read data transfers, i n d e p e n d e n t of the n u m b e r of crates on the bus. Both 16-bit and 24-bit data transfers are separately support ed for the mo s t efficient line utilization. The SBD contains circuitry to handle some 22 CAMAC scanning modes, and it is p a t t e r n e d after a similar parallel branch driver developed previously at SLAC to achieve a high degree of code compatibility with the prior unit.

*Portions of this paper will appear in I E E E Transactions on N u c l e a r Science. 0252-7308/85/$3.30

© Elsevier Sequoia/Printed in The Netherlands

144 2. Typical application The c o m b i n a t i o n of SCCs and the SBD is particularly useful in applications where either the crates are in r e m o t e locations (up to 1200 ft) or a large n u m b e r o f crates need to be controlled. Figure 1 shows a typical system configuration. In this system, one twisted pair is required for the c o m m a n d and data transfers; the second pair, which is an OR of SCC LAMS, is imp lemen ted only if the system requires and can handle LAMS.

~

A

5 Megablt s/s CAMAC RS-422A System Differential TTL / itionoI Serial Brunches / One or Two Twisted Pairs- Up to I000 Feetj('~

W FT-I- -

C,~MAC

F~

...

SCC= Serial Crate Controller SBD--- Serial Branch Driver ( ~ = Line Terminator

i ii

iFI

Per Branch

Fig. 1. Typical system configuration.

F o r systems where the cable length does n o t exceed 500 ft, cable such as Belden 9730 is satisfactory; for distances up to 1200 ft, cable such as Belden 9851 is used. Both ends o f the cable are terminated to eliminate signal reflection. It should be n o t e d here that the m a x i m u m achievable block transfer rate is 276 Kbytes s ~, assuming a bit rate of 5 Mbits s -I. At SLAC the first operational system using SBDs and SCCs has three SBDs driving three serial branches. One serial branch 1200 ft in length communicates with seven crates containing magnet pow er supply controllers and monitors; the o t h e r t w o branches c o m m u n i c a t e with three crates containing a variety o f data acquisition modules.

3. Line

protocol

The discipline of the serial link connecting the SBD and SCC is shown in Fig. 2. The messages are grouped into " c o m m a n d s " , from SBD to SCC, and "responses", f r om the addressed SCC back to the SBD. For most efficient use of the line, each message is preceded by a unique SYNC bit at the electrical line level. This SYNC consists of a double-width pulse n o t occurring in any message, which initializes all units on the line for every message and assures that they properly interpret the three line cont rol bits

145 .ERli~L

LiNE

PROTOCOL

]he protocol is defined by o special sync bH, followed O~ 5 ne c:n:ro! blls, the corer-rand or do*o message, and completed b~, O te,r", no" ,

B - : Type Cammonds (=raft' Driver to SCC):

C ~ Word Length

,~&MAC COrT,m,ond I A ~ ,~

(~ot~

'¢~,lte

Dot 9

A 9 C

FuncTion

,$Jbqdq,ess

16 bits or 24 b t s ~

WrPe 3ate

[ ~ W ,

Module

Opt. 24 Bits ,

16Bits W i 6 i B B i t s

W'24~

~hoM Command for Read Block Tronsfer~or Repeal .Son'rol: A B C

qescs~ses ',F ram SCC to Driver): ;,~eod Oat(] /'. E~, ~] Q

!

:

i6 bi~s or 24

X L

bits:

Read Da!o

Opt. 24 bits

'or ' of L ines ,p adOfessed crole, gated by L enable. Read L l=mes

P~ ':~ (

I *

L

24 b~l mcde: Read L Line

L4

Reads state of L Enable F F :. k'ort Rest:)snse

for~r~te,

Write

Bioc~ Transfer, Conf~ol :

A B ', Q X •

Fig. 2. Line protocol.

A, B and C on every transaction, thereby avoiding troublesome SYNC search and recovery procedures. Once a crate is addressed by a c o m m a n d message, it remains in this state until unaddressed by another command. Hence an inherent feature of this line protocol consists of "single-address" block transfers for read, write and control, achieving an increased transfer rate because of the lower line overhead. Other types of block transfers are achieved by SBD algorithms; these achieve higher data rates through central processing unit (CPU) overhead reduction. Another approach to improved line utilization is the use of dual data formats, one for 16 bits and the other for 24 bits (the use of the C bit should be noted). This capability exists for both random operations and the block transfer mode. Actual transaction times for 16-bit transfers are given in Table 1, n o t including CPU overhead.

146 TABLE

1

Transaction times at 5 Mbits s -1 Random read Random write Control Single-address read block transfer Single-address write block transfer Control block transfer

11 ~zs 12 ps 8/~ s 7.5 ps 7.5 ps 4.5 ps

Read and write times assume 16-bit data transfers.

F o r every a c t i o n in an addressed SCC a response message is r e t u r n e d t o SBD. With every such message t h e state o f Q, X and L is included, t h e r e b y p r o v i d i n g a t y p e o f " p o l l e d " L capability, in a d d i t i o n to the p r o m p t L described previously. O n c e a crate c o n t a i n i n g a positive L response is identified, a special c o m m a n d to the SCC r e t u r n s the state o f all 23 Ls in t h e a f f e c t e d crate to i d e n t i f y f u r t h e r t h e source(s). The presence o f a d e f i n e d response a f t e r every o p e r a t i o n gives c o n t i n u o u s c o n f i r m a t i o n o f s y s t e m o p e r a t i o n as well as providing a s y s t e m h a n d shake f o r o p t i m u m t i m i n g o f o p e r a t i o n s .

4. Special c o m m a n d s o f t h e serial crate c o n t r o l l e r A set o f special c o m m a n d s directed t o the SCC itself is p a t t e r n e d after similar o p e r a t i o n s in t h e s t a n d a r d t y p e A and L-2 crate controllers. These are s h o w n in Table 2 and are s e l f ¢ x p l a n a t o r y . TABLE 2 Special commands of the serial crate controller

N(31) N(30)F(0)A(0-7) N(30)F(24)A(9) N(30)F(26)A(9) N(30)F(24)A(10) N(30)F(26)A(10) N(28)F(26)A(9) N(28)F(26)A(8) Power on

Addresses all modules Read L signals, I line, L enable Set I = 0 Set I = I Disable L Enable L Run CAMAC cycle with C = 1 Run CAMAC cycle with Z = 1, set I -- 0, disable L Same as Z

5. Description o f the serial branch driver The design o f t h e SBD was greatly d e t e r m i n e d b y the r e q u i r e m e n t t o be highly s o f t w a r e c o m p a t i b l e with a parallel b r a n c h driver s y s t e m already

147

I C'ate :%TLW B~ts

I

Module

lS~boddressl

I

Mode Bits

I

Fu~c,on

18l 121 , 1,6181 121, I 1 ]21, I lL×lLqsq q l'q l l l'

I

I

CAMAC R&W tl>es Where : O the do*a -node, D 0 corresponds to the 1 6 - b i t mode D- I corresponds to the 24 b~t mode LX, LQ, SC, SN, S,h - scan mode controL bits where in gener}l: SA implies scon A (LSB} SN ~mpi,es scan N SC imp!~es scan C LQ implies

LAM on no Q

LX imphes LAM on no X (MSB)

Fig. 3. SBD c o n t r o l w o r d f o r m a t .

existing at SLAC. A restriction in the use o f the SBD is t h a t it m u s t be used in a CAMAC crate where the crate c o n t r o l l e r recognizes and o b e y s the H O L D line. T h e basic o p e r a t i o n requires t w o CAMAC cycles in the SBD crate for e v e r y CAMAC cycle in t h e r e m o t e crate. First, a c o n t r o l w o r d (Fig. 3) is l o a d e d with an F ( 1 7 ) A ( x ) . This c o n t r o l w o r d can be read back b y an F ( 1 ) A ( x ) read c o m m a n d . T h e n , e i t h e r an F ( 1 6 ) A ( x ) or an F ( 0 ) A ( x ) will cause a serial transmission to, a CAMAC cycle in and a response f r o m the r e m o t e crate. On r e c e i p t o f this c o m m a n d , the H O L D line is set to one. T h e n the c o n t r o l c o m m a n d is t r a n s m i t t e d via t h e m u x (shown in Fig. 4) t h r o u g h the d a t a e n c o d e r o n t o t h e d a t a bus. T h e following t h r e e actions occur. (1) If t h e F c o d e in t h e c o n t r o l w o r d is a write, the d a t a o n the W lines are t r a n s m i t t e d via the m u x and d a t a e n c o d e r ; the SBD t h e n turns o f f t h e t r a n s m i t enable and awaits t h e response. (2) If the F c o d e in t h e c o n t r o l w o r d is a read, the SBD turns o f f the t r a n s m i t enable a n d awaits t h e read d a t a and response, (3) If the F c o d e in t h e c o n t r o l w o r d is a dataless o p e r a t i o n , the SBD turns o f f t h e t r a n s m i t enable and awaits the response. On r e c e i p t o f the response, t h e SBD releases t h e h o l d line, allowing t h e n o r m a l c o m p l e t i o n o f the d a t a w a y cycle. S h o u l d t h e r e be n o response within the e x p e c t e d time, t h e SBD times o u t , releases the h o l d line and again allows t h e d a t a w a y cycle t o c o m p l e t e . Figure 5 shows a t y p i c a l SBD timing sequence. T h e d a t a w a y S1 and $2 strobes o c c u r a f t e r the release o f the hold line. T h e X and Q r e s p o n s e o f t h e r e m o t e c r a t e is passed t o the d a t a w a y . It s h o u l d be n o t e d t h a t a l t h o u g h t h e SCC includes in its response the state o f L w i t h i n its crate, this is ignored b y t h e c u r r e n t i m p l e m e n t a t i o n o f t h e SBD for s o f t w a r e c o m p a t i b i l i t y with t h e SLAC parallel-branch driver.

148 DATABUS

I

~

.~

MUX

-

~_~

runSmconC~ro/~Un t ~ [ ~

~w

=CTLw

~

NFA Hold L

Fig. 4. SBD block diagram.

ofsBD-- y Lood Control Word

Remole Operation

Hold Transmit Enable ____1

J'~ ,

k

Databus ,RemoteCAMACCycle

Fig. 5. Typical SBD timing sequence. The m o d e bits are used for scanning operations, which are used to improve system t h r o u g h p u t for large data acquisition systems. Of the 32 possible modes, 22 are implemented. Table 3 shows several examples. Mode 1 allows scanning of a single module, m o d e 2 a scan of all modules within a crate, m o d e 4 a scan o f all crates and m o d e 15 a scan of all modules in all crates. When using these modes, the SBD takes full advantage of the short c o m m a n d for read block transfer or repeat control. 6. Description o f the serial crate controller System design of the SCC to implement the described p r o t o c o l is quite straightforward. A block diagram is shown in Fig. 6. The data decoder

149 TABLE 3 Selected scan modes of the serial branch driver

Scan mode

LX

LQ

SC

SN

SA

Description

1

0

0

0

0

1

2

0

0

0

1

0

4

0

0

1

0

0

7

0

0

1

1

1

Scan A up to 15 with the same N and C L is g e n e r a t e d a f t e r A = 1 5 S c a n N u p t o 23 w i t h t h e s a m e A a n d C L is g e n e r a t e d a f t e r N = 23. S c a n C u p t o 15 w i t h t h e s a m e A a n d N L is g e n e r a t e d a f t e r C = 1 5 S c a n A u p t o 15 w i t h t h e s a m e N a n d C; t h e n s c a n n e x t N w i t h A = 0 - 15 u n t i l N = 23; then scan next C with N = 1 23 a n d A = 0 - 1 5 for eachN L is g e n e r a t e d a f t e r A = 15, N = 23 a n d

C=15

• Bus

J

2-coc

"1 Rec°veyr I ~ "

~

Sync

~1 Reqster J

k ~

Receive Control (FPLS)

RV'r~' ~

K~

Regs~e~ Data Encode

~

I0 MHZ

XTAL

MUX

]~

(5 iVlegaBits/sec) Fig. 6. B l o c k d i a g r a m o f SCC.

I

Transmit 1 Control (FPLS)

A I .....le~ F--I cianol~

150 regenerates NRZ data, clock, and SYNC from the encoded data. The data are then shipped to serial-to-parallel shift registers as directed by the control circuitry. The internal 10 MHz crystal clock takes over and runs a CAMAC cycle followed by parallel-to-serial conversion in shift registers as appropriate. A multiplexer selects the " r e a d " register, or the L register as appropriate, for transmission to the data encoder, which adds SYNC bits A, B and C, encodes into biphase and terminates the message properly. All special c o m m a n d s are decoded in an 82S100 FPLA. The key elements in the cont r ol sections are two 82S105 FPLS which direct actions and store sequence states depending on the bit c o u n t state contained in a c o m m o n 64-bit counter. This same " c o u n t state" philosophy is used to generate the CAMAC cycle during the " t ransm i t sequence" instead of using discrete logic.

7. L i n e s i g n a l s

Differential line signals are used. A typical encoded data stream is shown in Fig. 7. It should be not ed t ha t a transition occurs at each normal 200 ns bit b o u n d a r y to permit bit-by-bit clock recovery in the decoder, which avoids phase-locked loops. A transition in the center denotes a one; no transition indicates a zero. For a self-clocked syst em , this t y p e of data encoding makes the most efficient use o f line bandwidth. The unique SYNC pulse preceding each message is a 400 ns positive pulse, easily distinguishable f r o m the ~rest of the message. T e r m i na t ion following the message consists of returning the line to the zero level one-half bit time later, if the final level at the end of the message is at the one level. Both SYNC and termination are shown in Fig. 7. SYNC

+

"1'

-

0

0

0

I

-

I

~

T

1

Dalo

T : ]er mination Pulse Returns Lme lo Zero Level A'qer sage

-- " 0 "

--I

2 0 0 ns

i

I

~--I

I

I

I

t (ns]

Fig. 7. Line signal waveform. The twisted pair is terminated in its characteristic impedance at each physical end to eliminate reflections. The termination n e t w o r k shown in Fig. 8 also includes a small a m o u n t of inherent bias, to keep the receivers in the zero state when all drivers are in the high impedance state. As the signals propagate along the line, t h e y are distorted by line dispersion and a " j i t t e r " is i nt r oduced at the zero, or slicing, level where

151

+5V 1.2 Kg? B. . . . f ' 200mV

,\~ \ \

I10~ I I . 2 K*

+5',,'

2BoOm°f

1.2 K,~ liO,~ 1'-2K~

Tw s*es Pair

l ~-~*_

/ : ~O0~,

+5'v

~u~\\,

I1240~

Be der, 9750

l ~-~*

l 240-0" Belden 985i

compahbqlly

Fig, 8. Line termination networks,

ENCODER

75159

t

Message Gate

~

I

:2 ~

oMH: 1

Nole Does not Snow Sync ]enerahcn

DECODER ~ E d g e

TS175

~ulses

q_7

96S02

4 L S '4 A

Dots

~,',:Z>

-rr~Zb_

N°n- Retr19 I

q~

tZ~

J

Fig. 9. E n c o d e r - d e c o d e r circuits.

an ideal receiver switches. This jitter, or timing error, is w h a t primarily limits t h e line length. We have run s y s t e m s at 5 Mbits s ~ using Belden 9 7 3 0 cable over 5 0 0 ft with immeasurable error rates and over 1 0 0 0 ft using Belden 9 8 5 1 cable. We have f o u n d that the m a x i m u m transmission distance is achieved w h e n the S B D driver is in the high i m p e d a n c e state rather than the zero state prior to the message transmission.

152 8. E n c o d e r - d e c o d e r The en co de r (transmitter) and decoder (receiver) circuits used in both SBD and SCC are shown in Fig. 9. In the encoder the J - K fl i p-fl op assures a transition at each bit b o u n d a r y , as well as at the center for a one. SYNC and t e r m i n a t i o n generation circuitry are n o t shown. The d eco der is one-shot based for simplicity and toleration of line distortion. The circuit derives clock pulses, SYNC and NRZ data from the received signal stream.

Ack n o wled g ment s The authors wish to acknowledge the support of R. Melen and M. Breidenbach at SLAC and the contributions of M. Browne and S. MacKenzie. H. Walz first suggested the use of the FPLS to implement the control logic of the SCC. Work s u p por t ed by the D e p a r t m e n t of Energy, Contract DE-AC0376SF00515.