- Email: [email protected]
A novel LDMOS structure using P-trench for high performance applications
Materials Science in Semiconductor Processing 39 (2015) 654–658
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp
A novel LDMOS structure using P-trench for high performance applications Ali A. Orouji n, Hojjat Allah Mansoori, A. Dideban, Hadi Shahnazarisani Electrical and Computer Engineering Department, Semnan University, Semnan, IRAN
a r t i c l e in f o
Keywords: LDMOS Silicon on insulator Trench 2-D device simulation.
abstract In this paper, we propose a new structure of silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) field effect transistors to improve the device performance. In the proposed structure, a trench is created in the buried oxide under the drift and drain regions and filled with p-type Si. We called the proposed structure as P-trench SOI-LDMOS (PT-LDMOS). Our simulations with two dimensional ATLAS simulator shows the unique features exhibited by the proposed structure in comparison with a conventional SOI-LDMOS (C-LDMOS). In the PT-LDMOS, the electric field is modified by producing a new additional peak at the electric field distribution, reducing the magnitude of electric field peak near the gate edge, removing of electric field crowding near the drift and drain junction at the bottom surface of the silicon layer, and making the surface electric field distribution more smooth. We optimize the doping concentration and the dimensions of the P-trench in the PT-LDMOS structure. Hence, the results illustrate the benefits of high performance PT-LDMOS over conventional one and expand the application of SOI-LDMOSs to high voltage. & 2015 Elsevier Ltd. All rights reserved.
1. Introduction Due to the significant advantages of lateral double diffused MOSFET (LDMOS) structure compared to traditional structures including, high compatibility for integration into modern BiCMOS power technologies, high power gain and efficiency, and low cost, this structure has been extensively utilized in intelligent power integrated circuits [1–4]. On the other hand, by considering the numerous benefits that is provided by silicon on insulator (SOI) technology such as ideal dielectric isolation, compactness, high speed, high temperature capability, and low loss, there is a great interest in applying these structures for production of high-voltage lateral devices [5–8].
n
Corresponding author. Tel.: þ982333654100, Fax: þ982333631623. E-mail address: [email protected] (A.A. Orouji).
http://dx.doi.org/10.1016/j.mssp.2015.05.063 1369-8001/& 2015 Elsevier Ltd. All rights reserved.
In SOI structure for power devices due to the existence of buried oxide layer, two issues have attracted the attention of self-heating effect (SHE) and low breakdown voltage [9–11]. In recent years, numerous schemes have been proposed for SOI-LDMOS to improve the performance of the device and solve these problems [12–14]. In this paper a new structure is presented for LDMOS devices to overcome the low breakdown voltage problem. The proposed structure enhances the breakdown voltage by applying a P-trench that is placed under the drift and drain regions. We called the proposed structure as P-trench SOILDMOS (PT-LDMOS). In this work, it will be illustrated that the electric field of the proposed structure is modified by producing an additional electric field peak, reducing the peak of electric field near the gate edge, and removing the electric field crowding near the drift and drain junction at the bottom surface of the silicon layer. Therefore, access to a more homogenous curve for the electric field distribution will be available in the PT-LDMOS structure and the
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
characteristics of conventional SOI-LDMOS (C-LDMOS) are significantly improved. So, first the proposed structure will be introduced and then we will present two-dimensional numerical simulation results [15] of the proposed structure and the influence of the P-trench will be compared with the C-LDMOS characteristics.
2. Device structure and simulation method Fig. 1 shows the schematic cross-sectional view of the proposed structure. As shown in the figure, a trench is created in the buried oxide at the drain side and filled with p-type doping to improve the breakdown voltage. The physical parameters used for simulating the PT-LDMOS structure are equivalent to the device parameters of the CLDMOS structure, but the C-LDMOS structure does not have the P-trench in the buried oxide. These values are specified in Table 1. Also the width of the device for both the structures is 1 μm. In order to investigate the effects of P-trench creating at PT-LDMOS performance the simulations carried out by using ATLAS 2-D device simulator. Various models including, “SRH”, “Auger”, “Analytic”, “Fldmob”, “Incomplete”, and “Impact Selb”are utilized in simulation to reach more actual results.
655
3. Discussion and results When the applied voltage between the drain and source for the C-LDMOS structure is equal to breakdown voltage, the height of the electrical field peaks is close to a critical amount at two regions; one at the gate edge side to drift region at the top surface of the silicon layer and the other one is placed near the drift and drain junction region at the bottom surface of the silicon layer [16] as illustrated in Fig. 2. The figure shows the 2-D electric field curves at the top surface and the bottom surface of the silicon layer for the C-LDMOS and PT-LDMOS structures, respectively. So, the high breakdown voltage can be provided by reducing the electric field peak in these regions. The P-trench that is used in the proposed structure leads to the displacement of electric field crowding near the drift/drain junction at the bottom surface of the silicon layer and putting it at the bottom surface of P-trench in the buried oxide, creating an additional peak at the electric field distribution, reducing the peak of electric field near the gate edge, modifying the electric field in the drift region and monotonous surface electric field distribution. Therefore, it is possible to achieve higher breakdown voltage (VBR) in the proposed structure
Fig. 1. Cross section of the PT-LDMOS structure.
Table 1 Device simulation parameters. Parameters
Symbol
Value
Unit
Length of drift region Length of buried oxide Thickness of buried oxide Height of P-trench Length of P-trench Doping of P-trench N þ Source/drain doping Doping of N drift region Doping of P-substrate layer Length of channel
Ldrift LBOX tBOX H L Nt Nn Nd Nsub Lchannel
10 14 1 0.9 4 1 1013 1 1019 2 1016 1 1013 2
mm mm mm mm mm cm 3 cm 3 cm 3 cm 3 mm
Fig. 2. Electric field distribution for the C-LDMOS and PT-LDMOS structures at (a) top surface and (b) bottom surface of the silicon layer.
656
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
[17–19]. In the PT-LDMOS structure the height of the common peak near the gate edge is reduced by producing a new peak at the drift region due to creating the P-trench, and more uniformity is observed in distribution curve of the electric field; on the other hand, since the area occupied underneath the electric field distribution curve is increased in the PT-LDMOS structure and this area is equal to the voltage magnitude that is applied to the device, a significant enhancement in the VBR of the proposed structure can be seen [20]. The VBR improves from 72 V for the C-LDMOS to
Fig. 5. The breakdown voltage versus the height of P-trench.
110 V for the PT-LDMOS. Therefore, a 52.77% increment in the VBR of the proposed structure is achieved, and the device can tolerate much higher voltages compared with the C-LDMOS structure. The equipotential contours of the C-LDMOS and PT-LDMOS structures at their VBR are shown in Fig. 3(a) and (b), respectively. The figure shows the extraordinary effect of the P-trench in distributing the potential lines toward the drain. The drain current (ID) of the PT-LDMOS and C-LDMOS structures are plotted in Fig. 4 for the various drain–source voltage from 0 V to 30 V. It can be seen that the ID improves from 120 μA for the conventional structure to 133 μA for the proposed structure, at VDS ¼30 V condition. Therefore, a significant increase in the ID of the PT-LDMOS structure is achieved in comparison with the C-LDMOS structure.
Fig. 3. Simulated equipotential contours at breakdown voltage for the (a) C-LDMOS and (b) PT-LDMOS.
4. Design considerations
Fig. 4. Drain current against drain–source voltage for C-LDMOS and PTLDMOS structures.
In order to achieve the best results and the importance of designing a high-power device, it is important to investigate the effect of height, length, and doping density of P-trench on the breakdown voltage. The initial values for height (H), length (L), and doping are determined as 0.9 μm, 4 μm, and 1 1013 cm 3, respectively. Fig. 5 shows the values of VBR for the PT-LDMOS according to the trench height. As the trench height increases, it can modulate more parts of the channel electric field distribution. But, if the trench height increases more than 0.9 μm the additional electric field peak in the drift region disappears, and the electric field peaks increase at the top surface near the gate and at the bottom surface near the drain. Therefore, if the trench height increases more than optimum value, the breakdown voltage is significantly reduced. The breakdown occurs at the bottom surface of the silicon layer near the drain region, so when the p-type trench region is situated under the drain, the VBR increases. When the trench length is beyond a certain amount, the p-type trench edge will be far away from the drain edge and gets
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
Fig. 6. Electric field distribution for the PT-LDMOS for different lengths of the P-trench more than 4 μm at (a) top surface and (b) bottom surface of the silicon layer.
closer to edge of the gate region, and the effect of P-trench on the reduction of the electric field crowding and the height of the additional peak at electric field distribution will be lower. Fig. 6 shows the electrical field distribution for PT-LDMOS by different lengths of P-trench (L¼ 4 μm, L ¼6 μm and L¼8 μm). It is clear from the figure that by increasing the length of P-trench the additional peak at the electric field distribution, far from the drain edge and the area underneath the electric field curve is reduced. Therefore, the breakdown voltage for the PT-LDMOS structure with P-trench more than 4 μm decreases. By reducing the length of P-trench to lower than 4 μm, the new peak that is added to the electric field in the drift region, moves to the drain side and the magnitude of this peak is increased. Although the magnitude of additional new peak is enhanced, the breakdown voltage decreases due to the reduction of area underneath the electric field curve, as shown in Fig. 7. The values of the VBR for PT-LDMOS structure with various P-trench lengths are plotted in Fig. 8. The doping density of trench significantly affects the device characteristics. By increasing the doping density of the P-trench to 1 1013 cm 3, the VBR of the PT-LDMOS
657
Fig. 7. Electric field distribution for the PT-LDMOS for different lengths of the P-trench lower than 4 μm at (a) top surface and (b) bottom surface of the silicon layer.
Fig. 8. The breakdown voltage against the length of P-trench.
increases, which can be seen in Fig. 9. When the P-trench doping density is higher than a certain amount the breakdown voltage decreases.
658
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
conventional LDMOS (C-LDMOS). Also the driving current of the proposed structure has desirable improvement. References
Fig. 9. The breakdown voltage according to doping of P-trench.
5. Conclusion We proposed a new structure for SOI-LDMOSFET with a P-trench (PT-LDMOS) in the buried oxide at the drain side to achieve high blocking voltage. The P-trench in the proposed structure leads to displacement of the electric field crowding near the drift/drain junction at the bottom surface of the silicon layer and putting it at the bottom surface of the P-trench in the buried oxide. Also, by using P-trench an additional peak is created at electric field distribution, and peak of the electric field near the gate edge is reduced, therefore the electric field distribution in the drift region is modified and more uniform. Investigations by using two dimensional numerical simulations demonstrated that by applying the P-trench the breakdown voltage improved by 52.77% in comparison with a
[1] M. Zitouni, F. Morancho, P. Rossel, H. Tranduc, and J. Buxo, A new concept for the lateral DMOS transistor for smart power IC's, in: Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99, 1999, pp. 73–76. [2] C.W. Tang, K.Y. Tong, Solid State Electron. 46 (12) (2002) 2111–2115. [3] T.R. Efland, C.-Y. Tsai, and S. Pendharkar, Lateral thinking about power devices (LDMOS), Technical Digest, International Electron Devices Meeting. IEDM'98, 1998, pp. 679–682. [4] G. Cao, S.K. Manhas, E.S. Narayanan, M.M. De Souza, D. Hinchley, Electron Devices, IEEE Trans. 51 (8) (2004) 1296–1303. [5] A. Nakagawa, N. Yasuhara, Y. Baba, Electron Devices, IEEE Trans. 38 (7) (1991) 1650–1654. [6] J.G. Fiorenza, J.A. Del Alamo, Electron Devices, IEEE Trans. 49 (4) (2002) 687–692. [7] M. Bawedin, C. Renaux, D. Flandre, Solid State Electron. 48 (12) (2004) 2263–2270. [8] E. Arnold, J. Electrochem. Soc. 141 (7) (1994) 1983–1988. [9] E. Arnold, H. Pein, and S.P. Herko, Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices, Technical Digest, International Electron Devices Meeting, IEDM'94, 1994, pp. 813–816. [10] A.A. Orouji, M. Rahimian, Phys. E Low-Dimens. Syst. Nanostruct. 44 (1) (2011) 333–338. [11] I.J. Kim, S. Matsumoto, T. Sakai, T. Yachi, IEEE Electron. Device Lett. 15 (5) (1994) 148–150. [12] A.A. Orouji, H.A. Moghadam, A. Dideban, Phys. E Low-Dimens. Syst. Nanostruct. 43 (1) (2010) 498–502. [13] A.A. Orouji, M. Mehrad, Superlattices Microstruct. 51 (3) (2012) 412–420. [14] D. Xu, X. Cheng, Y. Yu, Z. Wang, D. Cao, C. Xia, L. Liu, S. Trellenkamp, S. Mantl, Q.-T. Zhao, Microelectron. Eng. 122 (2014) 29–32. [15] Device Simulator ATLAS, Silvaco Int., Santa Clara, CA, 2012. [16] A.A. Orouji, M. Mehrad, Superlattices Microstruct. 72 (2014) 336–343. [17] A.A. Orouji, S. Sharbati, M. Fathipour, Device Mater. Reliab. IEEE Trans. 9 (3) (2009) 449–453. [18] A.A. Orouji, A. Pak, Mater. Sci. Semicond. Process. 34 (2015) 230–235. [19] M. Mehrad, A.A. Orouji, Mater. Sci. Semicond. Process. 16 (6) (2013) 1977–1981. [20] S.J. Mahabadi, A.A. Orouji, P. Keshavarzi, H.A. Moghadam, Semicond. Sci. Technol. 26 (9) (2011) 095005.
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp
A novel LDMOS structure using P-trench for high performance applications Ali A. Orouji n, Hojjat Allah Mansoori, A. Dideban, Hadi Shahnazarisani Electrical and Computer Engineering Department, Semnan University, Semnan, IRAN
a r t i c l e in f o
Keywords: LDMOS Silicon on insulator Trench 2-D device simulation.
abstract In this paper, we propose a new structure of silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) field effect transistors to improve the device performance. In the proposed structure, a trench is created in the buried oxide under the drift and drain regions and filled with p-type Si. We called the proposed structure as P-trench SOI-LDMOS (PT-LDMOS). Our simulations with two dimensional ATLAS simulator shows the unique features exhibited by the proposed structure in comparison with a conventional SOI-LDMOS (C-LDMOS). In the PT-LDMOS, the electric field is modified by producing a new additional peak at the electric field distribution, reducing the magnitude of electric field peak near the gate edge, removing of electric field crowding near the drift and drain junction at the bottom surface of the silicon layer, and making the surface electric field distribution more smooth. We optimize the doping concentration and the dimensions of the P-trench in the PT-LDMOS structure. Hence, the results illustrate the benefits of high performance PT-LDMOS over conventional one and expand the application of SOI-LDMOSs to high voltage. & 2015 Elsevier Ltd. All rights reserved.
1. Introduction Due to the significant advantages of lateral double diffused MOSFET (LDMOS) structure compared to traditional structures including, high compatibility for integration into modern BiCMOS power technologies, high power gain and efficiency, and low cost, this structure has been extensively utilized in intelligent power integrated circuits [1–4]. On the other hand, by considering the numerous benefits that is provided by silicon on insulator (SOI) technology such as ideal dielectric isolation, compactness, high speed, high temperature capability, and low loss, there is a great interest in applying these structures for production of high-voltage lateral devices [5–8].
n
Corresponding author. Tel.: þ982333654100, Fax: þ982333631623. E-mail address: [email protected] (A.A. Orouji).
http://dx.doi.org/10.1016/j.mssp.2015.05.063 1369-8001/& 2015 Elsevier Ltd. All rights reserved.
In SOI structure for power devices due to the existence of buried oxide layer, two issues have attracted the attention of self-heating effect (SHE) and low breakdown voltage [9–11]. In recent years, numerous schemes have been proposed for SOI-LDMOS to improve the performance of the device and solve these problems [12–14]. In this paper a new structure is presented for LDMOS devices to overcome the low breakdown voltage problem. The proposed structure enhances the breakdown voltage by applying a P-trench that is placed under the drift and drain regions. We called the proposed structure as P-trench SOILDMOS (PT-LDMOS). In this work, it will be illustrated that the electric field of the proposed structure is modified by producing an additional electric field peak, reducing the peak of electric field near the gate edge, and removing the electric field crowding near the drift and drain junction at the bottom surface of the silicon layer. Therefore, access to a more homogenous curve for the electric field distribution will be available in the PT-LDMOS structure and the
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
characteristics of conventional SOI-LDMOS (C-LDMOS) are significantly improved. So, first the proposed structure will be introduced and then we will present two-dimensional numerical simulation results [15] of the proposed structure and the influence of the P-trench will be compared with the C-LDMOS characteristics.
2. Device structure and simulation method Fig. 1 shows the schematic cross-sectional view of the proposed structure. As shown in the figure, a trench is created in the buried oxide at the drain side and filled with p-type doping to improve the breakdown voltage. The physical parameters used for simulating the PT-LDMOS structure are equivalent to the device parameters of the CLDMOS structure, but the C-LDMOS structure does not have the P-trench in the buried oxide. These values are specified in Table 1. Also the width of the device for both the structures is 1 μm. In order to investigate the effects of P-trench creating at PT-LDMOS performance the simulations carried out by using ATLAS 2-D device simulator. Various models including, “SRH”, “Auger”, “Analytic”, “Fldmob”, “Incomplete”, and “Impact Selb”are utilized in simulation to reach more actual results.
655
3. Discussion and results When the applied voltage between the drain and source for the C-LDMOS structure is equal to breakdown voltage, the height of the electrical field peaks is close to a critical amount at two regions; one at the gate edge side to drift region at the top surface of the silicon layer and the other one is placed near the drift and drain junction region at the bottom surface of the silicon layer [16] as illustrated in Fig. 2. The figure shows the 2-D electric field curves at the top surface and the bottom surface of the silicon layer for the C-LDMOS and PT-LDMOS structures, respectively. So, the high breakdown voltage can be provided by reducing the electric field peak in these regions. The P-trench that is used in the proposed structure leads to the displacement of electric field crowding near the drift/drain junction at the bottom surface of the silicon layer and putting it at the bottom surface of P-trench in the buried oxide, creating an additional peak at the electric field distribution, reducing the peak of electric field near the gate edge, modifying the electric field in the drift region and monotonous surface electric field distribution. Therefore, it is possible to achieve higher breakdown voltage (VBR) in the proposed structure
Fig. 1. Cross section of the PT-LDMOS structure.
Table 1 Device simulation parameters. Parameters
Symbol
Value
Unit
Length of drift region Length of buried oxide Thickness of buried oxide Height of P-trench Length of P-trench Doping of P-trench N þ Source/drain doping Doping of N drift region Doping of P-substrate layer Length of channel
Ldrift LBOX tBOX H L Nt Nn Nd Nsub Lchannel
10 14 1 0.9 4 1 1013 1 1019 2 1016 1 1013 2
mm mm mm mm mm cm 3 cm 3 cm 3 cm 3 mm
Fig. 2. Electric field distribution for the C-LDMOS and PT-LDMOS structures at (a) top surface and (b) bottom surface of the silicon layer.
656
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
[17–19]. In the PT-LDMOS structure the height of the common peak near the gate edge is reduced by producing a new peak at the drift region due to creating the P-trench, and more uniformity is observed in distribution curve of the electric field; on the other hand, since the area occupied underneath the electric field distribution curve is increased in the PT-LDMOS structure and this area is equal to the voltage magnitude that is applied to the device, a significant enhancement in the VBR of the proposed structure can be seen [20]. The VBR improves from 72 V for the C-LDMOS to
Fig. 5. The breakdown voltage versus the height of P-trench.
110 V for the PT-LDMOS. Therefore, a 52.77% increment in the VBR of the proposed structure is achieved, and the device can tolerate much higher voltages compared with the C-LDMOS structure. The equipotential contours of the C-LDMOS and PT-LDMOS structures at their VBR are shown in Fig. 3(a) and (b), respectively. The figure shows the extraordinary effect of the P-trench in distributing the potential lines toward the drain. The drain current (ID) of the PT-LDMOS and C-LDMOS structures are plotted in Fig. 4 for the various drain–source voltage from 0 V to 30 V. It can be seen that the ID improves from 120 μA for the conventional structure to 133 μA for the proposed structure, at VDS ¼30 V condition. Therefore, a significant increase in the ID of the PT-LDMOS structure is achieved in comparison with the C-LDMOS structure.
Fig. 3. Simulated equipotential contours at breakdown voltage for the (a) C-LDMOS and (b) PT-LDMOS.
4. Design considerations
Fig. 4. Drain current against drain–source voltage for C-LDMOS and PTLDMOS structures.
In order to achieve the best results and the importance of designing a high-power device, it is important to investigate the effect of height, length, and doping density of P-trench on the breakdown voltage. The initial values for height (H), length (L), and doping are determined as 0.9 μm, 4 μm, and 1 1013 cm 3, respectively. Fig. 5 shows the values of VBR for the PT-LDMOS according to the trench height. As the trench height increases, it can modulate more parts of the channel electric field distribution. But, if the trench height increases more than 0.9 μm the additional electric field peak in the drift region disappears, and the electric field peaks increase at the top surface near the gate and at the bottom surface near the drain. Therefore, if the trench height increases more than optimum value, the breakdown voltage is significantly reduced. The breakdown occurs at the bottom surface of the silicon layer near the drain region, so when the p-type trench region is situated under the drain, the VBR increases. When the trench length is beyond a certain amount, the p-type trench edge will be far away from the drain edge and gets
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
Fig. 6. Electric field distribution for the PT-LDMOS for different lengths of the P-trench more than 4 μm at (a) top surface and (b) bottom surface of the silicon layer.
closer to edge of the gate region, and the effect of P-trench on the reduction of the electric field crowding and the height of the additional peak at electric field distribution will be lower. Fig. 6 shows the electrical field distribution for PT-LDMOS by different lengths of P-trench (L¼ 4 μm, L ¼6 μm and L¼8 μm). It is clear from the figure that by increasing the length of P-trench the additional peak at the electric field distribution, far from the drain edge and the area underneath the electric field curve is reduced. Therefore, the breakdown voltage for the PT-LDMOS structure with P-trench more than 4 μm decreases. By reducing the length of P-trench to lower than 4 μm, the new peak that is added to the electric field in the drift region, moves to the drain side and the magnitude of this peak is increased. Although the magnitude of additional new peak is enhanced, the breakdown voltage decreases due to the reduction of area underneath the electric field curve, as shown in Fig. 7. The values of the VBR for PT-LDMOS structure with various P-trench lengths are plotted in Fig. 8. The doping density of trench significantly affects the device characteristics. By increasing the doping density of the P-trench to 1 1013 cm 3, the VBR of the PT-LDMOS
657
Fig. 7. Electric field distribution for the PT-LDMOS for different lengths of the P-trench lower than 4 μm at (a) top surface and (b) bottom surface of the silicon layer.
Fig. 8. The breakdown voltage against the length of P-trench.
increases, which can be seen in Fig. 9. When the P-trench doping density is higher than a certain amount the breakdown voltage decreases.
658
A.A. Orouji et al. / Materials Science in Semiconductor Processing 39 (2015) 654–658
conventional LDMOS (C-LDMOS). Also the driving current of the proposed structure has desirable improvement. References
Fig. 9. The breakdown voltage according to doping of P-trench.
5. Conclusion We proposed a new structure for SOI-LDMOSFET with a P-trench (PT-LDMOS) in the buried oxide at the drain side to achieve high blocking voltage. The P-trench in the proposed structure leads to displacement of the electric field crowding near the drift/drain junction at the bottom surface of the silicon layer and putting it at the bottom surface of the P-trench in the buried oxide. Also, by using P-trench an additional peak is created at electric field distribution, and peak of the electric field near the gate edge is reduced, therefore the electric field distribution in the drift region is modified and more uniform. Investigations by using two dimensional numerical simulations demonstrated that by applying the P-trench the breakdown voltage improved by 52.77% in comparison with a
[1] M. Zitouni, F. Morancho, P. Rossel, H. Tranduc, and J. Buxo, A new concept for the lateral DMOS transistor for smart power IC's, in: Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99, 1999, pp. 73–76. [2] C.W. Tang, K.Y. Tong, Solid State Electron. 46 (12) (2002) 2111–2115. [3] T.R. Efland, C.-Y. Tsai, and S. Pendharkar, Lateral thinking about power devices (LDMOS), Technical Digest, International Electron Devices Meeting. IEDM'98, 1998, pp. 679–682. [4] G. Cao, S.K. Manhas, E.S. Narayanan, M.M. De Souza, D. Hinchley, Electron Devices, IEEE Trans. 51 (8) (2004) 1296–1303. [5] A. Nakagawa, N. Yasuhara, Y. Baba, Electron Devices, IEEE Trans. 38 (7) (1991) 1650–1654. [6] J.G. Fiorenza, J.A. Del Alamo, Electron Devices, IEEE Trans. 49 (4) (2002) 687–692. [7] M. Bawedin, C. Renaux, D. Flandre, Solid State Electron. 48 (12) (2004) 2263–2270. [8] E. Arnold, J. Electrochem. Soc. 141 (7) (1994) 1983–1988. [9] E. Arnold, H. Pein, and S.P. Herko, Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices, Technical Digest, International Electron Devices Meeting, IEDM'94, 1994, pp. 813–816. [10] A.A. Orouji, M. Rahimian, Phys. E Low-Dimens. Syst. Nanostruct. 44 (1) (2011) 333–338. [11] I.J. Kim, S. Matsumoto, T. Sakai, T. Yachi, IEEE Electron. Device Lett. 15 (5) (1994) 148–150. [12] A.A. Orouji, H.A. Moghadam, A. Dideban, Phys. E Low-Dimens. Syst. Nanostruct. 43 (1) (2010) 498–502. [13] A.A. Orouji, M. Mehrad, Superlattices Microstruct. 51 (3) (2012) 412–420. [14] D. Xu, X. Cheng, Y. Yu, Z. Wang, D. Cao, C. Xia, L. Liu, S. Trellenkamp, S. Mantl, Q.-T. Zhao, Microelectron. Eng. 122 (2014) 29–32. [15] Device Simulator ATLAS, Silvaco Int., Santa Clara, CA, 2012. [16] A.A. Orouji, M. Mehrad, Superlattices Microstruct. 72 (2014) 336–343. [17] A.A. Orouji, S. Sharbati, M. Fathipour, Device Mater. Reliab. IEEE Trans. 9 (3) (2009) 449–453. [18] A.A. Orouji, A. Pak, Mater. Sci. Semicond. Process. 34 (2015) 230–235. [19] M. Mehrad, A.A. Orouji, Mater. Sci. Semicond. Process. 16 (6) (2013) 1977–1981. [20] S.J. Mahabadi, A.A. Orouji, P. Keshavarzi, H.A. Moghadam, Semicond. Sci. Technol. 26 (9) (2011) 095005.