- Email: [email protected]
Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage
Superlattices and Microstructures 91 (2016) 193e200
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage Mahsa Mehrad School of Engineering, Damghan University, Damghan, Iran
a r t i c l e i n f o
a b s t r a c t
Article history: Received 23 November 2015 Received in revised form 25 December 2015 Accepted 26 December 2015 Available online 29 December 2015
A new device structure for high breakdown voltage and low maximum lattice temperature of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using a Si3N4 trench region with open windows made by silicon in it. In the conventional structure, a trench oxide was used to have high breakdown voltage that causes high lattice temperature. So, replacing Si3N4 material is suitable way to have a more reliable device. The proposed periodic trench region in LDMOS transistor (PTR-LDMOS) has periodic open windows to increase the additional peaks in the electric field profile and increase the breakdown voltage. Also, the simulation with two-dimensional ATLAS simulator shows that reduced main electric field peaks cause low electron temperature that enhances the reliability of the proposed structure. © 2015 Elsevier Ltd. All rights reserved.
Keywords: LDMOS Breakdown voltage Lattice temperature Reliability
1. Introduction Metal Oxide Semiconductor Field Effect Transistors (MOSFET) play a great role in electronic industry development [1e8]. During last decades, a lot of researchers have attempted to increase the quality of this important kind of transistors [9e11]. Silicon On Insulator technology (SOI) is one of the results of these attempts which leads to more reliable MOSFET [12e14]. SOI MOSFET reduces the capacitances between Source-bulk and drain-bulk, leakage current, latch up phenomena, and power consumption [15e16]. The need for having high breakdown voltage in power applications is a reason for emerging Lateral Double Diffused Metal Oxide Semiconductors (LDMOS) [17e19]. The breakdown voltage increases by inserting a trench oxide in the drift region of LDMOS transistors which is called trench oxide LDMOS [20e21]. However, in this structure, the thermal conductivity of oxide is poor and leads to increasing the maximum lattice temperature of the device. Therefore, when the drain voltage increases, the temperature rises in the drift region and the oxide acts as a barrier. In this case, the device gets hot and some parameters may be destroyed. Some efforts have been accomplished in last years to overcome this effect [22e24]. In this paper, a new structure for trench oxide LDMOS is proposed to improve the lattice temperature with higher breakdown voltage. So, some great changes are considered in the new structure that makes it more reliable than conventional trench oxide LDMOS. In the new structure, Si3N4 layer is considered in the drift region instead of SiO2 which has better thermal conductivity. Moreover, this layer is periodically etched in some parts and filled with silicon. So, the new structure is called Periodic Trench region LDMOS (PTR-LDMOS). The simulation with two dimensional ATLAS simulator shows that PTRLDMOS can effectively reduce the lattice temperature because of better thermal conductivity of Si3N4 layer [25]. Moreover, the
E-mail address: [email protected]. http://dx.doi.org/10.1016/j.spmi.2015.12.041 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
194
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
electric field gets more uniform and the breakdown voltage increases [26e28]. Therefore, PTR-LDMOS is more reliable than conventional one for high temperature applications. The rest of the paper is organized as follows. In Section 2, the new structure is introduced. The simulation results and design consideration are presented in Section 3. Finally the paper is concluded in Section 4.
2. Device structure A new structure for trench oxide LDMOS is proposed in this section which can reach to an improved lattice temperature and higher breakdown voltage. The schematic cross-section of the new structure which is called PTR-LDMOS is illustrated in Fig. 1(a) and the conventional one (C-LDMOS) is depicted in Fig. 1(b). As these figures show, the trench oxide is replaced with Si3N4 in the PTR-LDMOS because of better thermal conductivity. Moreover, some parts of Si3N4 are periodically etched and filled with silicon which leads to more uniform electric field. The PTR-LDMOS parameters that are used in ATLAS simulations are shown in Table 1. Numerical simulations were performed by solving Poisson and drift/diffusion equations plus SHR (ShockleyeHalleRead) and Auger generation/recombination and impact ionization processes. These simulations methods allow taking into account carrier velocity saturation, carrierecarrier scattering in the high doping concentration, dependence of mobility on temperature and vertical electric influence [25]. Also, in the simulation, the boundary condition of the heat flow is fixed at 300 K at the bottom interface of the silicon substrate. However thermo contact is used for considering temperature variation and selfheating effect.
Gate Source
x A
y
N Poly
N+
Drain
LTrench +
LOW
LTW DTrench
P
N+
A’
N+
A’
N-Drift BOX
P-Substrate
(a) Gate Source
x y
A
N+Poly
N+
P
N-Drift BOX
P-Substrate
(b)
Si3N4
SiO2
Poly Si
Si
Fig. 1. A schematic cross-sectional view of (a) periodic trench region LDMOS (PTR-LDMOS) structure and (b) conventional LDMOS transistor (C-LDMOS) implemented in ATLAS simulator.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
195
Table 1 Typical parameters for PTR-LDMOS used in ATLAS simulations. Device Parameters
Value
Channel length Drift region length Silicon thickness Gate oxide thickness (tox) Trench length (LTrench) Trench depth (DTrench) Length of open window in trench region (LOW) Length of trench window (LTW) Buried oxide thickness Drift region doping concentration Channel doping concentration Source/drain doping concentration Substrate doping concentration
3 mm 11 mm 0.6 mm 50 nm 9 mm 0.4 mm 1 mm 1 mm 0.3 mm 5 1015 1 1017 1 1019 5 1013
cm3 cm3 cm3 cm3
3. Results and discussion This section presents comparing the results of simulated PTR-LDMOS with C-LDMOS. So, the electrical parameters and design consideration are discussed, respectively.
3.1. Electrical parameters In this section the electrical parameters of PTR-LDMOS in comparison to C-LDMOS transistor are evaluated. In the proposed structure, SiO2 layer is replaced with Si3N4 layer and silicon windows. Si3N4 in PTR-LDMOS with more conductivity than oxide causes the heat to conduct easily. So, the lattice temperature can effectively reduce. Fig. 2(a) shows the maximum lattice 0 temperature versus lateral position in drift region for both PTR-LDMOS and C-LDMOS along cut line AA’ (cut line AA is shown in Fig. 1 which is located at 50 nm from the surface of the drift region). As it is obvious, the maximum lattice temperature of PTR-LDMOS along drift region is very smaller than C-LDMOS which makes it more reliable in the case of temperature. In Fig. 2(b), the lattice temperature versus drain voltage is illustrated for the both PTR-LDMOS and C-LDMOS. The figure shows that the lattice temperature increases when the drain voltage enhances but the increasing rate for PTR-LDMOS is very smaller than C-LDMOS. It is clear that the lattice temperature is approximately fixed for the proposed structure when the drain voltage increases. This is because of the Si3N4 layer in PTR-LDMOS which is replaced with the trench oxide. As it is clear, the thermal conductivity of Si3N4 is more than silicon dioxide which can effectively conduct the heat. The lattice temperature is very important parameter since it increases by the drain voltage. In this case the mobility decreases and consequently the drain current reduces at the high drain biases. In Fig. 3, the electron mobility along the channel is depicted for PTR-LDMOS and C-LDMOS structures. As it is clear, the mobility for PTR-LDMOS is higher than C-LDMOS because of higher thermal conductivity of Si3N4 than oxide. When the temperature increases, mobility decreases which is because of scattering effect. So, using the materials with higher thermal conductivity causes higher mobility. Obtaining high breakdown voltage is objective for LDMOS structures sine for the applied voltages bigger than breakdown, the drain current increases suddenly and the normal behavior is violated [29]. The breakdown behavior occurs at high electric field. So, reducing the maximum values of electric field causes high breakdown voltage. One way for reducing the maximum values of electric field is creating new peaks in electric field profile [30]. These new peaks modify the electric field profile and leads to reducing the height of maximum electric field. In Fig. 4 horizontal electric field versus lateral position is illustrated for both PTR-LDMOS and C-LDMOS transistors. This figure shows that there are five peaks in the electric profile of C-LDMOS. Three of them have bigger values and are very important (which are called main peaks) since the breakdown behavior occurs at the maximum electric field. In PTR-LDMOS, new peaks appear because of considering periodic silicon windows in the trench. Appearing the new peaks decreases the height of main peaks and consequently the breakdown voltage increases. Therefore, PTR-LDMOS has more uniform electric field profile and higher breakdown voltage than C-LDMOS. The breakdown voltages versus drift length are depicted in Fig. 5 for the proposed structure and conventional one. The figure shows that the breakdown voltage for PTR-LDMOS is about 450 V in drift length of 11 mm while it is about 170 V for CLDMOS. Another important parameter for introducing PTR-LDMOS is electron temperature. There is a relation between electron temperature and device reliability. In order to increase the reliability of the device, the electron temperature should be reduced. The electron temperatures of the PTR-LDMOS and C-LDMOS are measured in x ¼ 10 mm and y ¼ 0.5 mm. In the proposed structure, electrons have lower temperature in the different drift lengths as it is shown in Fig. 6. This behavior is due to the replacing periodic Si3N4 trench region instead of trench oxide that reduces the height of main peaks in the electric field profile. So, the PTR-LDMOS structure acts as a reliable device in comparison to the C-LDMOS transistor.
196
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
Maximum Lattice Temperature [K]
(a)
900
800
700
600
PTR-LDMOS C-LDMOS
500
VG= 8 V VD= 15 V
400
300 0
2
4
6
8
10
12
Lateral Position in Drift Region [μm]
(b)
Lattice Temperature [K]
630
PTR-LDMOS C-LDMOS
560
490
420
VG= 10 V
350
280 0
2
4
6
8
10
Drain Voltage [V] Fig. 2. (a) Maximum lattice temperature in the drift region of the proposed structure and conventional transistor. (b) Lattice temperature versus drain voltage at VG ¼ 10 V is compared between PTR-LDMOS and C-LDMOS.
600
PTR-LDMOS C-LDMOS
2
Electron Mobility [cm /Vs]
500
400
300
200
VG= 8 V VD= 15 V
100 0
1
2
3
4
5
Lateral Position In Channel [μm] Fig. 3. Variation of electron mobility in the lateral position in the channel for PTR-LDMOS and C-LDMOS.
Reducing silicon thickness is an important trend in semiconductor devices due to the reduction of kink effect, increasing carrier mobility and elimination of punch-through [15]. In other words thin silicon thickness causes high density and speed in MOSFETs. Fig. 7 compares the breakdown voltage versus silicon thickness in the PTR-LDMOS and C-LDMOS transistors. As can be seen from the figure, the maximum breakdown occurs when the thickness of silicon is 0.6 mm. Also, the proposed structure has higher breakdown voltage in this thickness.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
197
Fig. 4. Horizontal electric field profiles for the PTR-LDMOS and C-LDMOS structures along cut line AA’.
Breakdown Voltage [V]
600
500
400
PTR-LDMOS C-LDMOS
300
200
100 6
8
10
12
14
16
18
20
22
N-Drift Length [μm] Fig. 5. The breakdown voltage of proposed structure and C-LDMOS structure is compared in different drift length.
PTR-LDMOS C-LDMOS
Electron Temperature [K]
3000
2400
1800
1200
600 12
14
16
18
20
22
24
Drift Length [μm] Fig. 6. Comparison of electron temperature versus drift length for the PTR-LDMOS and C-LDMOS transistor at VD ¼ 5 V and VG ¼ 1 V.
198
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
3.2. Design consideration Two factors cause low lattice temperature in the PTR-LDMOS. One is replacing Si3N4 in the trench oxide, and the other is considering periodic silicon windows in the trench oxide. In order to have the best possible behavior of the proposed structure, the lengths and depths of Si3N4 trench and silicon windows should be optimized. In Fig. 8 the lattice temperature is plotted in different silicon window lengths at x ¼ 10 mm and y ¼ 0.5 mm. It is clear that Low ¼ 1 mm has an acceptable lattice temperature value and chooses for the device simulation. The other parameter that should be optimized is the length of trench window (it is shown in Fig. 1). In Fig. 9 the breakdown voltage as a function of LOW/LTW is plotted for the PTR-LDMOS structure. Increasing LOW/LTW causes high breakdown voltage until the LOW/LTW reaches about value 1. After this value, increasing LOW/LTW reduces the breakdown voltage. This reduction is due to the electric field. It means by increasing the length of open window, the numbers of trench windows reduce which decreases the numbers of additional peaks in the electric field profile and reduces the breakdown voltage. So, LOW/LTW ¼ 1 is suitable to have high breakdown voltage. The optimum length and depth of trench Si3N4 is determined in Fig. 10 and Fig. 11. In Fig. 10, the maximum temperature in the drift region and the breakdown voltages is shown for different trench lengths. It is clear that longer trench increases the maximum temperature in the drift region. But, in another point of view, increasing the trench length causes higher breakdown voltage. In this case the Ltrench ¼ 9 mm is chosen to have an acceptable temperature in the drift region and high breakdown voltage. Drain current is plotted in different trench depths in Fig. 11. The trench in the drift region acts as a barrier for the electrons to flow. Increasing the depth of trench in the drift reduces the drain current as it is shown in the figure. But, increased trench depth causes high breakdown voltage. So, a trade off should be considered to have suitable drain current and breakdown voltage. Dtrench ¼ 0.4 is an acceptable value for the proposed PTR-LDMOS transistor to have high drain current and breakdown voltage.
Breakdown Voltage [V]
420 350 280
PTR-LDMOS C-LDMOS
210 140
70 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Silicon Layer Thickness [μm] Fig. 7. Dependence of the breakdown voltage on the silicon thickness in PTR-LDMOS transistor and C-LDMOS.
Lattice Temperature [K]
480
450
420
PTR-LDMOS
390
360
330
LDrift= 11 μm 0.2
0.4
0.6
0.8
1.0
1.2
Length of Open Window (LOW) [μm] Fig. 8. Lattice temperature as a function of open window length for PTR-LDMOS structure.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
199
450
PTR-LDMOS
Breakdown Voltage [V]
420
390
360
330
300 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Ratio of LOW to LTW(LOW/LTW)
Maximum Temperature in the Drift Region [K]
Fig. 9. Breakdown voltage of PTR-LDMOS versus the ratio of LOW/LTW.
BV=821 V 500
PTR-LDMOS
450
BV=764 V BV=659 V
BV=426 V
400
BV=312 V 350
LDrift= 20 μm 6
8
10
12
14
16
Trench Length (LTrench) [μm]
Fig. 10. Comparison of maximum temperature in the drift region and breakdown voltage of PTR-LDMOS transistor in different trench length.
Fig. 11. Dependence of drain current on the trench depth in PTR-LDMOS transistor.
4. Conclusion A new reliable high breakdown voltage LDMOS is reported in this paper. In the new transistor, a Si3N4 trench region is considered in the drift region and periodic open window with silicon material is inserted in this trench. Thermal conductivity of Si3N4 in the trench region of proposed PTR-LDMOS is better than silicon dioxide in the trench oxide of conventional LDMOS
200
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
(C-LDMOS). So, lattice temperature reduces significantly. Also, periodic silicon windows cause additional peaks in the electric profile which reduces the height of main peaks. The simulation with ATLAS simulator shows high breakdown voltage and reduced electron temperature of the proposed LDMOS structure. References [1] A.A. Orouji, M. Mehrad, A new rounded edge fin field effect transistor for improving self-heating effects, Jpn. J. Appl. Phys. 50 (2011) 124303e124309. [2] S.E. Jamali Mahabadi, Ali A. Orouji, Parviz Keshavarzi, Saba Rajabi, Hamid Amini Moghadam, Maryam Iranian Pour Haghighi, A novel step buried oxide partial SOI LDMOSFET with triple drift layer, in: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), India, 2011, pp. 174e177. [3] M. Saremi, A.A. Kusha, S. Mohammadi, Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits, Microelectron. Eng. 95 (2012) 74e82. [4] V. Fathipour, A. Mojab, M.A. Malakoutian, S. Fathipour, M. Fathipour, The impact of process parameter variations on the electrical characteristics of a RESURF LDMOS and its compact modeling, in: IEEE International Semiconductor Device Research Symposium (ISDRS), College Park, MD, Dec, 2011. [5] M. Saremi, B. Ebrahimi, A.A. Kusha, Process variation study of ground plane SOI MOSFET, in: 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010, pp. 66e69. [6] Hamid Amini Moghadam, S.E. Jamali Mahabadi, Saba Rajabi, Combination of a 4H-SiC MESFET with a 4H-SiC MOSFET to realize a high voltage MOSFET, in: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), India, 2011, pp. 172e173. [7] M. Saremi, B. Ebrahimi, A.A. Kusha, Ground plane SOI MOSFET based SRAM with consideration of process variation, in: Proc. 2010 International Conference on Electron Devices & Solid-state Circuits (EDSSC), 2010, pp. 1e4. [8] Hamid Amini Moghadam, Ali A. Orouji, S.E. Jamali Mahabadi, Employing reduced surface field technique by a P-type region in 4H-SiC metal semiconductor field effect transistors for increasing breakdown voltage, Int. J. Numer. Model. Electron. 26 (no. 2) (2013) 103e111. [9] S.E. Jamali Mahabadi, Hamid Amini Moghadam, Comprehensive study of a 4HeSiC MESeMOSFET, Phys. E Low Dimens. Syst. Nanostruct. 74 (2015) 25e29. [10] H. Aghababa, B. Ebrahimi, M. Saremi, V. Moalemi, B. Forouzandeh, G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems, IEICE Electron. Express 9 (2012) 881e887. [11] M.A. Malakoutian, V. Fathipour, M. Fathipour, A. Mojab, M.M. Allame, M. Moradinasab, The impact of process parameters on the output characteristics of an LDMOS Device, World Acad. Sci. Eng. Technol. 4 (No. 9) (Sep. 2010). [12] E. Arnold, Silicon-on-insulator devices for high voltage and power IC applications, J. Electrochem. Soc. 141 (1994) 1983. [13] S. Cristoloveanu, Silicon on insulator technologies and devices: from present to future, Solid State Electron. 45 (2001) 1403e1411. [14] J.P. Colinge, Silicon-on-insulator Technology: Materials to VLSI, third ed., Kluwer Academic Publishers, 2004. [15] P. Antognetti, Power Integrated Circuits: Physics, Design and Applications, McGraw-Hill, 1986. [16] H. Lu, C. Andre, T. Salama, A 2 GHz, 60 V-Class, SOI power LDMOSFET for base station applications, in: Proc. IEEE 15th Int. Symp. ISPSD, 2003, pp. 270e273. [17] A.A. Orouji, M. Mehrad, Positive charges at buried oxide interface of resurf: an analytical model for the breakdown voltage, Superlattices Microstruct. 72 (2014) 336e343. [18] A.A. Orouji, M. Mehrad, The best control of parasitic BJT effect in SOI-LDMOS with SiGe window under channel, IEEE Trans. Electron. Devices 59 (2012) 419e425. [19] S.E.J. Mahabadi, A.A. Orouji, P. Keshavarzi, H.A. Moghadam, A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage, Semicond. Sci. Technol. 26 (2011) 095005. [20] A.A. Orouji, M. Mehrad, Breakdown voltage improvement of LDMOSs by charge balancing: an inserted p-layer in trench oxide (IPT-LDMOS), Superlattices Microstruct. 51 (2012) 412e420. [21] S.E.J. Mahabadi, S. Rajabi, J. Loiacono, A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement, Superlattices Microstruct. 85 (2015) 872e879. [22] M. Mehrad, A.A. Orouji, A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a u-shape buried oxide feature, Mater. Sci. Semicond. Process. 16 (2013) 1977e1981. [23] M. Mehrad, Omega shape channel LDMOS: A novel structure for high voltage applications, Phys. E Low Dimens. Syst. Nanostruct. 75 (2016) 196e201. [24] M. Zareiee, A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel, Superlattices Microstruct. 88 (2015) 254e261. [25] Atlas User's Manual, Silvaco International, Santa Clara, CA, 2007. [26] M. Mehrad, A.A. Orouji, New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using SiGe zone in drift region, Curr. Appl. Phys. 12 (2012) 1340e1344. [27] S.E. Jamali Mahabadi, Ali A. Orouji, Hamid Amini Moghadam, P. Keshavarzi, A new method for improving breakdown voltage in PSOI MOSFETs using variable drift region doping concentration, in: IEEE International Conference on Computer Science and Automation Engineering (CSAE) China, vol. 3, 2011, pp. 57e60. [28] S.E. Jamali Mahabadi, Upper drift region double step partial SOI LDMOSFET: a novel device for enhancing breakdown voltage and output characteristics, Superlattices Microstruct. 89 (2016) 345e354. [29] M. Mehrad, Thin layer oxide in the drift region of laterally double-diffused metal oxide semiconductor on silicon-on-insulator: a novel device structure enabling reliable high-temperature power transistors, Mater. Sci. Semicond. Process. 30 (2015) 599e604. [30] M. Saremi, B. Ebrahimi, A.A. Kusha, S. Mohammadi, A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement, Microelectron. Reliab. 51 (2011) 2069e2076.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage Mahsa Mehrad School of Engineering, Damghan University, Damghan, Iran
a r t i c l e i n f o
a b s t r a c t
Article history: Received 23 November 2015 Received in revised form 25 December 2015 Accepted 26 December 2015 Available online 29 December 2015
A new device structure for high breakdown voltage and low maximum lattice temperature of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using a Si3N4 trench region with open windows made by silicon in it. In the conventional structure, a trench oxide was used to have high breakdown voltage that causes high lattice temperature. So, replacing Si3N4 material is suitable way to have a more reliable device. The proposed periodic trench region in LDMOS transistor (PTR-LDMOS) has periodic open windows to increase the additional peaks in the electric field profile and increase the breakdown voltage. Also, the simulation with two-dimensional ATLAS simulator shows that reduced main electric field peaks cause low electron temperature that enhances the reliability of the proposed structure. © 2015 Elsevier Ltd. All rights reserved.
Keywords: LDMOS Breakdown voltage Lattice temperature Reliability
1. Introduction Metal Oxide Semiconductor Field Effect Transistors (MOSFET) play a great role in electronic industry development [1e8]. During last decades, a lot of researchers have attempted to increase the quality of this important kind of transistors [9e11]. Silicon On Insulator technology (SOI) is one of the results of these attempts which leads to more reliable MOSFET [12e14]. SOI MOSFET reduces the capacitances between Source-bulk and drain-bulk, leakage current, latch up phenomena, and power consumption [15e16]. The need for having high breakdown voltage in power applications is a reason for emerging Lateral Double Diffused Metal Oxide Semiconductors (LDMOS) [17e19]. The breakdown voltage increases by inserting a trench oxide in the drift region of LDMOS transistors which is called trench oxide LDMOS [20e21]. However, in this structure, the thermal conductivity of oxide is poor and leads to increasing the maximum lattice temperature of the device. Therefore, when the drain voltage increases, the temperature rises in the drift region and the oxide acts as a barrier. In this case, the device gets hot and some parameters may be destroyed. Some efforts have been accomplished in last years to overcome this effect [22e24]. In this paper, a new structure for trench oxide LDMOS is proposed to improve the lattice temperature with higher breakdown voltage. So, some great changes are considered in the new structure that makes it more reliable than conventional trench oxide LDMOS. In the new structure, Si3N4 layer is considered in the drift region instead of SiO2 which has better thermal conductivity. Moreover, this layer is periodically etched in some parts and filled with silicon. So, the new structure is called Periodic Trench region LDMOS (PTR-LDMOS). The simulation with two dimensional ATLAS simulator shows that PTRLDMOS can effectively reduce the lattice temperature because of better thermal conductivity of Si3N4 layer [25]. Moreover, the
E-mail address: [email protected]. http://dx.doi.org/10.1016/j.spmi.2015.12.041 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
194
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
electric field gets more uniform and the breakdown voltage increases [26e28]. Therefore, PTR-LDMOS is more reliable than conventional one for high temperature applications. The rest of the paper is organized as follows. In Section 2, the new structure is introduced. The simulation results and design consideration are presented in Section 3. Finally the paper is concluded in Section 4.
2. Device structure A new structure for trench oxide LDMOS is proposed in this section which can reach to an improved lattice temperature and higher breakdown voltage. The schematic cross-section of the new structure which is called PTR-LDMOS is illustrated in Fig. 1(a) and the conventional one (C-LDMOS) is depicted in Fig. 1(b). As these figures show, the trench oxide is replaced with Si3N4 in the PTR-LDMOS because of better thermal conductivity. Moreover, some parts of Si3N4 are periodically etched and filled with silicon which leads to more uniform electric field. The PTR-LDMOS parameters that are used in ATLAS simulations are shown in Table 1. Numerical simulations were performed by solving Poisson and drift/diffusion equations plus SHR (ShockleyeHalleRead) and Auger generation/recombination and impact ionization processes. These simulations methods allow taking into account carrier velocity saturation, carrierecarrier scattering in the high doping concentration, dependence of mobility on temperature and vertical electric influence [25]. Also, in the simulation, the boundary condition of the heat flow is fixed at 300 K at the bottom interface of the silicon substrate. However thermo contact is used for considering temperature variation and selfheating effect.
Gate Source
x A
y
N Poly
N+
Drain
LTrench +
LOW
LTW DTrench
P
N+
A’
N+
A’
N-Drift BOX
P-Substrate
(a) Gate Source
x y
A
N+Poly
N+
P
N-Drift BOX
P-Substrate
(b)
Si3N4
SiO2
Poly Si
Si
Fig. 1. A schematic cross-sectional view of (a) periodic trench region LDMOS (PTR-LDMOS) structure and (b) conventional LDMOS transistor (C-LDMOS) implemented in ATLAS simulator.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
195
Table 1 Typical parameters for PTR-LDMOS used in ATLAS simulations. Device Parameters
Value
Channel length Drift region length Silicon thickness Gate oxide thickness (tox) Trench length (LTrench) Trench depth (DTrench) Length of open window in trench region (LOW) Length of trench window (LTW) Buried oxide thickness Drift region doping concentration Channel doping concentration Source/drain doping concentration Substrate doping concentration
3 mm 11 mm 0.6 mm 50 nm 9 mm 0.4 mm 1 mm 1 mm 0.3 mm 5 1015 1 1017 1 1019 5 1013
cm3 cm3 cm3 cm3
3. Results and discussion This section presents comparing the results of simulated PTR-LDMOS with C-LDMOS. So, the electrical parameters and design consideration are discussed, respectively.
3.1. Electrical parameters In this section the electrical parameters of PTR-LDMOS in comparison to C-LDMOS transistor are evaluated. In the proposed structure, SiO2 layer is replaced with Si3N4 layer and silicon windows. Si3N4 in PTR-LDMOS with more conductivity than oxide causes the heat to conduct easily. So, the lattice temperature can effectively reduce. Fig. 2(a) shows the maximum lattice 0 temperature versus lateral position in drift region for both PTR-LDMOS and C-LDMOS along cut line AA’ (cut line AA is shown in Fig. 1 which is located at 50 nm from the surface of the drift region). As it is obvious, the maximum lattice temperature of PTR-LDMOS along drift region is very smaller than C-LDMOS which makes it more reliable in the case of temperature. In Fig. 2(b), the lattice temperature versus drain voltage is illustrated for the both PTR-LDMOS and C-LDMOS. The figure shows that the lattice temperature increases when the drain voltage enhances but the increasing rate for PTR-LDMOS is very smaller than C-LDMOS. It is clear that the lattice temperature is approximately fixed for the proposed structure when the drain voltage increases. This is because of the Si3N4 layer in PTR-LDMOS which is replaced with the trench oxide. As it is clear, the thermal conductivity of Si3N4 is more than silicon dioxide which can effectively conduct the heat. The lattice temperature is very important parameter since it increases by the drain voltage. In this case the mobility decreases and consequently the drain current reduces at the high drain biases. In Fig. 3, the electron mobility along the channel is depicted for PTR-LDMOS and C-LDMOS structures. As it is clear, the mobility for PTR-LDMOS is higher than C-LDMOS because of higher thermal conductivity of Si3N4 than oxide. When the temperature increases, mobility decreases which is because of scattering effect. So, using the materials with higher thermal conductivity causes higher mobility. Obtaining high breakdown voltage is objective for LDMOS structures sine for the applied voltages bigger than breakdown, the drain current increases suddenly and the normal behavior is violated [29]. The breakdown behavior occurs at high electric field. So, reducing the maximum values of electric field causes high breakdown voltage. One way for reducing the maximum values of electric field is creating new peaks in electric field profile [30]. These new peaks modify the electric field profile and leads to reducing the height of maximum electric field. In Fig. 4 horizontal electric field versus lateral position is illustrated for both PTR-LDMOS and C-LDMOS transistors. This figure shows that there are five peaks in the electric profile of C-LDMOS. Three of them have bigger values and are very important (which are called main peaks) since the breakdown behavior occurs at the maximum electric field. In PTR-LDMOS, new peaks appear because of considering periodic silicon windows in the trench. Appearing the new peaks decreases the height of main peaks and consequently the breakdown voltage increases. Therefore, PTR-LDMOS has more uniform electric field profile and higher breakdown voltage than C-LDMOS. The breakdown voltages versus drift length are depicted in Fig. 5 for the proposed structure and conventional one. The figure shows that the breakdown voltage for PTR-LDMOS is about 450 V in drift length of 11 mm while it is about 170 V for CLDMOS. Another important parameter for introducing PTR-LDMOS is electron temperature. There is a relation between electron temperature and device reliability. In order to increase the reliability of the device, the electron temperature should be reduced. The electron temperatures of the PTR-LDMOS and C-LDMOS are measured in x ¼ 10 mm and y ¼ 0.5 mm. In the proposed structure, electrons have lower temperature in the different drift lengths as it is shown in Fig. 6. This behavior is due to the replacing periodic Si3N4 trench region instead of trench oxide that reduces the height of main peaks in the electric field profile. So, the PTR-LDMOS structure acts as a reliable device in comparison to the C-LDMOS transistor.
196
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
Maximum Lattice Temperature [K]
(a)
900
800
700
600
PTR-LDMOS C-LDMOS
500
VG= 8 V VD= 15 V
400
300 0
2
4
6
8
10
12
Lateral Position in Drift Region [μm]
(b)
Lattice Temperature [K]
630
PTR-LDMOS C-LDMOS
560
490
420
VG= 10 V
350
280 0
2
4
6
8
10
Drain Voltage [V] Fig. 2. (a) Maximum lattice temperature in the drift region of the proposed structure and conventional transistor. (b) Lattice temperature versus drain voltage at VG ¼ 10 V is compared between PTR-LDMOS and C-LDMOS.
600
PTR-LDMOS C-LDMOS
2
Electron Mobility [cm /Vs]
500
400
300
200
VG= 8 V VD= 15 V
100 0
1
2
3
4
5
Lateral Position In Channel [μm] Fig. 3. Variation of electron mobility in the lateral position in the channel for PTR-LDMOS and C-LDMOS.
Reducing silicon thickness is an important trend in semiconductor devices due to the reduction of kink effect, increasing carrier mobility and elimination of punch-through [15]. In other words thin silicon thickness causes high density and speed in MOSFETs. Fig. 7 compares the breakdown voltage versus silicon thickness in the PTR-LDMOS and C-LDMOS transistors. As can be seen from the figure, the maximum breakdown occurs when the thickness of silicon is 0.6 mm. Also, the proposed structure has higher breakdown voltage in this thickness.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
197
Fig. 4. Horizontal electric field profiles for the PTR-LDMOS and C-LDMOS structures along cut line AA’.
Breakdown Voltage [V]
600
500
400
PTR-LDMOS C-LDMOS
300
200
100 6
8
10
12
14
16
18
20
22
N-Drift Length [μm] Fig. 5. The breakdown voltage of proposed structure and C-LDMOS structure is compared in different drift length.
PTR-LDMOS C-LDMOS
Electron Temperature [K]
3000
2400
1800
1200
600 12
14
16
18
20
22
24
Drift Length [μm] Fig. 6. Comparison of electron temperature versus drift length for the PTR-LDMOS and C-LDMOS transistor at VD ¼ 5 V and VG ¼ 1 V.
198
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
3.2. Design consideration Two factors cause low lattice temperature in the PTR-LDMOS. One is replacing Si3N4 in the trench oxide, and the other is considering periodic silicon windows in the trench oxide. In order to have the best possible behavior of the proposed structure, the lengths and depths of Si3N4 trench and silicon windows should be optimized. In Fig. 8 the lattice temperature is plotted in different silicon window lengths at x ¼ 10 mm and y ¼ 0.5 mm. It is clear that Low ¼ 1 mm has an acceptable lattice temperature value and chooses for the device simulation. The other parameter that should be optimized is the length of trench window (it is shown in Fig. 1). In Fig. 9 the breakdown voltage as a function of LOW/LTW is plotted for the PTR-LDMOS structure. Increasing LOW/LTW causes high breakdown voltage until the LOW/LTW reaches about value 1. After this value, increasing LOW/LTW reduces the breakdown voltage. This reduction is due to the electric field. It means by increasing the length of open window, the numbers of trench windows reduce which decreases the numbers of additional peaks in the electric field profile and reduces the breakdown voltage. So, LOW/LTW ¼ 1 is suitable to have high breakdown voltage. The optimum length and depth of trench Si3N4 is determined in Fig. 10 and Fig. 11. In Fig. 10, the maximum temperature in the drift region and the breakdown voltages is shown for different trench lengths. It is clear that longer trench increases the maximum temperature in the drift region. But, in another point of view, increasing the trench length causes higher breakdown voltage. In this case the Ltrench ¼ 9 mm is chosen to have an acceptable temperature in the drift region and high breakdown voltage. Drain current is plotted in different trench depths in Fig. 11. The trench in the drift region acts as a barrier for the electrons to flow. Increasing the depth of trench in the drift reduces the drain current as it is shown in the figure. But, increased trench depth causes high breakdown voltage. So, a trade off should be considered to have suitable drain current and breakdown voltage. Dtrench ¼ 0.4 is an acceptable value for the proposed PTR-LDMOS transistor to have high drain current and breakdown voltage.
Breakdown Voltage [V]
420 350 280
PTR-LDMOS C-LDMOS
210 140
70 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Silicon Layer Thickness [μm] Fig. 7. Dependence of the breakdown voltage on the silicon thickness in PTR-LDMOS transistor and C-LDMOS.
Lattice Temperature [K]
480
450
420
PTR-LDMOS
390
360
330
LDrift= 11 μm 0.2
0.4
0.6
0.8
1.0
1.2
Length of Open Window (LOW) [μm] Fig. 8. Lattice temperature as a function of open window length for PTR-LDMOS structure.
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
199
450
PTR-LDMOS
Breakdown Voltage [V]
420
390
360
330
300 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Ratio of LOW to LTW(LOW/LTW)
Maximum Temperature in the Drift Region [K]
Fig. 9. Breakdown voltage of PTR-LDMOS versus the ratio of LOW/LTW.
BV=821 V 500
PTR-LDMOS
450
BV=764 V BV=659 V
BV=426 V
400
BV=312 V 350
LDrift= 20 μm 6
8
10
12
14
16
Trench Length (LTrench) [μm]
Fig. 10. Comparison of maximum temperature in the drift region and breakdown voltage of PTR-LDMOS transistor in different trench length.
Fig. 11. Dependence of drain current on the trench depth in PTR-LDMOS transistor.
4. Conclusion A new reliable high breakdown voltage LDMOS is reported in this paper. In the new transistor, a Si3N4 trench region is considered in the drift region and periodic open window with silicon material is inserted in this trench. Thermal conductivity of Si3N4 in the trench region of proposed PTR-LDMOS is better than silicon dioxide in the trench oxide of conventional LDMOS
200
M. Mehrad / Superlattices and Microstructures 91 (2016) 193e200
(C-LDMOS). So, lattice temperature reduces significantly. Also, periodic silicon windows cause additional peaks in the electric profile which reduces the height of main peaks. The simulation with ATLAS simulator shows high breakdown voltage and reduced electron temperature of the proposed LDMOS structure. References [1] A.A. Orouji, M. Mehrad, A new rounded edge fin field effect transistor for improving self-heating effects, Jpn. J. Appl. Phys. 50 (2011) 124303e124309. [2] S.E. Jamali Mahabadi, Ali A. Orouji, Parviz Keshavarzi, Saba Rajabi, Hamid Amini Moghadam, Maryam Iranian Pour Haghighi, A novel step buried oxide partial SOI LDMOSFET with triple drift layer, in: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), India, 2011, pp. 174e177. [3] M. Saremi, A.A. Kusha, S. Mohammadi, Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits, Microelectron. Eng. 95 (2012) 74e82. [4] V. Fathipour, A. Mojab, M.A. Malakoutian, S. Fathipour, M. Fathipour, The impact of process parameter variations on the electrical characteristics of a RESURF LDMOS and its compact modeling, in: IEEE International Semiconductor Device Research Symposium (ISDRS), College Park, MD, Dec, 2011. [5] M. Saremi, B. Ebrahimi, A.A. Kusha, Process variation study of ground plane SOI MOSFET, in: 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010, pp. 66e69. [6] Hamid Amini Moghadam, S.E. Jamali Mahabadi, Saba Rajabi, Combination of a 4H-SiC MESFET with a 4H-SiC MOSFET to realize a high voltage MOSFET, in: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), India, 2011, pp. 172e173. [7] M. Saremi, B. Ebrahimi, A.A. Kusha, Ground plane SOI MOSFET based SRAM with consideration of process variation, in: Proc. 2010 International Conference on Electron Devices & Solid-state Circuits (EDSSC), 2010, pp. 1e4. [8] Hamid Amini Moghadam, Ali A. Orouji, S.E. Jamali Mahabadi, Employing reduced surface field technique by a P-type region in 4H-SiC metal semiconductor field effect transistors for increasing breakdown voltage, Int. J. Numer. Model. Electron. 26 (no. 2) (2013) 103e111. [9] S.E. Jamali Mahabadi, Hamid Amini Moghadam, Comprehensive study of a 4HeSiC MESeMOSFET, Phys. E Low Dimens. Syst. Nanostruct. 74 (2015) 25e29. [10] H. Aghababa, B. Ebrahimi, M. Saremi, V. Moalemi, B. Forouzandeh, G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems, IEICE Electron. Express 9 (2012) 881e887. [11] M.A. Malakoutian, V. Fathipour, M. Fathipour, A. Mojab, M.M. Allame, M. Moradinasab, The impact of process parameters on the output characteristics of an LDMOS Device, World Acad. Sci. Eng. Technol. 4 (No. 9) (Sep. 2010). [12] E. Arnold, Silicon-on-insulator devices for high voltage and power IC applications, J. Electrochem. Soc. 141 (1994) 1983. [13] S. Cristoloveanu, Silicon on insulator technologies and devices: from present to future, Solid State Electron. 45 (2001) 1403e1411. [14] J.P. Colinge, Silicon-on-insulator Technology: Materials to VLSI, third ed., Kluwer Academic Publishers, 2004. [15] P. Antognetti, Power Integrated Circuits: Physics, Design and Applications, McGraw-Hill, 1986. [16] H. Lu, C. Andre, T. Salama, A 2 GHz, 60 V-Class, SOI power LDMOSFET for base station applications, in: Proc. IEEE 15th Int. Symp. ISPSD, 2003, pp. 270e273. [17] A.A. Orouji, M. Mehrad, Positive charges at buried oxide interface of resurf: an analytical model for the breakdown voltage, Superlattices Microstruct. 72 (2014) 336e343. [18] A.A. Orouji, M. Mehrad, The best control of parasitic BJT effect in SOI-LDMOS with SiGe window under channel, IEEE Trans. Electron. Devices 59 (2012) 419e425. [19] S.E.J. Mahabadi, A.A. Orouji, P. Keshavarzi, H.A. Moghadam, A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage, Semicond. Sci. Technol. 26 (2011) 095005. [20] A.A. Orouji, M. Mehrad, Breakdown voltage improvement of LDMOSs by charge balancing: an inserted p-layer in trench oxide (IPT-LDMOS), Superlattices Microstruct. 51 (2012) 412e420. [21] S.E.J. Mahabadi, S. Rajabi, J. Loiacono, A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement, Superlattices Microstruct. 85 (2015) 872e879. [22] M. Mehrad, A.A. Orouji, A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a u-shape buried oxide feature, Mater. Sci. Semicond. Process. 16 (2013) 1977e1981. [23] M. Mehrad, Omega shape channel LDMOS: A novel structure for high voltage applications, Phys. E Low Dimens. Syst. Nanostruct. 75 (2016) 196e201. [24] M. Zareiee, A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel, Superlattices Microstruct. 88 (2015) 254e261. [25] Atlas User's Manual, Silvaco International, Santa Clara, CA, 2007. [26] M. Mehrad, A.A. Orouji, New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using SiGe zone in drift region, Curr. Appl. Phys. 12 (2012) 1340e1344. [27] S.E. Jamali Mahabadi, Ali A. Orouji, Hamid Amini Moghadam, P. Keshavarzi, A new method for improving breakdown voltage in PSOI MOSFETs using variable drift region doping concentration, in: IEEE International Conference on Computer Science and Automation Engineering (CSAE) China, vol. 3, 2011, pp. 57e60. [28] S.E. Jamali Mahabadi, Upper drift region double step partial SOI LDMOSFET: a novel device for enhancing breakdown voltage and output characteristics, Superlattices Microstruct. 89 (2016) 345e354. [29] M. Mehrad, Thin layer oxide in the drift region of laterally double-diffused metal oxide semiconductor on silicon-on-insulator: a novel device structure enabling reliable high-temperature power transistors, Mater. Sci. Semicond. Process. 30 (2015) 599e604. [30] M. Saremi, B. Ebrahimi, A.A. Kusha, S. Mohammadi, A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement, Microelectron. Reliab. 51 (2011) 2069e2076.