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Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS)
Superlattices and Microstructures 51 (2012) 412–420
Contents lists available at SciVerse ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS) Ali A. Orouji ⇑, Mahsa Mehrad Electrical Engineering Department, Semnan University, Semnan, Iran
a r t i c l e
i n f o
Article history: Received 28 September 2011 Received in revised form 26 November 2011 Accepted 4 January 2012 Available online 10 January 2012 Keywords: LDMOS Trench oxide Breakdown voltage Specific on-resistance
a b s t r a c t For the first time, the novel inserted P-layer in trench oxide of LDMOS structure (IPT-LDMOS) is proposed in which a trench oxide with inserted P-layer is considered in the drift region to improve the breakdown voltage. Our simulation with two dimensional ALTAS simulator shows that by determining the optimum doping concentration of the P-layer, the charges of the N-drift and P-layer regions would be balanced. Therefore, complete depletion at the breakdown voltage in the drift region happens. Also, electric field in the IPT-LDMOS is modified by producing additional peaks which decrease the common peaks near the drain and source junctions. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction High performance power transistor is essential for integrated circuits and discrete power devices. Among different power transistors, Lateral Double Diffused MOSFET (LDMOS) structure has been widely used in intelligent power applications [1–3]. In another vision, silicon on insulator (SOI) technology has been attracted much attention in power ICs due to the low leakage current, higher switching speed, considerable reduction in parasitic capacitance and so on [4]. However, low vertical breakdown voltage in SOI devices is the major problem that restricts power applications. In order to increase breakdown voltage in such devices, many novel structures have been proposed in which modifying the electric field distribution in the drift region is the effective solution [5–7]. Another challenge in the power device design is obtaining small specific on-resistance [8,9]. Two significant methods which reduce specific on-resistance are obtained by a high doping concentration in drift region and short drift length [10]. But, these solutions reduce breakdown voltage [9–11]. In order ⇑ Corresponding author. Tel.: +98 2313354100; fax: +98 2313331623. E-mail address: [email protected] (A.A. Orouji). 0749-6036/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.spmi.2012.01.005
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to achieve the best characteristic of LDMOS in both of breakdown voltage and specific on-resistance, a novel structure has been proposed in this paper. The goal of the present work is incorporating trench oxide with inserted P-layer in the drift region. The proposed structure which is named as inserted P-layer in trench oxide of LDMOS (IPT-LDMOS), exhibits the best characteristics in terms of breakdown voltage and specificon-resistance. An interesting mechanism occurs to improve breakdown voltage of IPT-LDMOS. The inserted Player helps reducing the surface electric field and simultaneously increases the breakdown voltage. It means that when the device switches in the OFF state with high drain voltage, the depletion width of the reverse-biased junction between the inserted P-layer and N-drift will increase. So, it helps to deplete the drift region and also increase the breakdown voltage. It is important to note that when the transistor is in the ON state with a low drain voltage, the depletion width of the reverse-biased junction is small which have a few influences on the ON-state current. Also, the P-layer is doped to achieve a balanced charge condition which means that the charge of depletion layer is zero. Our simulation with two dimensional ATLAS simulator shows the P-layer in the trench oxide helps to reduce the drift length without further decreasing the conduction area [12]. So, the specific onresistance of the IPT-LDMOS is reduced effectively as compared with Conventional LDMOS structure (C-LDMOS) which the trench oxide and the P-layer are not considered in the drift region.
2. Device structure and simulation The schematic cross section of the IPT-LDMOS is illustrated in Fig. 1. As the figure shows the trench oxide is located in the drift region and a P-layer is inserted in it with the length of LP and the depth of DP. Also, the length and depth of trench oxide are labeled as, LT and DT, respectively. The thicknesses of buried oxide and silicon layer are 0.3 and 0.6 lm, respectively. The length and depth of P-layer as well as its doping concentration is determined in the next part. The IPT-LDMOS parameters used in our simulation are shown in Table 1. All the device parameters of the new structure are equivalent to those of the C-LDMOS unless otherwise state. Two dimensional numerical simulations of the proposed structure are done with ATLAS simulator. In addition to, Poisson and drift/diffusion equations, SRH (Shockley-Read-Hall) and Auger models are considered for generation/recombination, and also IMPACT SELB for impact ionization. These simulations methods allow taking into account carrier velocity saturation, carrier–carrier scattering in the high doping concentration, dependence of mobility on temperature and vertical electric influence [13]. It is worth noting that the two dimensional (2D) simulator is calibrated to experimental data [14]. The transfer characteristics at the drain bias of 0.1 V of SOI-LDMOS, is extracted from experimentally measured have been compared with ATLAS simulation in Fig. 2 [14]. It can be seen from the figure that a good agreement between experimental data and 2D simulation results is achieved.
Gate Source
Drain N+ Poly
A
N+
P
tOX DP
LT A’ SiO2 P-Layer
N-Drift
DT
N+
TSi
LP
SiO2 Substrate Fig. 1. Schematic of Inserted P-layer in trench oxide of LDMOS (IPT-LDMOS).
TOX
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Table 1 Typical parameters for IPT-LDMOS and C-LDMOS used in simulations. Device parameters
Value in IPT-LDMOS
Value in C-LDMOS
Gate length (LG) Channel length Drift region length P-layer length (LP) Trench oxide length (LT) Buried oxide thickness Silicon thickness Gate oxide thickness Trench oxide depth (DT) P-layer depth (DP) P-layer doping concentration Channel doping concentration Source/drain doping concentration Substrate doping concentration Drift region doping concentration
5 lm 2 lm 10 lm 3 lm 5 lm 0.3 lm 0.6 lm 50 nm 0.3 lm 0.1 lm 2 1016 cm3 1 1017 cm3 1 1019 cm3 5 1013 cm3 5 1015 cm3
5 lm 2 lm 10 lm Not defined Not defined 0.3 lm 0.6 lm 50 nm Not defined Not defined Not defined 1 1017 cm3 1 1019 cm3 5 1013 cm3 5 1015 cm3
Drain Current [mA]
2.0
Experimental Data [14] ATLAS Simulation
1.5
1.0
0.5
VDS=0.1 V 0.0 0
1
2
3
4
5
6
Gate Voltage [V] Fig. 2. The output characteristic of simulated SOI-LDMOS has been compared with experimental results in Ref. [14] at the drain bias of 0.1 V.
3. Results and discussion 3.1. Performance of IPT-LDMOS in comparison with C-LDMOS Fig. 3(a) and (b) shows the electron concentration in the drift region of IPT-LDMOS and C-LDMOS at VGS = 0 V, respectively. The applied voltage between drain and source is VDS = 80 V for IPT-LDMOS and VDS = 48 V for the C-LDMOS. It is clear in the figure that in the proposed structure the trench oxide in the N-drift region blocks the passage of charge carriers at higher drain voltage. Also, the complete active drift region gets depleted due to the balanced charges of N-drift region (Qn) and inserted P-layer (Qp). Fig. 4 shows the electric field distribution of the IPT-LDMOS and C-LDMOS along the AA0 cut line located at 20 nm from the surface of the N-drift region. As can be seen from the figure, there is one new electric field peak in IPT-LDMOS structure in addition to the usual electric field peaks. In the C-LDMOS, the peaks are located in the x = 3 lm (the interface of the source and gate regions), x = 8 lm (under poly gate corner), and x = 15 lm (the edge between drift region and drain).
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Fig. 3. Distribution of electron concentration in the drift region for (a) IPT-LDMOS and (b) C-LDMOS.
5
Horizontal Electric Field [V/cm]
3.0x10
5
2.5x10
IPT-LDMOS C-LDMOS
5
2.0x10
5
1.5x10
5
1.0x10
4
5.0x10
0.0 0
4
8
12
16
X Position [μm] Fig. 4. Horizontal electric field profiles for the IPT-LDMOS and C-LDMOS structures along cutline AA0 .
Previous efforts show that trench oxide in the drift region causes an additional peak in the middle of the trench oxide [15]. In the IPT-LDMOS, inserted P-layer in the trench oxide creates two peaks. One peak occurs in the left edge of trench oxide (at x = 8 lm) and the other peak is located in the right edge of trench oxide (at x = 13 lm). As the figure shows the left edge of trench oxide in IPT-LDMOS is located under poly gate corner (at x = 8 lm). So, in x = 8 lm the electric field has higher value in the proposed structure than conventional one.
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In another point of view, the applied voltage magnitude is the area underneath the electric field curve. So, the heights of peaks in drain and source of IPT-LDMOS are reduced as compared with CLDMOS. This effect is due to the new peaks in the proposed structure which modulates surface electric field distribution. Therefore, more uniform electric field distribution and the effective improvement in breakdown voltage are achieved. The variation of the OFF state breakdown voltage versus the N-drift length has been shown in Fig. 5. It is clear that in IPT-LDMOS and C-LDMOS devices, breakdown voltage increases by longer N-drift length. This effect is due to the voltage drop along drift region. In the IPT-LDMOS, as the drift length increases from 5 to 10 lm, the breakdown voltage increases from 52 to 80 V. Therefore, with the same N-drift length and doping concentration, the breakdown voltage increases about 35% in the proposed structure. This especial behavior is due to the trench oxide with P-layer inserted in it which can reduce the surface electric field under the gate edge in the drift region. Fig. 6 shows the breakdown voltage versus N-drift doping concentration for both IPT-LDMOS and C-LDMOS structures. If the N-drift doping reduces below the 5 1015 cm3, the maximum electric field is moved towards the drain edge. If the doping exceeds the 5 1015 cm3, a high electric field is moved towards the gate edge. In both cases lower breakdown voltage is achieved. In the proposed structure, the trench oxide with P-layer increases the surface path of the depletion region and drift length can be reduced without degrading the breakdown voltage. Also, in the LDMOS structure reduced the N-drift area affects the charge balance condition, so, the maximum doping in the drift region increases slightly. Reduced silicon film thickness is one of the important challenges in SOI devices. As the silicon thickness reduces, the carrier mobility would increase and also kink effect would be eliminated. In Fig. 7 the variation of the breakdown voltage versus silicon film thickness (TSi) shows that the highest breakdown voltage occurs in the o.6 lm of IPT-LDMOS as well as conventional structure. It is important to note that in IPT-LDMOS maximum breakdown voltage is increased about 40% in comparison with C-LDMOS. Fig. 8 shows the comparison of specific on-resistance versus the drift region length for the IPTLDMOS and C-LDMOS. The IPT-LDMOS shows lower specific on resistance due to the P-layer in the trench oxide that helps to reduce the drift length without further decreasing the conduction area.
85 80 75
Breakdown Voltage [V]
70 65 60 55 50 45 40 35 30
IPT-LDMOS C-LDMOS
25 20 15 4
6
8
10
12
N-Drift Length [μm] Fig. 5. Variation of breakdown voltage versus N-drift length for IPT-LDMOS and C-LDMOS.
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90
IPT-LDMOS C-LDMOS
Breakdown Voltage [V]
80
70
60
50
40
30 15
16
10
10 -3
N-Drift Doping Concentration [cm ] Fig. 6. Breakdown voltage as a function of N-drift doping concentration.
IPT-LDMOS C-LDMOS
80
Breakdown Voltage [V]
70
60
50
40
30 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Silicon Layer Thickness [μm] Fig. 7. Comparison of breakdown voltage versus silicon layer thickness for IPT-LDMOS and C-LDMOS.
3.2. Design consideration In this section the thicknesses of trench oxide and P-layer as well as their lengths are determined. In Fig. 9, the breakdown voltage versus doping concentration of P-layer in the proposed structure with various DT/DP is shown. The doping concentration of N-drift is fixed at 5 1015 cm3. The ratio of DT/ DP determines the length of the surface path of the device. The breakdown voltage has higher value
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IPT-LDMOS C-LDMOS
2
Specific on-Resistance [mΩ cm ]
20
15
10
5
6
8
10
12
14
16
Drift Region Length [μm] Fig. 8. Comparison of specific on-resistance versus drift region length for IPT-LDMOS and C-LDMOS.
Breakdown Voltage [V]
80
70
IPT-LDMOS (DT/DP=1.5 μm) IPT-LDMOS (DT/DP=2 μm) IPT-LDMOS (DT/DP=3 μm) IPT-LDMOS (DT/DP=3.5 μm)
60
16
17
10
10 -3
Doping Concentration of P-Layer [cm ] Fig. 9. Breakdown voltage of IPT-LDMOS for different ratio of DT/DP.
(80 V) if the DT/DP = 3. Also, in the ratio of 3.5, the breakdown voltage is 80 V but it occurs in the higher doping of P-layer due to the balanced charges in the drift region. So, we have considered DT = 0.3 lm and DP = 0.1 lm in our simulation. In order to obtain the maximum breakdown voltage in the IPTLDMOS, Qn and Qp must be balanced for complete depletion of drift region at the breakdown voltage. If the P-layer length becomes larger, the doping concentration of this layer should be reduced to fulfill
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IPT-LDMOS (LT= 3 μm) IPT-LDMOS (LT= 4 μm) IPT-LDMOS (LT= 5 μm)
2
Specific-on-Resistance [mΩ cm ]
15
10
5
0 0
1
2
3
4
5
6
Length of P-Layer [μm] Fig. 10. Specific on-resistance as a function of the P-layer length for different trench lengths.
the charge balance. Fig. 10 shows the relationship between specific on-resistance and P-layer length for different trench oxide lengths. As the figure shows in lower LP and LT specific on-resistance of the proposed structure is improved due to the increased conduction area. In the LT = 5 lm and LP = 3 lm it is possible to achieve minimum specific on-resistance of about 4.9 mO cm2. 4. Conclusion In order to improve breakdown voltage, a novel structure of the LDMOS device is proposed. At Inserted P-layer in Trench oxide of LDMOS (IPT-LDMOS) structure, the P-layer is incorporated in trench oxide to modify electric field by additional peaks in the edges of trench oxide. Also, our simulation with two dimensional ATLAS simulator shows the charges of P-layer and N-drift can be balanced to deplete drift region. References [1] P. Antognetti, Power Integrated Circuits: Physics, Design and Applications, McGraw-Hill, 1986. [2] H. Xu, E. Lampin, E. Dubois, S. Bardy, F. Murray, Impact of large tilt implantation on the threshold voltage of LDMOS transistors on SOI, Mater. Sci. Eng. B, 2005, pp. 323–326. [3] G. Ma, W. Burger, M. Shelds, High efficiency 0.4 lm gate LDMOS power FET for low voltage wireless communications, in: Proceedings of the IEEE Microwave Theory Technical Society Symposium Dig., 1999, pp. 1195–1198. [4] E. Arnold, Silicon-on-insulator devices for high voltage and power IC applications, J. Electrochem. Soc. 141 (1994) 1983. [5] A.A. Orouji, H.A. Moghadam, A. Dideban, Double window partial SOI-LDMOSFET: a novel device for breakdown voltage improvement, Physica E: Low-dimensional Syst. Nanostruct. (2010) 498–502. [6] A.A. Orouji, S. Sharbati, M. Fathiopur, A new partial-SOI LDMOSFET with modified electric field for breakdown voltage improvement, IEEE Trans. Device Mater. Reliab. 9 (3) (2009) 449–453. [7] H. Elahipanah, A.A. Orouji, A1300-V 0.34-O cm2 partial SOI LDMOSFET with novel dual charge accumulation layers, IEEE Trans. Electron Device 57 (8) (2010) 1959–1965. [8] A.W. Ludikhuize, A review of RESURF technology, in: Proceedings of ISPSD, 2000, pp. 11–18. [9] W. Chen, B. Zhang, Z. Li, SJ-LDMOS with high breakdown voltage and ultra-low on-resistance, Electron. Lett. 42 (22) (2006) 1314–1316. [10] X.B. Chen, J.K.O. Sin, Optimization of the specific on-resistance of the COOLMOS, IEEE Trans. Electron Devices 48 (2) (2001) 344–348. [11] J.F. Chen, J.R. Lee, K.M. Wu, T.Y. Huang, C.M. Liu, Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors, IEEE Trans. Electron Devices 55 (8) (2008) 2259–2262.
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[12] Device simulator ATLAS, Silvaco, International, 2007. [13] Atlas User’s Manual, Silvaco International, Santa Clara, CA, 2007. [14] X. Cheng, Z. Song, Y. Dong, Y. Yu, D. Shen, Patterned silicon-on-insulator technology for RF power LDMOSFET, Microelectron. Eng. 81 (2005) 150–155. [15] W.S. Son, Y.H. Sohn, S.Y. Choi, Effects of a trench under the gate in high voltage RESURF LDMOS for SOI power integrated circuits, Solid-State Electron. 48 (2004) 1629–1635.
Contents lists available at SciVerse ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS) Ali A. Orouji ⇑, Mahsa Mehrad Electrical Engineering Department, Semnan University, Semnan, Iran
a r t i c l e
i n f o
Article history: Received 28 September 2011 Received in revised form 26 November 2011 Accepted 4 January 2012 Available online 10 January 2012 Keywords: LDMOS Trench oxide Breakdown voltage Specific on-resistance
a b s t r a c t For the first time, the novel inserted P-layer in trench oxide of LDMOS structure (IPT-LDMOS) is proposed in which a trench oxide with inserted P-layer is considered in the drift region to improve the breakdown voltage. Our simulation with two dimensional ALTAS simulator shows that by determining the optimum doping concentration of the P-layer, the charges of the N-drift and P-layer regions would be balanced. Therefore, complete depletion at the breakdown voltage in the drift region happens. Also, electric field in the IPT-LDMOS is modified by producing additional peaks which decrease the common peaks near the drain and source junctions. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction High performance power transistor is essential for integrated circuits and discrete power devices. Among different power transistors, Lateral Double Diffused MOSFET (LDMOS) structure has been widely used in intelligent power applications [1–3]. In another vision, silicon on insulator (SOI) technology has been attracted much attention in power ICs due to the low leakage current, higher switching speed, considerable reduction in parasitic capacitance and so on [4]. However, low vertical breakdown voltage in SOI devices is the major problem that restricts power applications. In order to increase breakdown voltage in such devices, many novel structures have been proposed in which modifying the electric field distribution in the drift region is the effective solution [5–7]. Another challenge in the power device design is obtaining small specific on-resistance [8,9]. Two significant methods which reduce specific on-resistance are obtained by a high doping concentration in drift region and short drift length [10]. But, these solutions reduce breakdown voltage [9–11]. In order ⇑ Corresponding author. Tel.: +98 2313354100; fax: +98 2313331623. E-mail address: [email protected] (A.A. Orouji). 0749-6036/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.spmi.2012.01.005
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to achieve the best characteristic of LDMOS in both of breakdown voltage and specific on-resistance, a novel structure has been proposed in this paper. The goal of the present work is incorporating trench oxide with inserted P-layer in the drift region. The proposed structure which is named as inserted P-layer in trench oxide of LDMOS (IPT-LDMOS), exhibits the best characteristics in terms of breakdown voltage and specificon-resistance. An interesting mechanism occurs to improve breakdown voltage of IPT-LDMOS. The inserted Player helps reducing the surface electric field and simultaneously increases the breakdown voltage. It means that when the device switches in the OFF state with high drain voltage, the depletion width of the reverse-biased junction between the inserted P-layer and N-drift will increase. So, it helps to deplete the drift region and also increase the breakdown voltage. It is important to note that when the transistor is in the ON state with a low drain voltage, the depletion width of the reverse-biased junction is small which have a few influences on the ON-state current. Also, the P-layer is doped to achieve a balanced charge condition which means that the charge of depletion layer is zero. Our simulation with two dimensional ATLAS simulator shows the P-layer in the trench oxide helps to reduce the drift length without further decreasing the conduction area [12]. So, the specific onresistance of the IPT-LDMOS is reduced effectively as compared with Conventional LDMOS structure (C-LDMOS) which the trench oxide and the P-layer are not considered in the drift region.
2. Device structure and simulation The schematic cross section of the IPT-LDMOS is illustrated in Fig. 1. As the figure shows the trench oxide is located in the drift region and a P-layer is inserted in it with the length of LP and the depth of DP. Also, the length and depth of trench oxide are labeled as, LT and DT, respectively. The thicknesses of buried oxide and silicon layer are 0.3 and 0.6 lm, respectively. The length and depth of P-layer as well as its doping concentration is determined in the next part. The IPT-LDMOS parameters used in our simulation are shown in Table 1. All the device parameters of the new structure are equivalent to those of the C-LDMOS unless otherwise state. Two dimensional numerical simulations of the proposed structure are done with ATLAS simulator. In addition to, Poisson and drift/diffusion equations, SRH (Shockley-Read-Hall) and Auger models are considered for generation/recombination, and also IMPACT SELB for impact ionization. These simulations methods allow taking into account carrier velocity saturation, carrier–carrier scattering in the high doping concentration, dependence of mobility on temperature and vertical electric influence [13]. It is worth noting that the two dimensional (2D) simulator is calibrated to experimental data [14]. The transfer characteristics at the drain bias of 0.1 V of SOI-LDMOS, is extracted from experimentally measured have been compared with ATLAS simulation in Fig. 2 [14]. It can be seen from the figure that a good agreement between experimental data and 2D simulation results is achieved.
Gate Source
Drain N+ Poly
A
N+
P
tOX DP
LT A’ SiO2 P-Layer
N-Drift
DT
N+
TSi
LP
SiO2 Substrate Fig. 1. Schematic of Inserted P-layer in trench oxide of LDMOS (IPT-LDMOS).
TOX
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Table 1 Typical parameters for IPT-LDMOS and C-LDMOS used in simulations. Device parameters
Value in IPT-LDMOS
Value in C-LDMOS
Gate length (LG) Channel length Drift region length P-layer length (LP) Trench oxide length (LT) Buried oxide thickness Silicon thickness Gate oxide thickness Trench oxide depth (DT) P-layer depth (DP) P-layer doping concentration Channel doping concentration Source/drain doping concentration Substrate doping concentration Drift region doping concentration
5 lm 2 lm 10 lm 3 lm 5 lm 0.3 lm 0.6 lm 50 nm 0.3 lm 0.1 lm 2 1016 cm3 1 1017 cm3 1 1019 cm3 5 1013 cm3 5 1015 cm3
5 lm 2 lm 10 lm Not defined Not defined 0.3 lm 0.6 lm 50 nm Not defined Not defined Not defined 1 1017 cm3 1 1019 cm3 5 1013 cm3 5 1015 cm3
Drain Current [mA]
2.0
Experimental Data [14] ATLAS Simulation
1.5
1.0
0.5
VDS=0.1 V 0.0 0
1
2
3
4
5
6
Gate Voltage [V] Fig. 2. The output characteristic of simulated SOI-LDMOS has been compared with experimental results in Ref. [14] at the drain bias of 0.1 V.
3. Results and discussion 3.1. Performance of IPT-LDMOS in comparison with C-LDMOS Fig. 3(a) and (b) shows the electron concentration in the drift region of IPT-LDMOS and C-LDMOS at VGS = 0 V, respectively. The applied voltage between drain and source is VDS = 80 V for IPT-LDMOS and VDS = 48 V for the C-LDMOS. It is clear in the figure that in the proposed structure the trench oxide in the N-drift region blocks the passage of charge carriers at higher drain voltage. Also, the complete active drift region gets depleted due to the balanced charges of N-drift region (Qn) and inserted P-layer (Qp). Fig. 4 shows the electric field distribution of the IPT-LDMOS and C-LDMOS along the AA0 cut line located at 20 nm from the surface of the N-drift region. As can be seen from the figure, there is one new electric field peak in IPT-LDMOS structure in addition to the usual electric field peaks. In the C-LDMOS, the peaks are located in the x = 3 lm (the interface of the source and gate regions), x = 8 lm (under poly gate corner), and x = 15 lm (the edge between drift region and drain).
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Fig. 3. Distribution of electron concentration in the drift region for (a) IPT-LDMOS and (b) C-LDMOS.
5
Horizontal Electric Field [V/cm]
3.0x10
5
2.5x10
IPT-LDMOS C-LDMOS
5
2.0x10
5
1.5x10
5
1.0x10
4
5.0x10
0.0 0
4
8
12
16
X Position [μm] Fig. 4. Horizontal electric field profiles for the IPT-LDMOS and C-LDMOS structures along cutline AA0 .
Previous efforts show that trench oxide in the drift region causes an additional peak in the middle of the trench oxide [15]. In the IPT-LDMOS, inserted P-layer in the trench oxide creates two peaks. One peak occurs in the left edge of trench oxide (at x = 8 lm) and the other peak is located in the right edge of trench oxide (at x = 13 lm). As the figure shows the left edge of trench oxide in IPT-LDMOS is located under poly gate corner (at x = 8 lm). So, in x = 8 lm the electric field has higher value in the proposed structure than conventional one.
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In another point of view, the applied voltage magnitude is the area underneath the electric field curve. So, the heights of peaks in drain and source of IPT-LDMOS are reduced as compared with CLDMOS. This effect is due to the new peaks in the proposed structure which modulates surface electric field distribution. Therefore, more uniform electric field distribution and the effective improvement in breakdown voltage are achieved. The variation of the OFF state breakdown voltage versus the N-drift length has been shown in Fig. 5. It is clear that in IPT-LDMOS and C-LDMOS devices, breakdown voltage increases by longer N-drift length. This effect is due to the voltage drop along drift region. In the IPT-LDMOS, as the drift length increases from 5 to 10 lm, the breakdown voltage increases from 52 to 80 V. Therefore, with the same N-drift length and doping concentration, the breakdown voltage increases about 35% in the proposed structure. This especial behavior is due to the trench oxide with P-layer inserted in it which can reduce the surface electric field under the gate edge in the drift region. Fig. 6 shows the breakdown voltage versus N-drift doping concentration for both IPT-LDMOS and C-LDMOS structures. If the N-drift doping reduces below the 5 1015 cm3, the maximum electric field is moved towards the drain edge. If the doping exceeds the 5 1015 cm3, a high electric field is moved towards the gate edge. In both cases lower breakdown voltage is achieved. In the proposed structure, the trench oxide with P-layer increases the surface path of the depletion region and drift length can be reduced without degrading the breakdown voltage. Also, in the LDMOS structure reduced the N-drift area affects the charge balance condition, so, the maximum doping in the drift region increases slightly. Reduced silicon film thickness is one of the important challenges in SOI devices. As the silicon thickness reduces, the carrier mobility would increase and also kink effect would be eliminated. In Fig. 7 the variation of the breakdown voltage versus silicon film thickness (TSi) shows that the highest breakdown voltage occurs in the o.6 lm of IPT-LDMOS as well as conventional structure. It is important to note that in IPT-LDMOS maximum breakdown voltage is increased about 40% in comparison with C-LDMOS. Fig. 8 shows the comparison of specific on-resistance versus the drift region length for the IPTLDMOS and C-LDMOS. The IPT-LDMOS shows lower specific on resistance due to the P-layer in the trench oxide that helps to reduce the drift length without further decreasing the conduction area.
85 80 75
Breakdown Voltage [V]
70 65 60 55 50 45 40 35 30
IPT-LDMOS C-LDMOS
25 20 15 4
6
8
10
12
N-Drift Length [μm] Fig. 5. Variation of breakdown voltage versus N-drift length for IPT-LDMOS and C-LDMOS.
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90
IPT-LDMOS C-LDMOS
Breakdown Voltage [V]
80
70
60
50
40
30 15
16
10
10 -3
N-Drift Doping Concentration [cm ] Fig. 6. Breakdown voltage as a function of N-drift doping concentration.
IPT-LDMOS C-LDMOS
80
Breakdown Voltage [V]
70
60
50
40
30 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Silicon Layer Thickness [μm] Fig. 7. Comparison of breakdown voltage versus silicon layer thickness for IPT-LDMOS and C-LDMOS.
3.2. Design consideration In this section the thicknesses of trench oxide and P-layer as well as their lengths are determined. In Fig. 9, the breakdown voltage versus doping concentration of P-layer in the proposed structure with various DT/DP is shown. The doping concentration of N-drift is fixed at 5 1015 cm3. The ratio of DT/ DP determines the length of the surface path of the device. The breakdown voltage has higher value
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IPT-LDMOS C-LDMOS
2
Specific on-Resistance [mΩ cm ]
20
15
10
5
6
8
10
12
14
16
Drift Region Length [μm] Fig. 8. Comparison of specific on-resistance versus drift region length for IPT-LDMOS and C-LDMOS.
Breakdown Voltage [V]
80
70
IPT-LDMOS (DT/DP=1.5 μm) IPT-LDMOS (DT/DP=2 μm) IPT-LDMOS (DT/DP=3 μm) IPT-LDMOS (DT/DP=3.5 μm)
60
16
17
10
10 -3
Doping Concentration of P-Layer [cm ] Fig. 9. Breakdown voltage of IPT-LDMOS for different ratio of DT/DP.
(80 V) if the DT/DP = 3. Also, in the ratio of 3.5, the breakdown voltage is 80 V but it occurs in the higher doping of P-layer due to the balanced charges in the drift region. So, we have considered DT = 0.3 lm and DP = 0.1 lm in our simulation. In order to obtain the maximum breakdown voltage in the IPTLDMOS, Qn and Qp must be balanced for complete depletion of drift region at the breakdown voltage. If the P-layer length becomes larger, the doping concentration of this layer should be reduced to fulfill
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IPT-LDMOS (LT= 3 μm) IPT-LDMOS (LT= 4 μm) IPT-LDMOS (LT= 5 μm)
2
Specific-on-Resistance [mΩ cm ]
15
10
5
0 0
1
2
3
4
5
6
Length of P-Layer [μm] Fig. 10. Specific on-resistance as a function of the P-layer length for different trench lengths.
the charge balance. Fig. 10 shows the relationship between specific on-resistance and P-layer length for different trench oxide lengths. As the figure shows in lower LP and LT specific on-resistance of the proposed structure is improved due to the increased conduction area. In the LT = 5 lm and LP = 3 lm it is possible to achieve minimum specific on-resistance of about 4.9 mO cm2. 4. Conclusion In order to improve breakdown voltage, a novel structure of the LDMOS device is proposed. At Inserted P-layer in Trench oxide of LDMOS (IPT-LDMOS) structure, the P-layer is incorporated in trench oxide to modify electric field by additional peaks in the edges of trench oxide. Also, our simulation with two dimensional ATLAS simulator shows the charges of P-layer and N-drift can be balanced to deplete drift region. References [1] P. Antognetti, Power Integrated Circuits: Physics, Design and Applications, McGraw-Hill, 1986. [2] H. Xu, E. Lampin, E. Dubois, S. Bardy, F. Murray, Impact of large tilt implantation on the threshold voltage of LDMOS transistors on SOI, Mater. Sci. Eng. B, 2005, pp. 323–326. [3] G. Ma, W. Burger, M. Shelds, High efficiency 0.4 lm gate LDMOS power FET for low voltage wireless communications, in: Proceedings of the IEEE Microwave Theory Technical Society Symposium Dig., 1999, pp. 1195–1198. [4] E. Arnold, Silicon-on-insulator devices for high voltage and power IC applications, J. Electrochem. Soc. 141 (1994) 1983. [5] A.A. Orouji, H.A. Moghadam, A. Dideban, Double window partial SOI-LDMOSFET: a novel device for breakdown voltage improvement, Physica E: Low-dimensional Syst. Nanostruct. (2010) 498–502. [6] A.A. Orouji, S. Sharbati, M. Fathiopur, A new partial-SOI LDMOSFET with modified electric field for breakdown voltage improvement, IEEE Trans. Device Mater. Reliab. 9 (3) (2009) 449–453. [7] H. Elahipanah, A.A. Orouji, A1300-V 0.34-O cm2 partial SOI LDMOSFET with novel dual charge accumulation layers, IEEE Trans. Electron Device 57 (8) (2010) 1959–1965. [8] A.W. Ludikhuize, A review of RESURF technology, in: Proceedings of ISPSD, 2000, pp. 11–18. [9] W. Chen, B. Zhang, Z. Li, SJ-LDMOS with high breakdown voltage and ultra-low on-resistance, Electron. Lett. 42 (22) (2006) 1314–1316. [10] X.B. Chen, J.K.O. Sin, Optimization of the specific on-resistance of the COOLMOS, IEEE Trans. Electron Devices 48 (2) (2001) 344–348. [11] J.F. Chen, J.R. Lee, K.M. Wu, T.Y. Huang, C.M. Liu, Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors, IEEE Trans. Electron Devices 55 (8) (2008) 2259–2262.
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[12] Device simulator ATLAS, Silvaco, International, 2007. [13] Atlas User’s Manual, Silvaco International, Santa Clara, CA, 2007. [14] X. Cheng, Z. Song, Y. Dong, Y. Yu, D. Shen, Patterned silicon-on-insulator technology for RF power LDMOSFET, Microelectron. Eng. 81 (2005) 150–155. [15] W.S. Son, Y.H. Sohn, S.Y. Choi, Effects of a trench under the gate in high voltage RESURF LDMOS for SOI power integrated circuits, Solid-State Electron. 48 (2004) 1629–1635.