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Realization of 850 V breakdown voltage LDMOS on Simbond SOI
Microelectronic Engineering 91 (2012) 102–105
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Realization of 850 V breakdown voltage LDMOS on Simbond SOI Zhongjian Wang a,b,⇑, Xinhong Cheng a, Dawei He a,b, Chao Xia a,b, Dawei Xu a,b, Yuehui Yu a, Dong Zhang c, Yanying Wang c, Yuqiang Lv c, Dawei Gong c, Kai Shao c a State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, PR China b Graduate University of Chinese Academy of Sciences, Beijing 100049, PR China c Technology Development Department, Advanced Semiconductor Manufacturing Corporation Limited, Hongcao Road 385, Shanghai 200233, PR China
a r t i c l e
i n f o
Article history: Received 21 April 2011 Received in revised form 26 September 2011 Accepted 20 October 2011 Available online 12 November 2011 Keywords: SOI Simbond High voltage device LDMOS
a b s t r a c t In this paper, 850 V breakdown voltage LDMOS fabricated on Simbond SOI wafer are reported. Simbond SOI wafers with 1.5 lm top silicon, 3 lm buried oxide layer, and n-type heavy doped handle wafers are used. In order to achieve uniform lateral electric field and shorten the vertical impact ionization integration path simultaneously, an optimized 60 lm drift region implant mask is designed to realize a linearly graded doping profile, and silicon thickness in the drift region is reduced from 1.5 lm to about 0.26 lm by thick field oxide process. CMOS compatible SOI LDMOS processes are designed and implemented successfully. Off-state breakdown voltage of SOI LDMOS can reach 850 V, and the specific on-resistance is 56 X mm2. Experimental results also show the thickness of the top silicon in the drift region has a good uniformity. The performance of SOI LDMOS indicated that Simbond SOI wafers are good choice for thin film high voltage devices. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction High breakdown voltage SOI LDMOS is attractive for using in power ICs because of its excellent isolation performance and small parasitical effect [1,2]. However, the design of exceeded 600 V high voltages devices using traditional RESURF structure on SOI is commonly recognized to be difficult due to the restriction of the low vertical breakdown voltage [3]. Some theory and experimental studies have proved the maximum breakdown voltage of the SOI devices depend mainly on the thickness of SOI layer and buried oxide [4], which is showed in the expression [5,6] as below and Fig. 1. esi and eox are the relative permittivity of silicon and SiO2, respectively,
V B;V ¼
tsi esi 9:783ð21:765 ln tsi Þ t box þ 3:975 þ ln tsi 2 eox
ð1Þ
As shown in Fig. 1, when the BOX is 3 lm or above, realization of 600 V breakdown voltage devices on SOI requires the thickness of top silicon at least above 20 lm or below 0.5 lm. However, for power ICs on a thick SOI layer (>20 lm), dielectric isolation through using trenches filled with dielectric or poly material is complex and costly [7]. Furthermore, for SOI wafers with 1.5 lm top silicon, it is easy to realize full dielectric isolation by trench, ⇑ Corresponding author at: State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, PR China. E-mail address: [email protected] (Z. Wang). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.10.014
and the top silicon can be reduced to below 0.5 lm by thick field oxide process in order to support high voltage simultaneously. When the top silicon becomes thinner, the uniformity is more important parameter to sustain high voltage. Currently, bonding and SIMOX are two commercial techniques to produce SOI wafers. However, the top Si thickness of bonded SOI wafers is usually more than 5 lm, and the thickness variation is ±0.5 lm. Furthermore, SIMOX SOI suffers from the limited thickness of the buried oxide layer, and the quality of SIMOX is not as good as that of a thermally oxidized SiO2 [8,9]. Simbond SOI technologies [10–12] combine both advantages of conventional SIMOX and wafer bonding technologies, which can produce SOI wafer with superior top silicon uniformity and high quality thick buried oxide layer. Simbond SOI wafer need two Si wafers, A wafer with 3 lm oxide layer on polished side, and B wafer with 120 nm buried oxide layer formed by oxygen ion-implantation. A wafer is bonded to B wafer with a interface of oxide/top silicon, the substrate of B wafer is etched until to buried oxide layer, buried layer is also removed away, then thinning top silicon to achieve an uniform silicon surface. At last, Silicon is epitaxially grown on the uniform silicon surface to achieve 1.5 lm thickness. In this paper, the high voltage device was fabricated on Simbond SOI wafer. Thick field oxide technology was used to thin top silicon in the drift region to 0.26 lm. Process simulation was especially explored to optimize the implanting and annealing parameters for the realization of linearly graded doping profile in the drift region.
Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
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Fig. 1. The maximum breakdown voltage versus the thickness of top silicon. Fig. 4. The doping profile and the electric field distribution in the drift region.
Fig. 2. The structure of 850 V LDMOS transistor.
2. Device structure and fabrication process Simbond SOI wafer with 1.5 lm top silicon and 3 lm buried oxide layer was used for SOI LDMOS fabrication, the handle wafers were n type doped with the resistivity of 0.0008–0.0018 X cm, and the top silicon was p type doped with the resistivity 10–20 X cm. As shown in Fig. 2, SOI LDMOS structures in this work derived from NXP 650V EZ-HV™ LDMOS [13,14]. The surface lateral electric field in drift region can be expressed as [15]:
Ex ðx; 0Þ ¼
tsi esi dNðxÞ t box þ dx esi eo 2 eox qtsi
ð2Þ
N(x) is the impurity concentration in the drift reign, eo is the permittivity of vacuum. In order to achieve a uniform lateral electric field, an optimized 60 lm drift region implant mask was designed to realize a linearly graded doping profile, as showed in Fig. 3. Phosphorus was implanted into the drift region using this mask and followed by annealing drive in at 1200 °C. Thick field oxide was grown onto the drift region and silicon thickness of the drift region was reduced from 1.5 lm to 0.26 lm. P-well was formed by the implanted of boron for threshold voltage adjustment. After gate oxide was grown, polysilicon was deposited by
Fig. 5. The breakdown voltage at different thickness of top silicon.
LPCVD and patterned for gate region. The source, drain and p-body region were formed by high dose implant followed by RTA activation. Finally, the metal and passivation layer were deposited. The numbers of the first line are implanted regions (lm), the numbers of the second line are the distances between implanted regions (lm). The proposed process flow and device performance of the designed LDMOS transistor were simulated by using the mixed numerical two-dimensional TCAD tool Sentaurus. As shown in Fig. 4, the doping concentration in drift region, simulated by use of proposed process flow, increased linearly from channel edge to drain side, the lateral electric field distribution was uniform and no obvious peak appeared at pn junctions. These indicated that proposed process flow can realize linear doping profile and make lateral electric field uniform distribution. The relationship of the breakdown voltage with the thickness of top silicon in the drift region was also simulated and illustrated in Fig. 5. 0.2 lm thickness
Fig. 3. The optimized 60 lm drift region implant mask for linearly graded doping profile.
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Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
Fig. 9. The experimental micrograph of reverse breakdown point.
Fig. 6. The SEM cross-section of source and gate region.
Fig. 10. The on-state output characteristics of the 850 V LDMOS.
3. Experimental results Fig. 7. The thickness of the top silicon layer in the drift region.
Fig. 8. The measured results of reverse breakdown characteristics.
drift region can block 860 V voltage, with the increase of thickness to 0.48 lm, blocking voltage decreased to 500 V. Therefore, the thickness of top silicon in drift region must be more uniform so as to achieve a stable high breakdown voltage.
The proposed SOI LDMOS process flow was compatible with conventional CMOS technology, and SOI LDMOS devices were fabricated on Simbond SOI wafer in ASMC company. The SEM crosssection of channel and drift regions were showed in Fig. 6, and the thickness of the top silicon layer in the drift region was measured as illustrated in Fig. 7. It was found that the silicon thickness was about 0.26 lm and was uniform along whole drift region, which verified simulating result’s reliability. Fig. 8 showed the measured results of off state breakdown characteristics, it reached to 852 V. The thermal breakdown points appeared at the circle layout region as shown in Fig. 9. This indicated current crowding effect at the circle region was main reason for breakdown, and the circle region should be further optimized in the following study. The threshold voltage was extracted to be 1.9 V, and the specific on-resistance was 56 X mm2. The field plate technology could be applied to improve the specific on-resistance for the further work. Output characteristics were shown in Fig. 10, where gate bias was changed from 2 V to 5 V. Drain current–Drain bias curves was flat, and negative conductance due to self-heating effects was observed as the voltage increased. The maximal value of drain current was limited to 100 mA due to semiconductor parameter analyzer’s power limitation. In the following work, parallel of several MCUs will be adopted to measure SOI LDMOS with large drain current. 4. Conclusion 850 V high breakdown voltage LDMOS structures were fabricated on Simbond SOI wafers. Breakdown theory analysis and
Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
TCAD simulation demonstrated that the thickness of the top silicon in the drift region and buried oxide layer has great influence on the maximum breakdown voltage of SOI LDMOS. Moreover, the uniform of silicon thickness in the drift region was vital to block high voltage. Using Simbond SOI wafer with 1.5 lm top silicon and 3 lm buried oxide layer, SOI LDMOS devices with 60 lm drift region was successfully fabricated, the off-state breakdown voltage can reached to 850 V, the threshold voltage was 1.9 V, and the specific on-resistance was 56 X mm2. Simbond SOI wafers were good choice to fabricate thin film high voltage SOI LDMOS due to superior uniformity in top silicon and flexibility in the thickness of top silicon and buried oxide layer.
Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 10775166 and No. 61006088) and SNF (09ZR1437700).
105
References [1] F. Udrea, in: IEEE Bipolar/BiCMOS Circuits and Technology Meeting, BCTM, 1997, pp. 74–81. [2] F. Udrea, D. Garner, K. Sheng, Electron. Commun. Eng. J. 12 (1) (2000) 27–40. [3] E. Napoli, in: International Semiconductor Conference, 2006, pp. 3–12. [4] S. Merchant, E. Arnold, H. Baumgart, et al., in: Fifth International Symposium Power Semiconductor Devices and IC’s, 1993, pp. 124–128. [5] Shengdong Hu, Bo Zhang, Zhaoji Li, in: IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, 2008, pp. 1–4. [6] Bo Zhang, Li Zhaoji, Shengdong Hu, Xiaorong Luo, IEEE Trans. Electron Devices 56 (10) (2009) 2327–2334. [7] L. Clavelier, B. Charlet, B. Giffard, M. Roy, in: 33rd Conference on European Solid-State Device Research, ESSDERC, 2003, pp. 497–500. [8] A.G. Revesz, G.A. Brown, H.L. Hughes, J. Electrochem. Soc. 140 (11) (1993) 3222–3229. [9] A.G. Revesz, G.A. Brown, IEEE Trans. Electron Devices 40 (9) (1993) 1700–1705. [10] Chen Meng, PCT Patent PCT/CN/2006/001901. [11] Xing Wei, Aimin Wu, Xiang Wang, J. Vac. Sci. Technol. B 28 (1) (2010) 163–168. [12] Xing Wei, Aimin Wu, Xiang Wang, J. Electrochem. Soc. 57 (1) (2010) H81–H85. [13] S. Merchant, E. Arnold, H. Baumgart, et al., in: Proc. ISPSD, 1991, pp. 31–35. [14] T. Letavic, E. Arnold, M. Simpson, et al., in: Proc. ISPSD, 1997, pp. 49–52. [15] Shengdong Zhang, Johnny K.O. Sin, Tommy M.L. Lai, et al., IEEE Trans. Electron Devices 46 (5) (1999) 1036–1041.
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Realization of 850 V breakdown voltage LDMOS on Simbond SOI Zhongjian Wang a,b,⇑, Xinhong Cheng a, Dawei He a,b, Chao Xia a,b, Dawei Xu a,b, Yuehui Yu a, Dong Zhang c, Yanying Wang c, Yuqiang Lv c, Dawei Gong c, Kai Shao c a State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, PR China b Graduate University of Chinese Academy of Sciences, Beijing 100049, PR China c Technology Development Department, Advanced Semiconductor Manufacturing Corporation Limited, Hongcao Road 385, Shanghai 200233, PR China
a r t i c l e
i n f o
Article history: Received 21 April 2011 Received in revised form 26 September 2011 Accepted 20 October 2011 Available online 12 November 2011 Keywords: SOI Simbond High voltage device LDMOS
a b s t r a c t In this paper, 850 V breakdown voltage LDMOS fabricated on Simbond SOI wafer are reported. Simbond SOI wafers with 1.5 lm top silicon, 3 lm buried oxide layer, and n-type heavy doped handle wafers are used. In order to achieve uniform lateral electric field and shorten the vertical impact ionization integration path simultaneously, an optimized 60 lm drift region implant mask is designed to realize a linearly graded doping profile, and silicon thickness in the drift region is reduced from 1.5 lm to about 0.26 lm by thick field oxide process. CMOS compatible SOI LDMOS processes are designed and implemented successfully. Off-state breakdown voltage of SOI LDMOS can reach 850 V, and the specific on-resistance is 56 X mm2. Experimental results also show the thickness of the top silicon in the drift region has a good uniformity. The performance of SOI LDMOS indicated that Simbond SOI wafers are good choice for thin film high voltage devices. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction High breakdown voltage SOI LDMOS is attractive for using in power ICs because of its excellent isolation performance and small parasitical effect [1,2]. However, the design of exceeded 600 V high voltages devices using traditional RESURF structure on SOI is commonly recognized to be difficult due to the restriction of the low vertical breakdown voltage [3]. Some theory and experimental studies have proved the maximum breakdown voltage of the SOI devices depend mainly on the thickness of SOI layer and buried oxide [4], which is showed in the expression [5,6] as below and Fig. 1. esi and eox are the relative permittivity of silicon and SiO2, respectively,
V B;V ¼
tsi esi 9:783ð21:765 ln tsi Þ t box þ 3:975 þ ln tsi 2 eox
ð1Þ
As shown in Fig. 1, when the BOX is 3 lm or above, realization of 600 V breakdown voltage devices on SOI requires the thickness of top silicon at least above 20 lm or below 0.5 lm. However, for power ICs on a thick SOI layer (>20 lm), dielectric isolation through using trenches filled with dielectric or poly material is complex and costly [7]. Furthermore, for SOI wafers with 1.5 lm top silicon, it is easy to realize full dielectric isolation by trench, ⇑ Corresponding author at: State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050, PR China. E-mail address: [email protected] (Z. Wang). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.10.014
and the top silicon can be reduced to below 0.5 lm by thick field oxide process in order to support high voltage simultaneously. When the top silicon becomes thinner, the uniformity is more important parameter to sustain high voltage. Currently, bonding and SIMOX are two commercial techniques to produce SOI wafers. However, the top Si thickness of bonded SOI wafers is usually more than 5 lm, and the thickness variation is ±0.5 lm. Furthermore, SIMOX SOI suffers from the limited thickness of the buried oxide layer, and the quality of SIMOX is not as good as that of a thermally oxidized SiO2 [8,9]. Simbond SOI technologies [10–12] combine both advantages of conventional SIMOX and wafer bonding technologies, which can produce SOI wafer with superior top silicon uniformity and high quality thick buried oxide layer. Simbond SOI wafer need two Si wafers, A wafer with 3 lm oxide layer on polished side, and B wafer with 120 nm buried oxide layer formed by oxygen ion-implantation. A wafer is bonded to B wafer with a interface of oxide/top silicon, the substrate of B wafer is etched until to buried oxide layer, buried layer is also removed away, then thinning top silicon to achieve an uniform silicon surface. At last, Silicon is epitaxially grown on the uniform silicon surface to achieve 1.5 lm thickness. In this paper, the high voltage device was fabricated on Simbond SOI wafer. Thick field oxide technology was used to thin top silicon in the drift region to 0.26 lm. Process simulation was especially explored to optimize the implanting and annealing parameters for the realization of linearly graded doping profile in the drift region.
Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
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Fig. 1. The maximum breakdown voltage versus the thickness of top silicon. Fig. 4. The doping profile and the electric field distribution in the drift region.
Fig. 2. The structure of 850 V LDMOS transistor.
2. Device structure and fabrication process Simbond SOI wafer with 1.5 lm top silicon and 3 lm buried oxide layer was used for SOI LDMOS fabrication, the handle wafers were n type doped with the resistivity of 0.0008–0.0018 X cm, and the top silicon was p type doped with the resistivity 10–20 X cm. As shown in Fig. 2, SOI LDMOS structures in this work derived from NXP 650V EZ-HV™ LDMOS [13,14]. The surface lateral electric field in drift region can be expressed as [15]:
Ex ðx; 0Þ ¼
tsi esi dNðxÞ t box þ dx esi eo 2 eox qtsi
ð2Þ
N(x) is the impurity concentration in the drift reign, eo is the permittivity of vacuum. In order to achieve a uniform lateral electric field, an optimized 60 lm drift region implant mask was designed to realize a linearly graded doping profile, as showed in Fig. 3. Phosphorus was implanted into the drift region using this mask and followed by annealing drive in at 1200 °C. Thick field oxide was grown onto the drift region and silicon thickness of the drift region was reduced from 1.5 lm to 0.26 lm. P-well was formed by the implanted of boron for threshold voltage adjustment. After gate oxide was grown, polysilicon was deposited by
Fig. 5. The breakdown voltage at different thickness of top silicon.
LPCVD and patterned for gate region. The source, drain and p-body region were formed by high dose implant followed by RTA activation. Finally, the metal and passivation layer were deposited. The numbers of the first line are implanted regions (lm), the numbers of the second line are the distances between implanted regions (lm). The proposed process flow and device performance of the designed LDMOS transistor were simulated by using the mixed numerical two-dimensional TCAD tool Sentaurus. As shown in Fig. 4, the doping concentration in drift region, simulated by use of proposed process flow, increased linearly from channel edge to drain side, the lateral electric field distribution was uniform and no obvious peak appeared at pn junctions. These indicated that proposed process flow can realize linear doping profile and make lateral electric field uniform distribution. The relationship of the breakdown voltage with the thickness of top silicon in the drift region was also simulated and illustrated in Fig. 5. 0.2 lm thickness
Fig. 3. The optimized 60 lm drift region implant mask for linearly graded doping profile.
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Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
Fig. 9. The experimental micrograph of reverse breakdown point.
Fig. 6. The SEM cross-section of source and gate region.
Fig. 10. The on-state output characteristics of the 850 V LDMOS.
3. Experimental results Fig. 7. The thickness of the top silicon layer in the drift region.
Fig. 8. The measured results of reverse breakdown characteristics.
drift region can block 860 V voltage, with the increase of thickness to 0.48 lm, blocking voltage decreased to 500 V. Therefore, the thickness of top silicon in drift region must be more uniform so as to achieve a stable high breakdown voltage.
The proposed SOI LDMOS process flow was compatible with conventional CMOS technology, and SOI LDMOS devices were fabricated on Simbond SOI wafer in ASMC company. The SEM crosssection of channel and drift regions were showed in Fig. 6, and the thickness of the top silicon layer in the drift region was measured as illustrated in Fig. 7. It was found that the silicon thickness was about 0.26 lm and was uniform along whole drift region, which verified simulating result’s reliability. Fig. 8 showed the measured results of off state breakdown characteristics, it reached to 852 V. The thermal breakdown points appeared at the circle layout region as shown in Fig. 9. This indicated current crowding effect at the circle region was main reason for breakdown, and the circle region should be further optimized in the following study. The threshold voltage was extracted to be 1.9 V, and the specific on-resistance was 56 X mm2. The field plate technology could be applied to improve the specific on-resistance for the further work. Output characteristics were shown in Fig. 10, where gate bias was changed from 2 V to 5 V. Drain current–Drain bias curves was flat, and negative conductance due to self-heating effects was observed as the voltage increased. The maximal value of drain current was limited to 100 mA due to semiconductor parameter analyzer’s power limitation. In the following work, parallel of several MCUs will be adopted to measure SOI LDMOS with large drain current. 4. Conclusion 850 V high breakdown voltage LDMOS structures were fabricated on Simbond SOI wafers. Breakdown theory analysis and
Z. Wang et al. / Microelectronic Engineering 91 (2012) 102–105
TCAD simulation demonstrated that the thickness of the top silicon in the drift region and buried oxide layer has great influence on the maximum breakdown voltage of SOI LDMOS. Moreover, the uniform of silicon thickness in the drift region was vital to block high voltage. Using Simbond SOI wafer with 1.5 lm top silicon and 3 lm buried oxide layer, SOI LDMOS devices with 60 lm drift region was successfully fabricated, the off-state breakdown voltage can reached to 850 V, the threshold voltage was 1.9 V, and the specific on-resistance was 56 X mm2. Simbond SOI wafers were good choice to fabricate thin film high voltage SOI LDMOS due to superior uniformity in top silicon and flexibility in the thickness of top silicon and buried oxide layer.
Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 10775166 and No. 61006088) and SNF (09ZR1437700).
105
References [1] F. Udrea, in: IEEE Bipolar/BiCMOS Circuits and Technology Meeting, BCTM, 1997, pp. 74–81. [2] F. Udrea, D. Garner, K. Sheng, Electron. Commun. Eng. J. 12 (1) (2000) 27–40. [3] E. Napoli, in: International Semiconductor Conference, 2006, pp. 3–12. [4] S. Merchant, E. Arnold, H. Baumgart, et al., in: Fifth International Symposium Power Semiconductor Devices and IC’s, 1993, pp. 124–128. [5] Shengdong Hu, Bo Zhang, Zhaoji Li, in: IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, 2008, pp. 1–4. [6] Bo Zhang, Li Zhaoji, Shengdong Hu, Xiaorong Luo, IEEE Trans. Electron Devices 56 (10) (2009) 2327–2334. [7] L. Clavelier, B. Charlet, B. Giffard, M. Roy, in: 33rd Conference on European Solid-State Device Research, ESSDERC, 2003, pp. 497–500. [8] A.G. Revesz, G.A. Brown, H.L. Hughes, J. Electrochem. Soc. 140 (11) (1993) 3222–3229. [9] A.G. Revesz, G.A. Brown, IEEE Trans. Electron Devices 40 (9) (1993) 1700–1705. [10] Chen Meng, PCT Patent PCT/CN/2006/001901. [11] Xing Wei, Aimin Wu, Xiang Wang, J. Vac. Sci. Technol. B 28 (1) (2010) 163–168. [12] Xing Wei, Aimin Wu, Xiang Wang, J. Electrochem. Soc. 57 (1) (2010) H81–H85. [13] S. Merchant, E. Arnold, H. Baumgart, et al., in: Proc. ISPSD, 1991, pp. 31–35. [14] T. Letavic, E. Arnold, M. Simpson, et al., in: Proc. ISPSD, 1997, pp. 49–52. [15] Shengdong Zhang, Johnny K.O. Sin, Tommy M.L. Lai, et al., IEEE Trans. Electron Devices 46 (5) (1999) 1036–1041.