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A novel linear-logarithmic readout integrated circuit with high dynamic range
Journal Pre-proofs A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range P.S. Chu, H.L. Chen, R.J. Ding PII: DOI: Reference:
S1350-4495(19)30830-8 https://doi.org/10.1016/j.infrared.2019.103158 INFPHY 103158
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Infrared Physics & Technology
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Please cite this article as: P.S. Chu, H.L. Chen, R.J. Ding, A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range, Infrared Physics & Technology (2019), doi: https://doi.org/10.1016/j.infrared. 2019.103158
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A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range P.S Chua,b , H.L Chena , R.J Ding∗a a
Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China b University of Chinese Academy of Science, Beijing 100049, China
Abstract This paper presents a novel pixel structure of readout integrated circuit (ROIC) for infrared focal array plane (IRFPA). The pixel can operate in the linear-logarithmic mode to reach high dynamic range. The pixel is based on the buffered direct injection (BDI) as the input cell. The logarithmic response is realized by adding two additional diode-connected MOSFETs. The pixel can automatically switch between the linear and the logarithmic mode. The threshold voltage of the mode-switching is controlled by a given voltage. A linear-logarithmic test chip consisting of a small pixel array has been designed and fabricated using Global Foundry 0.18µm 1P6M process. A medium wave infrared detector has been hybridized to the chip. The experimental results show that the logarithmic sensitivity is 86 mV/dec. The dynamic range of the chip is higher than 137 dB and the dynamic range of the chip with a detector is greater than 102 dB. Keywords: ROIC, linear-logarithmic response, high dynamic range PACS: 07.57.Hm, 07.05.Tp, 07.57.Kp 1. Introduction IRFPA has been widely used in both military and civilian fields such as weather forecasting[1], astronomy[2], missile defense system, target detection[3] etc. Currently, the third-generation IRFPA are being developed, which has better performances in quite a few aspects[4]. Medium wave infrared (MWIR) and long wave infrared (LWIR) contain more abundant information of the background and the object when it is compared to short wave infrared (SWIR) on earth. For the aim of achieving higher sensitivity and higher contrast ratio, MWIR detectors and LWIR detectors have been more to consider in use. Dynamic range is one of the most important parameters of IRFPA. An IR system with high dynamic range can acquire the weak signals without the loss of the strong signals when it comes to an environment with a large temperature difference.This advantage makes high dynamic range find itself playing quite a significant role in many applications. For example, a target detecting system with high dynamic range can handle the situation that has complex targets to identify or detect the fast-moving incoming hot targets in the cold background such as a plane in the winter night. The signal level depends on the distance between the plane and the detectors. The signal increases as the distance decreases. So, the detectors must detect the low-level signals of the plane at a long distance and do not saturate under high-level signals at a closer distance. There are serval ways to improve the dynamic range. The conventional way is to increase the charge capacity of readout integrated circuit (ROIC) with a larger integration capacitor. Preprint submitted to Infrared Physics & Technology
December 9, 2019
But it is limited by the area of pixel. So a self-selected capacitor ROIC has been reported[5]. Another way is the digital-pixel ROIC[6–8]. This technique enables the charge capacity up to 109 e− and the dynamic range above 90 dB. These methods all make the circuit more complex and the digital-pixel ROIC requires more advanced CMOS technology node. Human eyes are a system that responds light intensity logarithmically[9, 10]. But traditional logarithmic response scheme suffers from some disadvantages including the lack of output voltage swing and poor response to low-level signals. To improve these problems, liner-logarithmic response scheme[11–17] is proposed. The common linear-logarithmic CIS is shown in Figure 1. It can reach high dynamic range with simple operation and lower circuit complexity. It’s mostly been used in the CMOS image sensors (CIS) that published in literature.
Figure 1: Linear-logarithmic CMOS image sensor
This paper proposes a novel high dynamic range technique for IRFPA ROIC by combining linear-logarithmic response scheme used in CIS and the conventional buffered direct injection (BDI) used in ROIC input circuits as shown. The dynamic range of ROIC can be adjusted easily by using an applied voltage. This structure can obtain the advantages of the high signalto-noise ratio (SNR) at the linear response and extend the dynamic range by the logarithmic response. So the ROIC can acquire the detailed information of the low temperature objects and preserve the information of the high temperature objects in one infrared image. The proposed technique was designed using Global Foundry 0.18µm 1P6M process and its performances were evaluated. The following sections are organized in such an order. The proposed pixel and test chip architecture are described in Section 2 and Section3. Section 4 gives the measurement results of the test chip. Finally, Section 5 presents the conclusions. 2. Proposed pixel architecture In the infrared detectors, the signal-to-noise ratio (SNR) √ is influenced by the detectors’ photon shot noise. SNR can be expressed as: SN R = N/ N , where N is the number of the electrons collected by ROIC. The photon shot noise will decrease and SNR will be higher if the integration time and the number of the electrons, which is collected by the ROIC, increased in the traditional linear response. The logarithmic response relies on the logarithmic relationship of the MOSFET, which works in the subthreshold region. The advantage of the logarithmic response is that it can easily extend the infrared detectors’ detectable temperature range to get high dynamic range. 2
But the disadvantage should also be discussed. The input photocurrent does not need to integrate to get the output signal at the logarithmic mode. So, the logarithmic response technology for IRFPA will suffer from the lack of SNR. Additionally, if the input photocurrent was too low, the MOSFETs for logarithmic response will go into the cut-off region. This situation will cause no response to weak-level signals. To solve these problems, the traditional linear response technology must be leaded into the logarithmic-mode-only circuit in IRFPA. So, a new linear-logarithmic structure of ROIC for IRFPA is introduced. This technique can combine the advantages of the two working modes. Figure 2 shows the proposed pixel that capable of both linear and logarithmic operation. It contains a BDI input circuit, a sample-hold structure and a source-follower buffer (Msf ), which is the same as the linear response pixel. But in comparison with the conventional BDI input circuit, the proposed architecture adds two diode-connected MOSFETs (M1 , M2 ), which its gate connected with the drain. These two transistors let the pixel work at the logarithmic response with larger output swing, when V1 exceeds the threshold voltage controlled by Vlog . And the dynamic rang is adjustable by the given voltage Vlog .
Figure 2: Linear-logarithmic CMOS image sensor
The input stage is a bridge between the ROIC and the detectors. It needs to integrate and amplify the photocurrent generated by the detectors, keeps a constant bias voltage of the detector and has a high injection efficiency. The design of the input stage in the pixel is crucial. There are various types of the input stage circuit, such as Direct Inject (DI), Buffered Direct Inject (BDI), Capacitor Feedback Transimpedance Amplifier (CTIA). DI is the simplest input stage and gives an outstanding performance in terms of the power consumption, noise and area usage. But the injection efficiency is lower than BDI and CTIA. CTIA is not suitable for the logarithmic response to realize because M1 and M2 cannot be put into. So, BDI is selected. The injection efficiency of BDI is: ηBDI =
1 1+
1 Rdet gm Av
(1)
Where Rdet is the resistance of the detector, gm is the trans-conductance of the input MOSFET (Min ) and Av is the gain of the operational amplifier in BDI. The input MOSFET (Min ) works 3
in the subthreshold region, gm is not related to the size of the MOSFET. In order to have a better performance of the injection efficiency, the OPA needs to have a higher gain. The pixel also supports integration after read (ITR) mode and integration while read (IWR) mode. The sample and hold capacitor (Csh ) can be used as the integration capacitor while ITR mode is chosen, so that the pixel can handle more electric charge at the linear response. The timing diagram is shown in Figure 3.
Figure 3: Timing diagram of the pixel:(a)IWR and (b)ITR
The pixel operation consists of two phases: reset phase and integration phase. Here takes the IWR mode for detailed explanation. The pixel starts with the reset phase. In the reset phase, the reset transistor Mrst is on and V1 is pulled up to the power voltage VDD. The integration capacitor Cint is reset. When the reset phase completes, Mrst is set to off and the integration phase begins. In the course of the integration phase, Cint discharges and V1 decreases. At low signal condition, V1 does not reach the threshold (Vlog − 2|Vth |, where Vth is the threshold of M1 and M2 ) and M1 , M2 is off. The pixel is in the linear response. V1 is proportional to the current (Iph ) generated by infrared detector and integration time (tint ) as shown in (2): V1 = V DD −
Iph tint , V1 >Vlog − |2Vth | Cint
(2)
At high signal condition, V1 reach the threshold controlled by given voltage Vlog . The M1 and M2 are on. The pixel turns into logarithmic response. The transistors (M1 , M2 ) are working in the subthreshold region. If neglecting the body effect, the relationship between drain-to-source current (Ids ) and Vgs as follows[18]: Ids = I0 e
κVgs VT
(3)
where I0 is a constant that represents the zero-bias current for the given device, VT = kT /q is the thermal voltage, and κ measures the effectiveness of the gate potential in controlling the channel current. In order to eliminate the body effect, the M1 and M2 ’s substrates should connect to their sources (Vbs = 0). As the tape-out process been chosen is a N-well/P-sub process, NMOS cannot realize that. So M1 and M2 are PMOS in separated N-well. Equation (3) can be converted to find the logarithmic relationship between Vgs and Ids as shown below: VT Ids Vgs = ln( ) (4) κ I0 In the pixel proposed in Figure 2, the transfer function of V1 -Iph is: V1 = Vlog −
2VT Iph ln( ), V1 ≤ Vlog − |2Vth | κ I0 4
(5)
According to equation (2) and equation (5), the voltage swing of linear mode and logarithmic mode is tunable by the Vlog voltage. The voltage swing of the BDI in the linear mode is V DD − Vlog − |2Vth |. The dynamic range (DR) of the linear-logarithmic pixel is defined as below[13]: DR = DRlinear + DRlog = 20log(
Vlin swing Vlog swing ) + 20 Vlin noise Vlog sen
(6)
where Vlin swing , Vlin noise is the output swing and the output noise of the linear response respectively. And Vlog swing is the output swing of the logarithmic response, Vlog sen is the sensitivity of the logarithmic response. The two MOSFETs (M1 and M2 ) for logarithmic response is to enlarge the output swing in the logarithmic mode. The output swing of the logarithmic response of two MOSFETs is twice as much as one MOSFET and will improve the dynamic range. But if the number went beyond two, the output swing of the logarithmic response will be limited by other factors such as the source follower and the output buffer and so on. Besides this, the output swing of the logarithmic response is also restricted by the largest changing voltage of keeping M1 and M2 working in the subthreshold region. If the photocurrent was large enough, Vgs will be much greater than the threshold voltage of M1 and M2 . Because of the shortcut between gate and drain, Vgs = Vds . Then, Vds > Vgs − Vth , M1 and M2 will go into the saturation region and the relationship between V1 and Iph will no longer be logarithmic. Another way to improve the dynamic range is to lower the sensitivity of the logarithmic response. Vlog sen is influenced by the coefficient VT /κ. VT is a constant due to a constant working temperature and the influencing factor is κ. In BSIM3v3 model, κ is a function of the effective channel length and the interface state density. The relationship between 1/κ and the effective channel length is exponential. So, the length of M1 and M2 should be small enough. But in order to reduce the influence of the channel length modulation effect, the length of M1 and M2 should be greater than 1 µm. Finally, the W/L of M1 and M2 is optimized to 3 µm/1 µm. 3. Circuit Implementation The proposed pixel was designed using Global Foundry 0.18µm 1P6M standard Mixedsignal CMOS process, and simulated by using the Cadence Spectre. The power supply voltage is 3.3 V. Working temperature is 77 K because the HgCdTe detector needs to work at 77 K. It is also implemented by a test chip. The test chip contains 16×1 pixel array, a shift register module, a bias module and an output buffer as shown in Figure 4. The pixel pitch is 30 µm. The shift register is a module generates the signals to scan the output voltage of each pixel and to control the readout sequence and the readout rate. The function of the bias module is to produce the bias current for the operational amplifier of the pixel and the output buffer. The layout of the test chip is shown in Figure 5. The total chip size is 3 × 3 mm due to the foundry’s requirement of Multi Project Wafer (MPW) . The core cell area is 480×250 µm. For an easier way to connect to the detector, every pixel’s input port is connected to a separated PAD. 3.1. Pixel design The pixel schematic has been shown in Figure 2. In the pixel, the OPA in the BDI is a two-stage op amp. It causes the bigger area usage but can get very high gain performance. 5
Figure 4: Block diagram of the test chip
Figure 5: Layout of the test chip
The simulation results show that the gain is up to 102.6 dB. If the Rdet = 10 M Ω, the injection efficiency is higher than 99% according to the simulation. The capacitance of the integration capacitor Cint is 2 pF to get a large charge capacity. The sample and hold capacitor Csh should be carefully designed. During the sampling time, the electrons transfer from Cint to Csh . The transfer process obeys the law of charge conservation. So, the relationship between the V1 and V2 is: V2 = CintCint V . The smaller capacitance of +Csh 1 Csh , the higher gain of the sample and hold structure. But because of the sample and hold switch, there exists the KTC noise. The KTC noise is Vn2 KT C = kT /Csh . The KTC noise is bigger when Csh is lower. Here in the design, Csh = 200f F is chosen for better output swing performance. This choice leads to Vsh = V1 /1.1 ≈ 0.91V1 . The gain of a source follower is below one due to the body effect. The size of Msf is optimized to W/L = 7 µm/0.35 µm to get maximum gain and linearity. Figure 6 shows the layout of the pixel and particularly zooms in to reveal the significant transistors M1 and M2 .
6
Figure 6: Layout of the pixel
3.2. Output buffer design The output buffer should have high slew rate, low noise, enough output voltage range. To achieve those parameters, a unity-gain buffer consisting of a five-transistors differential amplifier has been designed. The size of the five transistors are large enough to reduce the 1/f noise. The simulation results show that gain is 53.7 dB, phase margin is 82.4 degree and CMRR is 81.2 dB under load capacitance of 25 pF. The schematic and the layout of the output buffer is presented in Figure 7. The layout is symmetrical to lower the mismatch of the differential transistors.
Figure 7: (a)Schematic and (b)Layout of the output buffer
3.3. Simulation results The photocurrent used to simulate is from 0 nA to 1 µA. Figure 8 shows the simulation results of the photocurrent response curves under different Vlog voltage. The pixel is working at the IWR mode. The trend of the logarithmic response is not influenced by the Vlog voltage. The turning point between linear response and logarithmic response can be controlled by Vlog as expected. The chip’s output voltage Vout is compressed, compared to the V1 voltage, because of the gain (< 1) of the sample and hold circuit, the source follower. For the purpose of finding the maximum output swing of the logarithmic response, the simulated photocurrent is extended to 20 µA under circumstances of Vlog = 3.3 V . The result is presented in Figure 9. The working region of M1 and M2 changes from subthreshold to saturation when Iph ≈ 1.2 µA from the report of the operation points in the Cadence Spectre. 7
Figure 8: Simulated response curves of the proposed pixel
After analyzing the simulation data in MATLAB, the result confirms the conclusion. The maximum output swing of the logarithmic response is about 0.4 V.
Figure 9: Further simulation for Vlog = 3.3 V
4. Experimental results The test chip is hybridized to a medium wave infrared (MWIR) detectors and set along with a custom designed printed circuit board (PCB). The PCB is assembled in a laboratory Dewar which can operate with liquid nitrogen (N2 ). A special test board based on the National Instrument PXI system for the test chip has been carefully designed. A custom LabVIEW software on PC has been used to control the PXI system to provide the timed signals (NI PXI 6552) to the test chip and acquire data (NI PXI 5122) from the test chip. The acquired data is processed by MATLAB on a PC. The test principle diagram and the tested PCB with a HgCdTe detector are demonstrated in Figure 10 and Figure 11. 4.1. Current source test A Keithley 2636A Source Meter Unit has been used to produce high precision and programmable current. The test chip can be set to provide the pixel with the current as the 8
Figure 10: Test block diagram
Figure 11: Tested chip in the Dewar
photocurrent. In this configuration, the linear-logarithmic response to the input current can be measured and calculated. The programmable current ranges from 0 to 1 µA and the integration time is 500 µs. Figure 12 shows the results of the output voltage to the programmable current curve. Figure 12 confirms the proposed pixel operates in linear-logarithmic response according to the simulation results and the expectations. In the linear response, the voltage output swing is 0.42 V, 0.61 V and 0.80 V when Vlog is 3.3 V, 3.0 V and 2.7 V. And the curves are very similar under different Vlog voltage. This means that the Vlog voltage can decide the turning point between the linear mode and logarithmic mode without affecting the output of the linear mode. In the logarithmic response, the sensitivity is not influenced by the Vlog voltage. Furthermore, the dynamic range is tunable by the Vlog voltage. In our design, Vlin noise is 0.32 mV and Vlog sen is 86 mV/dec. The output voltage ranges from 0.14 V to 1.24 V (when Iph = 0). The lowest output is limited by the voltage transfer of the analog chain such as sample-hold, buffer. So, the total output swing is 1.1 V. The tested output voltage is lower than the results of the simulation due to the parasitic of the
9
Figure 12: Measured current response curves of the test chip
Figure 13: Further test for Vlog = 3.3 V
layout. To measure the maximum output swing of logarithmic response, the input current is extended to 10 µA and Vlog is set to 3.3 V. The measurement result is presented in Figure 13. When input current is greater than 3 µA, the relationship between Vout and input current is not logarithmic. So, the maximum output swing of logarithmic response is about 0.34 V. The dynamic range of the chip under different Vlog voltage is shown in Table 1. When Vlog = 2.7 V , the output swing in logarithmic mode is limited to 0.30 V due to the lowest output voltage of the chip. Table 1: Dynamic range of the chip
Vlog /V 3.3 3.0 2.7
Vlin swing /V 0.42 0.61 0.80
Vlog swing /V 0.34 0.34 0.30
DRlinear /dB 62 65 68
10
DRlog /dB 79 79 69
DR/dB 141 144 137
4.2. Detector test The chip is set to use the photocurrent generated by the coupled MWIR HgCdTe detector as the input signal. A blackbody is used to produce the IR radiation. The temperature of the blackbody ranges from 280 K to 675 K. The detector’s bias voltage is set to -50 mV. According to the Stefan-Boltzmann law, the blackbody emissive power into the pixel is: P =
σT 4 AD L 2 4( D ) +1
(7)
where σ = 5.673 × 10−12 [W/(cm2 · K 4 ) is Stefan constant, T is the temperature of the blackbody, AD is the size of the pixel. D is the blackbody’s output aperture. L is the distance between the pixel and the blackbody’s output aperture. So the blackbody emissive power is between 5.25 × 10−9 W and 1.77 × 10−7 W . Figure 14 shows the dark current of the used HgCdTe detector and the relationship between the blackbody power and the HgCdTeconverted photocurrent,tested by a Keithley 6430 micro-current source meter. The dark current is 2.259 × 10−13 A and the resistance is 1.422 × 1011 Ω at -50 mV bias. The photocurrent is 6 × 10−10 A to 5 × 10−8 A.
Figure 14: (a) I − V and R − V curve (b) fitted Iph − P curve
Figure 15: Measured response curves of the tested chip with detector
Figure 15 shows the measured results of the detector test. It confirms the proposed pixel operates in linear-logarithmic response with an IR detector. The output noise of the linear 11
mode, Vlin noise , is 0.45 mV, a little bit higher than the current source test due to the noise of the detector. The logarithmic sensitivity is the same as the result in the section 4.1.The output voltage swing of logarithmic response is 0.18 V, 0.16 V and 0.14 V at Vlog=3.3 V, 3.0 V and 2.7 V. This is due to the difference of the voltage of linear-logarithmic-mode transfer. The measured highest dynamic range is 102 dB. In addition, because of the restriction of the used blackbody’s temperature range, the maximum output swing of logarithmic mode cannot be reached in test. If the blackbody’s temperature was high enough to make the output swing of the test chip achieving to the full output swing in the Table 1, the highest dynamic range will be 141 dB.The performance parameters of the tested chip with detector are shown in Table 2. The linear mode responsivity and logarithmic sensitivity of all pixels in the test chip under Vlog = 3.3 V is shown in Figure 16. The fixed patter noise and non-uniformity in logarithmic mode is larger than that inx linear mode. The explanation to this phenomenon is the mismatch of the M1 and M2 between different pixels. The logarithmic response relies on these two MOSFETs. So, for further improvement of the linear-logarithmic ROIC, the technics of non-uniformity correction and FPN reduction should be added into the circuit. Table 2: The performance parameters of the chip with a detector
Technology Power supply Dynamic range(measured) Linear mode responsivity Linear mode Detectivity* Linear mode noise Logarithmic sensitivity Linear mode Non-uniformity of response Log mode Linear mode Fixed Pattern Noise Log mode Power dissipation
0.18µm 1P6M 3.3 V 102 dB 4.01 × 107 V /W 4.51 × 108 cm · Hz 1/2 /W 0.45 mV 86 mV/dec 3.3% 6.2% 2.5 mV 5.7 mV 2.64 mW
Figure 16: The linear mode responsivity and logarithmic sensitivity
12
5. Conclusion A new design of the linear-logarithmic pixel with high dynamic range was proposed in this paper. The pixel operates in the linear mode at low input photocurrent and automatically switch to the logarithmic mode at lager input photocurrent. The simulation results has confirmed the efficacy of the design. By combining the linear response and the logarithmic response in one pixel, the dynamic range of the test chip is much higher than 137 dB. Along with a MWIR detectors, the dynamic range achieves 102 dB. It shows that the proposed pixel structure can provide a promising solution to the high dynamic range IRFPA ROIC. 6. Reference [1] K. Barnes, R. P. Davis, P. Knowles, N. Shorrocks, Infrared detectors for earth observation, in: Xiong, XJ and Kuriakose, SA and Kimura, T (Ed.), Earth Observing Missions and Sensors: Development, Implementation, and Characterization IV, Vol. 9881 of Proceedings of SPIE, SPIE; Indian Space Res Org; Minist Earth Sci; Natl Aeronaut & Space Adm, SPIE-INT SOC Optical Engineering, 1000 20th ST, Po Box 10, Bellingham, WA 98227-0010 USA, 2016, Conference on Earth Observing Missions and Sensors - Development, Implementation, and Characterization IV, Indian Soc Remote Sensing, New Delhi, INDIA, APR 04-07, 2016. doi:10.1117/12.2229580. [2] J. K. Davies, G. S. Wright, A. C. H. Glasse, Solar system observations with MIRI, the mid infrared instrument on the James Webb Space Telescope, Earth Moon and Planets 105 (2-4) (2009) 73–80, Workshop on Future Ground-based Solar System Research Synergies with Space Probes and Space Telescope, Portoferraio, Italy, SEP 08-12, 2008. doi:10.1007/s11038-009-9313-z. [3] A. Goldberg, T. Fischer, Z. Derzko, Application of dual-band infrared focal plane arrays to tactical and strategic military problems, in: Andresen, BF and Fulop, GF and Strojnik, M (Ed.), Infrared Technology and Applications XXV111, PTS 1 AND 2, Vol. 4820 of Proceedings of the Society of Photo-Optical Intrumentation Engineers (SPIE), SPIE, SPIE-INT SOC Optical Engineering, 1000 20th ST, Po Box 10, Bellingham, WA 98227-0010 USA, 2003, pp. 500–514, Conference on Infrared Technology and Applications XXVIII, SEATTLE, WA, JUL 07-11, 2002. doi:10.1117/12.451014. [4] A. Rogalski, J. Antoszewski, L. Faraone, Third-generation infrared photodetector arrays, Journal of Applied Physics 105 (9). doi:10.1063/1.3099572. [5] Y. S. Kim, D. H. Woo, Y. M. Jo, S. G. Kang, H. C. Lee, Low-noise and wide-dynamicrange ROIC with a self-selected capacitor for SWIR focal plane arrays, IEEE Sensors Journal 17 (1) (2017) 179–184. doi:10.1109/JSEN.2016.2625322. [6] M. T. E. D. B. S. B. L. M. P. C. J.-P. Z. P. M. M. Z. J.-C. P. Fabrice Guellec, Arnaud Peizerat, A 25m pitch lwir focal plane array with pixel-level 15-bit adc providing high well capacity and targeting 2mk netd (2010). doi:10.1117/12.849684. URL https://doi.org/10.1117/12.849684 [7] H. Kayahan, M. Yazici, O. Ceylan, Y. Gurbuz, A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise, Infrared Physics & Technology 63 (2014) 125–132. doi:10.1016/j.infrared.2013.12.013. 13
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Highlights:
A novel linear-logarithmic pixel for IRFPA have been proposed.
Logarithmic response is based on two additional diode-connected MOSFETs.
Pixel can auto switch between linear and logarithmic response.
Dynamic range is higher than 102 dB and logarithmic response is 86 mV/dec.
Conflict of Interest We declare that we have no financial and personal relationships with other people or organizations that can inappropriately influence our work, there is no professional or other personal interest of any nature or kind in any product, service and/or company that could be construed as influencing the position presented in, or the review of, the manuscript entitled, “A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range”
S1350-4495(19)30830-8 https://doi.org/10.1016/j.infrared.2019.103158 INFPHY 103158
To appear in:
Infrared Physics & Technology
Received Date: Revised Date: Accepted Date:
10 October 2019 9 December 2019 10 December 2019
Please cite this article as: P.S. Chu, H.L. Chen, R.J. Ding, A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range, Infrared Physics & Technology (2019), doi: https://doi.org/10.1016/j.infrared. 2019.103158
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A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range P.S Chua,b , H.L Chena , R.J Ding∗a a
Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China b University of Chinese Academy of Science, Beijing 100049, China
Abstract This paper presents a novel pixel structure of readout integrated circuit (ROIC) for infrared focal array plane (IRFPA). The pixel can operate in the linear-logarithmic mode to reach high dynamic range. The pixel is based on the buffered direct injection (BDI) as the input cell. The logarithmic response is realized by adding two additional diode-connected MOSFETs. The pixel can automatically switch between the linear and the logarithmic mode. The threshold voltage of the mode-switching is controlled by a given voltage. A linear-logarithmic test chip consisting of a small pixel array has been designed and fabricated using Global Foundry 0.18µm 1P6M process. A medium wave infrared detector has been hybridized to the chip. The experimental results show that the logarithmic sensitivity is 86 mV/dec. The dynamic range of the chip is higher than 137 dB and the dynamic range of the chip with a detector is greater than 102 dB. Keywords: ROIC, linear-logarithmic response, high dynamic range PACS: 07.57.Hm, 07.05.Tp, 07.57.Kp 1. Introduction IRFPA has been widely used in both military and civilian fields such as weather forecasting[1], astronomy[2], missile defense system, target detection[3] etc. Currently, the third-generation IRFPA are being developed, which has better performances in quite a few aspects[4]. Medium wave infrared (MWIR) and long wave infrared (LWIR) contain more abundant information of the background and the object when it is compared to short wave infrared (SWIR) on earth. For the aim of achieving higher sensitivity and higher contrast ratio, MWIR detectors and LWIR detectors have been more to consider in use. Dynamic range is one of the most important parameters of IRFPA. An IR system with high dynamic range can acquire the weak signals without the loss of the strong signals when it comes to an environment with a large temperature difference.This advantage makes high dynamic range find itself playing quite a significant role in many applications. For example, a target detecting system with high dynamic range can handle the situation that has complex targets to identify or detect the fast-moving incoming hot targets in the cold background such as a plane in the winter night. The signal level depends on the distance between the plane and the detectors. The signal increases as the distance decreases. So, the detectors must detect the low-level signals of the plane at a long distance and do not saturate under high-level signals at a closer distance. There are serval ways to improve the dynamic range. The conventional way is to increase the charge capacity of readout integrated circuit (ROIC) with a larger integration capacitor. Preprint submitted to Infrared Physics & Technology
December 9, 2019
But it is limited by the area of pixel. So a self-selected capacitor ROIC has been reported[5]. Another way is the digital-pixel ROIC[6–8]. This technique enables the charge capacity up to 109 e− and the dynamic range above 90 dB. These methods all make the circuit more complex and the digital-pixel ROIC requires more advanced CMOS technology node. Human eyes are a system that responds light intensity logarithmically[9, 10]. But traditional logarithmic response scheme suffers from some disadvantages including the lack of output voltage swing and poor response to low-level signals. To improve these problems, liner-logarithmic response scheme[11–17] is proposed. The common linear-logarithmic CIS is shown in Figure 1. It can reach high dynamic range with simple operation and lower circuit complexity. It’s mostly been used in the CMOS image sensors (CIS) that published in literature.
Figure 1: Linear-logarithmic CMOS image sensor
This paper proposes a novel high dynamic range technique for IRFPA ROIC by combining linear-logarithmic response scheme used in CIS and the conventional buffered direct injection (BDI) used in ROIC input circuits as shown. The dynamic range of ROIC can be adjusted easily by using an applied voltage. This structure can obtain the advantages of the high signalto-noise ratio (SNR) at the linear response and extend the dynamic range by the logarithmic response. So the ROIC can acquire the detailed information of the low temperature objects and preserve the information of the high temperature objects in one infrared image. The proposed technique was designed using Global Foundry 0.18µm 1P6M process and its performances were evaluated. The following sections are organized in such an order. The proposed pixel and test chip architecture are described in Section 2 and Section3. Section 4 gives the measurement results of the test chip. Finally, Section 5 presents the conclusions. 2. Proposed pixel architecture In the infrared detectors, the signal-to-noise ratio (SNR) √ is influenced by the detectors’ photon shot noise. SNR can be expressed as: SN R = N/ N , where N is the number of the electrons collected by ROIC. The photon shot noise will decrease and SNR will be higher if the integration time and the number of the electrons, which is collected by the ROIC, increased in the traditional linear response. The logarithmic response relies on the logarithmic relationship of the MOSFET, which works in the subthreshold region. The advantage of the logarithmic response is that it can easily extend the infrared detectors’ detectable temperature range to get high dynamic range. 2
But the disadvantage should also be discussed. The input photocurrent does not need to integrate to get the output signal at the logarithmic mode. So, the logarithmic response technology for IRFPA will suffer from the lack of SNR. Additionally, if the input photocurrent was too low, the MOSFETs for logarithmic response will go into the cut-off region. This situation will cause no response to weak-level signals. To solve these problems, the traditional linear response technology must be leaded into the logarithmic-mode-only circuit in IRFPA. So, a new linear-logarithmic structure of ROIC for IRFPA is introduced. This technique can combine the advantages of the two working modes. Figure 2 shows the proposed pixel that capable of both linear and logarithmic operation. It contains a BDI input circuit, a sample-hold structure and a source-follower buffer (Msf ), which is the same as the linear response pixel. But in comparison with the conventional BDI input circuit, the proposed architecture adds two diode-connected MOSFETs (M1 , M2 ), which its gate connected with the drain. These two transistors let the pixel work at the logarithmic response with larger output swing, when V1 exceeds the threshold voltage controlled by Vlog . And the dynamic rang is adjustable by the given voltage Vlog .
Figure 2: Linear-logarithmic CMOS image sensor
The input stage is a bridge between the ROIC and the detectors. It needs to integrate and amplify the photocurrent generated by the detectors, keeps a constant bias voltage of the detector and has a high injection efficiency. The design of the input stage in the pixel is crucial. There are various types of the input stage circuit, such as Direct Inject (DI), Buffered Direct Inject (BDI), Capacitor Feedback Transimpedance Amplifier (CTIA). DI is the simplest input stage and gives an outstanding performance in terms of the power consumption, noise and area usage. But the injection efficiency is lower than BDI and CTIA. CTIA is not suitable for the logarithmic response to realize because M1 and M2 cannot be put into. So, BDI is selected. The injection efficiency of BDI is: ηBDI =
1 1+
1 Rdet gm Av
(1)
Where Rdet is the resistance of the detector, gm is the trans-conductance of the input MOSFET (Min ) and Av is the gain of the operational amplifier in BDI. The input MOSFET (Min ) works 3
in the subthreshold region, gm is not related to the size of the MOSFET. In order to have a better performance of the injection efficiency, the OPA needs to have a higher gain. The pixel also supports integration after read (ITR) mode and integration while read (IWR) mode. The sample and hold capacitor (Csh ) can be used as the integration capacitor while ITR mode is chosen, so that the pixel can handle more electric charge at the linear response. The timing diagram is shown in Figure 3.
Figure 3: Timing diagram of the pixel:(a)IWR and (b)ITR
The pixel operation consists of two phases: reset phase and integration phase. Here takes the IWR mode for detailed explanation. The pixel starts with the reset phase. In the reset phase, the reset transistor Mrst is on and V1 is pulled up to the power voltage VDD. The integration capacitor Cint is reset. When the reset phase completes, Mrst is set to off and the integration phase begins. In the course of the integration phase, Cint discharges and V1 decreases. At low signal condition, V1 does not reach the threshold (Vlog − 2|Vth |, where Vth is the threshold of M1 and M2 ) and M1 , M2 is off. The pixel is in the linear response. V1 is proportional to the current (Iph ) generated by infrared detector and integration time (tint ) as shown in (2): V1 = V DD −
Iph tint , V1 >Vlog − |2Vth | Cint
(2)
At high signal condition, V1 reach the threshold controlled by given voltage Vlog . The M1 and M2 are on. The pixel turns into logarithmic response. The transistors (M1 , M2 ) are working in the subthreshold region. If neglecting the body effect, the relationship between drain-to-source current (Ids ) and Vgs as follows[18]: Ids = I0 e
κVgs VT
(3)
where I0 is a constant that represents the zero-bias current for the given device, VT = kT /q is the thermal voltage, and κ measures the effectiveness of the gate potential in controlling the channel current. In order to eliminate the body effect, the M1 and M2 ’s substrates should connect to their sources (Vbs = 0). As the tape-out process been chosen is a N-well/P-sub process, NMOS cannot realize that. So M1 and M2 are PMOS in separated N-well. Equation (3) can be converted to find the logarithmic relationship between Vgs and Ids as shown below: VT Ids Vgs = ln( ) (4) κ I0 In the pixel proposed in Figure 2, the transfer function of V1 -Iph is: V1 = Vlog −
2VT Iph ln( ), V1 ≤ Vlog − |2Vth | κ I0 4
(5)
According to equation (2) and equation (5), the voltage swing of linear mode and logarithmic mode is tunable by the Vlog voltage. The voltage swing of the BDI in the linear mode is V DD − Vlog − |2Vth |. The dynamic range (DR) of the linear-logarithmic pixel is defined as below[13]: DR = DRlinear + DRlog = 20log(
Vlin swing Vlog swing ) + 20 Vlin noise Vlog sen
(6)
where Vlin swing , Vlin noise is the output swing and the output noise of the linear response respectively. And Vlog swing is the output swing of the logarithmic response, Vlog sen is the sensitivity of the logarithmic response. The two MOSFETs (M1 and M2 ) for logarithmic response is to enlarge the output swing in the logarithmic mode. The output swing of the logarithmic response of two MOSFETs is twice as much as one MOSFET and will improve the dynamic range. But if the number went beyond two, the output swing of the logarithmic response will be limited by other factors such as the source follower and the output buffer and so on. Besides this, the output swing of the logarithmic response is also restricted by the largest changing voltage of keeping M1 and M2 working in the subthreshold region. If the photocurrent was large enough, Vgs will be much greater than the threshold voltage of M1 and M2 . Because of the shortcut between gate and drain, Vgs = Vds . Then, Vds > Vgs − Vth , M1 and M2 will go into the saturation region and the relationship between V1 and Iph will no longer be logarithmic. Another way to improve the dynamic range is to lower the sensitivity of the logarithmic response. Vlog sen is influenced by the coefficient VT /κ. VT is a constant due to a constant working temperature and the influencing factor is κ. In BSIM3v3 model, κ is a function of the effective channel length and the interface state density. The relationship between 1/κ and the effective channel length is exponential. So, the length of M1 and M2 should be small enough. But in order to reduce the influence of the channel length modulation effect, the length of M1 and M2 should be greater than 1 µm. Finally, the W/L of M1 and M2 is optimized to 3 µm/1 µm. 3. Circuit Implementation The proposed pixel was designed using Global Foundry 0.18µm 1P6M standard Mixedsignal CMOS process, and simulated by using the Cadence Spectre. The power supply voltage is 3.3 V. Working temperature is 77 K because the HgCdTe detector needs to work at 77 K. It is also implemented by a test chip. The test chip contains 16×1 pixel array, a shift register module, a bias module and an output buffer as shown in Figure 4. The pixel pitch is 30 µm. The shift register is a module generates the signals to scan the output voltage of each pixel and to control the readout sequence and the readout rate. The function of the bias module is to produce the bias current for the operational amplifier of the pixel and the output buffer. The layout of the test chip is shown in Figure 5. The total chip size is 3 × 3 mm due to the foundry’s requirement of Multi Project Wafer (MPW) . The core cell area is 480×250 µm. For an easier way to connect to the detector, every pixel’s input port is connected to a separated PAD. 3.1. Pixel design The pixel schematic has been shown in Figure 2. In the pixel, the OPA in the BDI is a two-stage op amp. It causes the bigger area usage but can get very high gain performance. 5
Figure 4: Block diagram of the test chip
Figure 5: Layout of the test chip
The simulation results show that the gain is up to 102.6 dB. If the Rdet = 10 M Ω, the injection efficiency is higher than 99% according to the simulation. The capacitance of the integration capacitor Cint is 2 pF to get a large charge capacity. The sample and hold capacitor Csh should be carefully designed. During the sampling time, the electrons transfer from Cint to Csh . The transfer process obeys the law of charge conservation. So, the relationship between the V1 and V2 is: V2 = CintCint V . The smaller capacitance of +Csh 1 Csh , the higher gain of the sample and hold structure. But because of the sample and hold switch, there exists the KTC noise. The KTC noise is Vn2 KT C = kT /Csh . The KTC noise is bigger when Csh is lower. Here in the design, Csh = 200f F is chosen for better output swing performance. This choice leads to Vsh = V1 /1.1 ≈ 0.91V1 . The gain of a source follower is below one due to the body effect. The size of Msf is optimized to W/L = 7 µm/0.35 µm to get maximum gain and linearity. Figure 6 shows the layout of the pixel and particularly zooms in to reveal the significant transistors M1 and M2 .
6
Figure 6: Layout of the pixel
3.2. Output buffer design The output buffer should have high slew rate, low noise, enough output voltage range. To achieve those parameters, a unity-gain buffer consisting of a five-transistors differential amplifier has been designed. The size of the five transistors are large enough to reduce the 1/f noise. The simulation results show that gain is 53.7 dB, phase margin is 82.4 degree and CMRR is 81.2 dB under load capacitance of 25 pF. The schematic and the layout of the output buffer is presented in Figure 7. The layout is symmetrical to lower the mismatch of the differential transistors.
Figure 7: (a)Schematic and (b)Layout of the output buffer
3.3. Simulation results The photocurrent used to simulate is from 0 nA to 1 µA. Figure 8 shows the simulation results of the photocurrent response curves under different Vlog voltage. The pixel is working at the IWR mode. The trend of the logarithmic response is not influenced by the Vlog voltage. The turning point between linear response and logarithmic response can be controlled by Vlog as expected. The chip’s output voltage Vout is compressed, compared to the V1 voltage, because of the gain (< 1) of the sample and hold circuit, the source follower. For the purpose of finding the maximum output swing of the logarithmic response, the simulated photocurrent is extended to 20 µA under circumstances of Vlog = 3.3 V . The result is presented in Figure 9. The working region of M1 and M2 changes from subthreshold to saturation when Iph ≈ 1.2 µA from the report of the operation points in the Cadence Spectre. 7
Figure 8: Simulated response curves of the proposed pixel
After analyzing the simulation data in MATLAB, the result confirms the conclusion. The maximum output swing of the logarithmic response is about 0.4 V.
Figure 9: Further simulation for Vlog = 3.3 V
4. Experimental results The test chip is hybridized to a medium wave infrared (MWIR) detectors and set along with a custom designed printed circuit board (PCB). The PCB is assembled in a laboratory Dewar which can operate with liquid nitrogen (N2 ). A special test board based on the National Instrument PXI system for the test chip has been carefully designed. A custom LabVIEW software on PC has been used to control the PXI system to provide the timed signals (NI PXI 6552) to the test chip and acquire data (NI PXI 5122) from the test chip. The acquired data is processed by MATLAB on a PC. The test principle diagram and the tested PCB with a HgCdTe detector are demonstrated in Figure 10 and Figure 11. 4.1. Current source test A Keithley 2636A Source Meter Unit has been used to produce high precision and programmable current. The test chip can be set to provide the pixel with the current as the 8
Figure 10: Test block diagram
Figure 11: Tested chip in the Dewar
photocurrent. In this configuration, the linear-logarithmic response to the input current can be measured and calculated. The programmable current ranges from 0 to 1 µA and the integration time is 500 µs. Figure 12 shows the results of the output voltage to the programmable current curve. Figure 12 confirms the proposed pixel operates in linear-logarithmic response according to the simulation results and the expectations. In the linear response, the voltage output swing is 0.42 V, 0.61 V and 0.80 V when Vlog is 3.3 V, 3.0 V and 2.7 V. And the curves are very similar under different Vlog voltage. This means that the Vlog voltage can decide the turning point between the linear mode and logarithmic mode without affecting the output of the linear mode. In the logarithmic response, the sensitivity is not influenced by the Vlog voltage. Furthermore, the dynamic range is tunable by the Vlog voltage. In our design, Vlin noise is 0.32 mV and Vlog sen is 86 mV/dec. The output voltage ranges from 0.14 V to 1.24 V (when Iph = 0). The lowest output is limited by the voltage transfer of the analog chain such as sample-hold, buffer. So, the total output swing is 1.1 V. The tested output voltage is lower than the results of the simulation due to the parasitic of the
9
Figure 12: Measured current response curves of the test chip
Figure 13: Further test for Vlog = 3.3 V
layout. To measure the maximum output swing of logarithmic response, the input current is extended to 10 µA and Vlog is set to 3.3 V. The measurement result is presented in Figure 13. When input current is greater than 3 µA, the relationship between Vout and input current is not logarithmic. So, the maximum output swing of logarithmic response is about 0.34 V. The dynamic range of the chip under different Vlog voltage is shown in Table 1. When Vlog = 2.7 V , the output swing in logarithmic mode is limited to 0.30 V due to the lowest output voltage of the chip. Table 1: Dynamic range of the chip
Vlog /V 3.3 3.0 2.7
Vlin swing /V 0.42 0.61 0.80
Vlog swing /V 0.34 0.34 0.30
DRlinear /dB 62 65 68
10
DRlog /dB 79 79 69
DR/dB 141 144 137
4.2. Detector test The chip is set to use the photocurrent generated by the coupled MWIR HgCdTe detector as the input signal. A blackbody is used to produce the IR radiation. The temperature of the blackbody ranges from 280 K to 675 K. The detector’s bias voltage is set to -50 mV. According to the Stefan-Boltzmann law, the blackbody emissive power into the pixel is: P =
σT 4 AD L 2 4( D ) +1
(7)
where σ = 5.673 × 10−12 [W/(cm2 · K 4 ) is Stefan constant, T is the temperature of the blackbody, AD is the size of the pixel. D is the blackbody’s output aperture. L is the distance between the pixel and the blackbody’s output aperture. So the blackbody emissive power is between 5.25 × 10−9 W and 1.77 × 10−7 W . Figure 14 shows the dark current of the used HgCdTe detector and the relationship between the blackbody power and the HgCdTeconverted photocurrent,tested by a Keithley 6430 micro-current source meter. The dark current is 2.259 × 10−13 A and the resistance is 1.422 × 1011 Ω at -50 mV bias. The photocurrent is 6 × 10−10 A to 5 × 10−8 A.
Figure 14: (a) I − V and R − V curve (b) fitted Iph − P curve
Figure 15: Measured response curves of the tested chip with detector
Figure 15 shows the measured results of the detector test. It confirms the proposed pixel operates in linear-logarithmic response with an IR detector. The output noise of the linear 11
mode, Vlin noise , is 0.45 mV, a little bit higher than the current source test due to the noise of the detector. The logarithmic sensitivity is the same as the result in the section 4.1.The output voltage swing of logarithmic response is 0.18 V, 0.16 V and 0.14 V at Vlog=3.3 V, 3.0 V and 2.7 V. This is due to the difference of the voltage of linear-logarithmic-mode transfer. The measured highest dynamic range is 102 dB. In addition, because of the restriction of the used blackbody’s temperature range, the maximum output swing of logarithmic mode cannot be reached in test. If the blackbody’s temperature was high enough to make the output swing of the test chip achieving to the full output swing in the Table 1, the highest dynamic range will be 141 dB.The performance parameters of the tested chip with detector are shown in Table 2. The linear mode responsivity and logarithmic sensitivity of all pixels in the test chip under Vlog = 3.3 V is shown in Figure 16. The fixed patter noise and non-uniformity in logarithmic mode is larger than that inx linear mode. The explanation to this phenomenon is the mismatch of the M1 and M2 between different pixels. The logarithmic response relies on these two MOSFETs. So, for further improvement of the linear-logarithmic ROIC, the technics of non-uniformity correction and FPN reduction should be added into the circuit. Table 2: The performance parameters of the chip with a detector
Technology Power supply Dynamic range(measured) Linear mode responsivity Linear mode Detectivity* Linear mode noise Logarithmic sensitivity Linear mode Non-uniformity of response Log mode Linear mode Fixed Pattern Noise Log mode Power dissipation
0.18µm 1P6M 3.3 V 102 dB 4.01 × 107 V /W 4.51 × 108 cm · Hz 1/2 /W 0.45 mV 86 mV/dec 3.3% 6.2% 2.5 mV 5.7 mV 2.64 mW
Figure 16: The linear mode responsivity and logarithmic sensitivity
12
5. Conclusion A new design of the linear-logarithmic pixel with high dynamic range was proposed in this paper. The pixel operates in the linear mode at low input photocurrent and automatically switch to the logarithmic mode at lager input photocurrent. The simulation results has confirmed the efficacy of the design. By combining the linear response and the logarithmic response in one pixel, the dynamic range of the test chip is much higher than 137 dB. Along with a MWIR detectors, the dynamic range achieves 102 dB. It shows that the proposed pixel structure can provide a promising solution to the high dynamic range IRFPA ROIC. 6. Reference [1] K. Barnes, R. P. Davis, P. Knowles, N. Shorrocks, Infrared detectors for earth observation, in: Xiong, XJ and Kuriakose, SA and Kimura, T (Ed.), Earth Observing Missions and Sensors: Development, Implementation, and Characterization IV, Vol. 9881 of Proceedings of SPIE, SPIE; Indian Space Res Org; Minist Earth Sci; Natl Aeronaut & Space Adm, SPIE-INT SOC Optical Engineering, 1000 20th ST, Po Box 10, Bellingham, WA 98227-0010 USA, 2016, Conference on Earth Observing Missions and Sensors - Development, Implementation, and Characterization IV, Indian Soc Remote Sensing, New Delhi, INDIA, APR 04-07, 2016. doi:10.1117/12.2229580. [2] J. K. Davies, G. S. Wright, A. C. H. Glasse, Solar system observations with MIRI, the mid infrared instrument on the James Webb Space Telescope, Earth Moon and Planets 105 (2-4) (2009) 73–80, Workshop on Future Ground-based Solar System Research Synergies with Space Probes and Space Telescope, Portoferraio, Italy, SEP 08-12, 2008. doi:10.1007/s11038-009-9313-z. [3] A. Goldberg, T. Fischer, Z. Derzko, Application of dual-band infrared focal plane arrays to tactical and strategic military problems, in: Andresen, BF and Fulop, GF and Strojnik, M (Ed.), Infrared Technology and Applications XXV111, PTS 1 AND 2, Vol. 4820 of Proceedings of the Society of Photo-Optical Intrumentation Engineers (SPIE), SPIE, SPIE-INT SOC Optical Engineering, 1000 20th ST, Po Box 10, Bellingham, WA 98227-0010 USA, 2003, pp. 500–514, Conference on Infrared Technology and Applications XXVIII, SEATTLE, WA, JUL 07-11, 2002. doi:10.1117/12.451014. [4] A. Rogalski, J. Antoszewski, L. Faraone, Third-generation infrared photodetector arrays, Journal of Applied Physics 105 (9). doi:10.1063/1.3099572. [5] Y. S. Kim, D. H. Woo, Y. M. Jo, S. G. Kang, H. C. Lee, Low-noise and wide-dynamicrange ROIC with a self-selected capacitor for SWIR focal plane arrays, IEEE Sensors Journal 17 (1) (2017) 179–184. doi:10.1109/JSEN.2016.2625322. [6] M. T. E. D. B. S. B. L. M. P. C. J.-P. Z. P. M. M. Z. J.-C. P. Fabrice Guellec, Arnaud Peizerat, A 25m pitch lwir focal plane array with pixel-level 15-bit adc providing high well capacity and targeting 2mk netd (2010). doi:10.1117/12.849684. URL https://doi.org/10.1117/12.849684 [7] H. Kayahan, M. Yazici, O. Ceylan, Y. Gurbuz, A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise, Infrared Physics & Technology 63 (2014) 125–132. doi:10.1016/j.infrared.2013.12.013. 13
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Highlights:
A novel linear-logarithmic pixel for IRFPA have been proposed.
Logarithmic response is based on two additional diode-connected MOSFETs.
Pixel can auto switch between linear and logarithmic response.
Dynamic range is higher than 102 dB and logarithmic response is 86 mV/dec.
Conflict of Interest We declare that we have no financial and personal relationships with other people or organizations that can inappropriately influence our work, there is no professional or other personal interest of any nature or kind in any product, service and/or company that could be construed as influencing the position presented in, or the review of, the manuscript entitled, “A Novel Linear-Logarithmic Readout Integrated Circuit with High Dynamic Range”