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A novel low temperature integration of hybrid CMOS devices on flexible substrates
Organic Electronics 10 (2009) 1217–1222
Contents lists available at ScienceDirect
Organic Electronics journal homepage: www.elsevier.com/locate/orgel
A novel low temperature integration of hybrid CMOS devices on flexible substrates S. Gowrisanker a, M.A. Quevedo-Lopez a,*, H.N. Alshareef a, B.E. Gnade a, S. Venugopal b, R. Krishna b, K. Kaftanoglu b, D.R. Allee b a b
Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States
a r t i c l e
i n f o
Article history: Received 29 April 2009 Received in revised form 19 June 2009 Accepted 20 June 2009 Available online 26 June 2009
PACS: 72.80.Le 73.61.Jc 81.05.Gc 85.30.Tv 85.40. e 84.30. r
a b s t r a c t In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and 1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress. Published by Elsevier B.V.
Keywords: Flexible electronics Hybrid CMOS NAND gate NOR gate
1. Introduction Silicon complementary metal–oxide–semiconductor (CMOS) technology dominates today’s high-end digital and analog microelectronic applications because of its high speed performance. CMOS technology is also used in applications that demand low power consumption because of low static power dissipation. Some of these applications include battery operated displays, cellular phones and display drivers [1,2]. Due to the potential application in low power/large area electronic systems, the development of flexible CMOS is of * Corresponding author. Tel.: +1 972 883 5714. E-mail address: [email protected] (M.A. Quevedo-Lopez). 1566-1199/$ - see front matter Published by Elsevier B.V. doi:10.1016/j.orgel.2009.06.012
great interest [3–7]. For instance, CMOS will enable a potential 50 reduction in power consumption for integrated source drivers for an electrophoretic display compared to n-channel (or p-channel) only thin-film transistor (TFT) circuits. Additional potential applications for large area flexible CMOS are thin, light-weight flexible displays and drivers, low-cost RFID tags, a wide variety of sensors, as well as large area solar panels with built in power control. Recent TFT CMOS demonstrations include simple circuits incorporating ZnO or InGaZnO as the n-channel component and pentacene as the p-channel element [8–10]. However, these demonstrations have been shown for relatively simple devices on rigid substrates. A common semiconductor material used in fabricating active matrix backplane displays is hydrogenated
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amorphous Si (a-Si:H) TFTs [11–15]. Low temperature a-Si:H thin-film transistors are generally n-channel [11,12,16] while organic semiconductors such as pentacene are generally p-channel [9,17,18]. Recently, pentacene-based thin-film transistors have had significant improvement, and are now comparable to a-Si:H TFTs [7,9,19]. Also, organic semiconductors showing n-type behavior with mobilities in the order of those of a-Si:H have been achieved; although this has been achieved in relatively simple devices [20,21]. In this work we demonstrate a novel CMOS integration approach that incorporates inorganic a-Si:H as the n-channel element and pentacene as the p-channel element using photolithography-based processing. Furthermore, the devices are fabricated on flexible substrates (PEN) and the maximum processing temperature is kept below the glass transition temperature of the substrate (<180 °C). Although CMOS devices have recently been demonstrated [5,7,9,20,22–24], our integration approach demonstrates an all-photolithography-based integration to fabricate several logic components integrated in the same substrate and compatible with current backplane manufacturing technology. 2. Results and discussion The integration of a-Si:H and pentacene has been demonstrated in rigid substrates and by interconnecting the discrete devices [5,7]. As opposite to those initial reports, the CMOS integration scheme presented in this work involves fabricating the CMOS devices in a flexible substrate and using standard interconnection technology. The process starts by fabricating the a-Si:H nMOS devices first, followed by the pentacene pMOS devices. The resulting CMOS circuits are then encapsulated using parylene as passivation and vias are opened for further testing. A schematic cross-section and optical photograph of the CMOS devices on PEN are shown in Fig. 1a and b, respectively. The detailed process is as follows. After planarization of the flexible substrate (PEN) the nMOS TFTs (a-Si:H) are fabricated using an inverted staggered architecture with
the gate underneath and the semiconductor and source/ drain on top (Fig. 1a). The components of the a-Si:H TFTs are: molybdenum as gate metal, Si3N4 gate dielectric, and aluminum as the source-drain metallization. Data lines and contacts are formed by deposition and patterning the n+ doped a-Si:H via PECVD and Al metal by DC sputtering. The maximum process temperature for nMOS fabrication was 180 °C. This process is completed at the Flexible Display Center at Arizona State University. Typical current voltage characteristics for the resulting n-channel a-Si:H TFTs are shown in Fig. 2. From Fig. 2a we extracted a saturation mobility of 0.75 cm2/V s with an Ion/Ioff current ratio >108. Subthreshold slope is approximately 0.35 V/decade and threshold voltage of 1.14 V. Fig. 2b shows a typical IDS–VDS family of curves for the nchannel a-Si:H process described above. Well behaved transistors characteristics are observed. After nMOs fabrication, pentacene-based pMOS TFTs are fabricated at UT-Dallas. pMOS TFTs are fabricated using a bottom gate approach. In our process, the gate insulator (parylene) is deposited after the inter-level dielectric (ILD) [12,25,26]. This fabrication process includes aluminum as gate metal, parylene as ILD (500 nm), parylene (100 nm) as gate dielectric and gold as source-drain contacts and interconnect metallization. The pMOS fabrication process starts with the ILD (0.5 lm of parylene) deposition over Al gate metal formed during nMOS fabrication. The ILD is deposited at room temperature and patterned to define the metal gate vias and channel region (Fig. 1a). Next, gold (100 nm) is deposited by e-beam evaporation and patterned to form source-drain contacts and interconnects. Pentacene (150 nm) is then deposited at room temperature to create the active channel [27]. Finally, the devices are capped using a parylene encapsulation process and vias are opened for device testing. As we reported, this approach provides a pristine and hydrophobic surface, which provides a favorable surface for pentacene growth [25,26]. If the gate dielectric layer is patterned before patterning the ILD layer the gate dielectric surface becomes hydrophilic due to exposure to the RIE oxygen resulting in degraded pentacene performance [25].
Fig. 1. (a) Cross-section of the integrated flexible CMOS. (b) Photograph of flexible CMOS fabricated on PEN.
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Fig. 2. (a) IDS–VGS for a-Si:H nMOS TFTs. (b) IDS–VDS for a-Si:H nMOS TFTs.
Fig. 3. (a) IDS–VGS for pentacene pMOS TFTs. (b) IDS–VDS for pentacene pMOS TFTs. Excellent transistor behavior is observed.
Fig. 3b shows typical IDS–VDS for the pMOs transistors obtained using the process described above. From these results we extracted a hole mobility of (0.05 cm2/V s) and threshold voltage of 1.4 V. Fig. 3b shows the IDS–VDS curve-family, where drain-source voltage (VDS) is swept from 0 V to 25 V for different gate voltages (VGS). Excellent transistor characteristics are observed. The resulting circuits fabricated with the integration approach described above are discussed next. Fig. 4a shows an optical image of a CMOS inverter, fabricated with the process described above. A typical voltage transfer curve for inverters is shown in Fig. 4b. The CMOS inverter has W/L for pMOS and nMOS of 500/5 and 100/ 11 lm, respectively. The inverter transition point is at VDD/2, as expected from our circuit simulations, and shows a maximum DC gain of 16. Figs. 5a and b show optical images and input–output characteristics for 2-input NAND and NOR gates, respectively. In both cases, for input A, a square wave with a 20 ms period and 50% duty cycle is used; for input B, a square wave with a 40 ms period and 50% duty cycle is used. As expected for a NAND gate, the output stays high except when both A and B are logic high.
On the other hand, for NOR gates the output stays low except when both A and B are logic low, as expected. These results demonstrate that with our integration approach we can achieve working CMOS devices on flexible substrates. It is well known that many types of TFTs are electrically unstable, and their performance degrades with electrical usage and/or ambient conditions [28]. We have performed initial electrical stress testing of the integrated devices and the results are shown in Fig. 6. Fig. 6a (top) shows an optical image of a pMOS device from an inverter before stress; no noticeable defects observed. However, after stress, defects in the dielectric appear and are likely due to weak spots present in the parylene dielectric. Recently, we reported detailed time dependent dielectric breakdown (TDDB) studies of parylene [29]. We demonstrated that TDDB has a power law distribution and that the parylene breakdown is mainly driven by defects in the dielectric. This is likely the cause of the parylene gate dielectric breakdown observed in the pMOS devices used to fabricate our CMOS circuits (Fig. 6b). Nevertheless, the devices functioned for approximately 8 h before failure (50% duty cycle).
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Fig. 4. (a) Optical image of the resulting CMOS inverter. (b) Voltage transfer curve and gain of the hybrid CMOS inverter.
Fig. 5. (a) Optical image of the resulting NAND (top) and logic verification (bottom). (b) Optical image of the resulting NOR (top) and logic verification (bottom).
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Fig. 6. (a) Optical image showing as fabricated (top) and stressed devices (bottom). (b) Area and voltage dependence for parylene TDDB. For a given stress voltage the larger the area the lower the time to breakdown. This indicates the presence of defects in the parylene dielectric.
3. Conclusions We have demonstrated a novel integration approach for pentacene pMOS and a-Si:H nMOS. These TFTs were integrated on a flexible PEN substrate to fabricate CMOS circuits including inverters, NAND and NOR gates. The maximum processing temperatures are 180 °C for nMOS and 120 °C for the pMOS. Inverters with a gain of 16 were demonstrated and 2-input NAND and NOR gates with excellent logic behavior were demonstrated. Initial reliability of these devices indicates that the parylene gate dielectric in the pMOS limits device lifetime due to electrical stress. We are currently evaluating alternate gate dielectrics to improve CMOS device reliability. References [1] T. Aoyama, K. Ogawa, Y. Mochizuki, N. Konishi, Inverse staggered poly-Si and amorphous Si double structure TFT’s for LCD panels with peripheral driver circuits integration, IEEE Transactions on Electron Devices 43 (1996) 701–705. [2] M. Yamano, H. Takesada, M. Yamasaki, Y. Okita, H. Hada, The 5-inch size full color liquid-crystal television addressed by amorphoussilicon thin-film transistors, IEEE Transactions on Consumer Electronics 31 (1985) 39–46. [3] M.C. LeMieux, Z.N. Bao, Flexible electronics stretching our imagination, Nature Nanotechnology 3 (2008) 585–586. [4] M. Hamedi, R. Forchheimer, O. Inganas, Towards woven logic from organic electronic fibres, Nature Materials 6 (2007) 357–362. [5] A. Dodabalapur, J. Baumbach, K. Baldwin, H.E. Katz, Hybrid organic/ inorganic complementary circuits, Applied Physics Letters 68 (1996) 2246–2248. [6] L. Han, P. Mandlik, K.H. Cherenack, S. Wagner, Amorphous silicon thin-film transistors with field-effect mobilities of 2 cm2/V s for electrons and 0.1 cm2/V s for holes, Applied Physics Letters 94 (2009) 162105. [7] M. Bonse, D.B. Thomasson, H. Klauk, D.J. Gundlach, T.N. Jackson, Integrated a-Si:H/pentacene inorganic/organic complementary circuits, Presented at International Electron Device Meeting, 1998. [8] H. Iechi, Y. Watanabe, H. Yamauchi, K. Kudo, Characterization of zinc oxide and pentacene thin film transistors for CMOS inverters, IEICE Transactions on Electronics E91C (2008) 1843–1847. [9] J.H. Na, M. Kitamura, Y. Arakawa, Complementary two-input NAND gates with low-voltage-operating organic transistors on plastic substrates, Applied Physics Express (2008) 1021803.
[10] M.S. Oh, D.K. Hwang, K. Lee, W.J. Choi, J.H. Kim, S. Im, S. Lee, Pentacene and ZnO hybrid channels for complementary thin-film transistor inverters operating at 2 V, Journal of Applied Physics 102 (2007) 076104. [11] S.M. Venugopal, D.R. Allee, Integrated a-Si:H source drivers for 4 QVGA electrophoretic display on flexible stainless steel substrate, Journal of Display Technology 3 (2007) 57–63. [12] G.B. Raupp, S.M. O’Rourke, C. Moyer, B.P. O’Brien, S.K. Ageno, D.E. Loy, E.J. Bawolek, D.R. Allee, S.M. Venugopal, J. Kaminski, D. Bottesch, J. Dailey, K. Long, M. Marrs, N.R. Munizza, H. Haverinen, N. Colaneri, Low-temperature amorphous-silicon backplane technology development for flexible displays in a manufacturing pilot-line environment, Journal of the Society for Information Display 15 (2007) 445–454. [13] S.M. Venugopal, D.B. Allee, Z. Li, L.T. Clark, Threshold-voltage recovery of a-S:H digital circuits, Journal of the Society for Information Display 14 (2006) 1053–1057. [14] A. Nathan, B.R. Chalamala, Flexible electronics technology, part II: materials and devices, Proceedings of the IEEE 93 (2005) 1391–1393. [15] A. Nathan, B.R. Chalamala, Special issue on flexible electronics technology, part 1: systems and applications, Proceedings of the IEEE 93 (2005) 1235–1238. [16] A. Sazonov, D. Striakhilev, C.H. Lee, A. Nathan, Low-temperature materials and thin film transistors for flexible electronics, Proceedings of the IEEE 93 (2005) 1420–1428. [17] G. Horowitz, R. Hajlaoui, R. Bourguiga, M. Hajlaoui, Theory of the organic field-effect transistor, Synthetic Metals 101 (1999) 401– 404. [18] G. Horowitz, Organic field-effect transistors, Advanced Materials 10 (1998) 365–377. [19] Y.Y. Lin, D.J. Gundlach, S.F. Nelson, T.N. Jackson, Pentacene-based organic thin-film transistors, IEEE Transactions on Electron Devices 44 (1997) 1325–1331. [20] H. Yan, Y. Zheng, R. Blache, C. Newman, S. Lu, J. Woerle, A. Facchetti, Solution processed top-gate n-channel transistors and complementary circuits on plastics operating in ambient conditions, Advanced Materials 20 (2008) 3393–3398. [21] R. Schmidt, J.H. Oh, Y.S. Sun, M. Deppisch, A.M. Krause, K. Radacki, H. Braunschweig, M. Konemann, P. Erk, Z. Bao, F. Wurthner, High-performance air-stable n-channel organic thin film transistors based on halogenated perylene bisimide semiconductors, Journal of the American Chemical Society 131 (2009) 6215–6228. [22] J.H. Na, M. Kitamura, Y. Arakawa, Low-voltage-operating organic complementary circuits based on pentacene and C60 transistors, Thin Solid Films 517 (2009) 2079–2082. [23] M.S. Oh, W. Choi, K. Lee, D.K. Hwang, S. Ima, Flexible high gain complementary inverter using n-ZnO and p-pentacene channels on polyethersulfone substrate, Applied Physics Letters 93 (2008) 033510.
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[24] X.H. Zhang, W. Potscavage, S. Choi, B. Kippelena, Low-voltage flexible organic complementary inverters with high noise margin and high dc gain, Applied Physics Letters 94 (2009) 043312. [25] S. Gowrisanker, Y. Ai, H. Jia, M.A. Quevedo-Lopez, H.N. Alshareef, I. Trachtenberg, H. Stiegler, H. Edwards, R. Barnett, B.E. Gnade, Organic thin-film transistors with low threshold voltage variation on lowtemperature substrates, Electrochemical and Solid State Letters 12 (2009) H50–H53. [26] S. Gowrisanker, A. Yuming, M.A. Quevedo-Lopez, H. Jia, E. Vogel, B. E. Gnade, A gate dielectric last approach to integrate organic based devices on plastic substrates, in: Proceedings of the Flexible Electronics and Displays Conference and Exhibition, 2008, pp. 1–3.
[27] S. Gowrisanker, Y. Ai, M.A. Quevedo-Lopez, H. Jia, H.N. Alshareef, E. Vogel, B. Gnade, Impact of semiconductor/contact metal thickness ratio on organic thin-film transistor performance, Applied Physics Letters 92 (2008) 153305. [28] R. Shringarpure, S. Venugopal, Z. Li, L.T. Clark, D.R. Allee, E. Bawolek, D. Toy, Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C, IEEE Transactions on Electron Devices 54 (2007) 1781–1783. [29] S. Gowrisanker, M.A. Quevedo-Lopez, H.N. Alshareef, B. Gnade, TDDB of parylene gate dielectrics, Organic Electronics 10 (5) (2009) 1024– 1027.
Contents lists available at ScienceDirect
Organic Electronics journal homepage: www.elsevier.com/locate/orgel
A novel low temperature integration of hybrid CMOS devices on flexible substrates S. Gowrisanker a, M.A. Quevedo-Lopez a,*, H.N. Alshareef a, B.E. Gnade a, S. Venugopal b, R. Krishna b, K. Kaftanoglu b, D.R. Allee b a b
Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States
a r t i c l e
i n f o
Article history: Received 29 April 2009 Received in revised form 19 June 2009 Accepted 20 June 2009 Available online 26 June 2009
PACS: 72.80.Le 73.61.Jc 81.05.Gc 85.30.Tv 85.40. e 84.30. r
a b s t r a c t In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and 1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress. Published by Elsevier B.V.
Keywords: Flexible electronics Hybrid CMOS NAND gate NOR gate
1. Introduction Silicon complementary metal–oxide–semiconductor (CMOS) technology dominates today’s high-end digital and analog microelectronic applications because of its high speed performance. CMOS technology is also used in applications that demand low power consumption because of low static power dissipation. Some of these applications include battery operated displays, cellular phones and display drivers [1,2]. Due to the potential application in low power/large area electronic systems, the development of flexible CMOS is of * Corresponding author. Tel.: +1 972 883 5714. E-mail address: [email protected] (M.A. Quevedo-Lopez). 1566-1199/$ - see front matter Published by Elsevier B.V. doi:10.1016/j.orgel.2009.06.012
great interest [3–7]. For instance, CMOS will enable a potential 50 reduction in power consumption for integrated source drivers for an electrophoretic display compared to n-channel (or p-channel) only thin-film transistor (TFT) circuits. Additional potential applications for large area flexible CMOS are thin, light-weight flexible displays and drivers, low-cost RFID tags, a wide variety of sensors, as well as large area solar panels with built in power control. Recent TFT CMOS demonstrations include simple circuits incorporating ZnO or InGaZnO as the n-channel component and pentacene as the p-channel element [8–10]. However, these demonstrations have been shown for relatively simple devices on rigid substrates. A common semiconductor material used in fabricating active matrix backplane displays is hydrogenated
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amorphous Si (a-Si:H) TFTs [11–15]. Low temperature a-Si:H thin-film transistors are generally n-channel [11,12,16] while organic semiconductors such as pentacene are generally p-channel [9,17,18]. Recently, pentacene-based thin-film transistors have had significant improvement, and are now comparable to a-Si:H TFTs [7,9,19]. Also, organic semiconductors showing n-type behavior with mobilities in the order of those of a-Si:H have been achieved; although this has been achieved in relatively simple devices [20,21]. In this work we demonstrate a novel CMOS integration approach that incorporates inorganic a-Si:H as the n-channel element and pentacene as the p-channel element using photolithography-based processing. Furthermore, the devices are fabricated on flexible substrates (PEN) and the maximum processing temperature is kept below the glass transition temperature of the substrate (<180 °C). Although CMOS devices have recently been demonstrated [5,7,9,20,22–24], our integration approach demonstrates an all-photolithography-based integration to fabricate several logic components integrated in the same substrate and compatible with current backplane manufacturing technology. 2. Results and discussion The integration of a-Si:H and pentacene has been demonstrated in rigid substrates and by interconnecting the discrete devices [5,7]. As opposite to those initial reports, the CMOS integration scheme presented in this work involves fabricating the CMOS devices in a flexible substrate and using standard interconnection technology. The process starts by fabricating the a-Si:H nMOS devices first, followed by the pentacene pMOS devices. The resulting CMOS circuits are then encapsulated using parylene as passivation and vias are opened for further testing. A schematic cross-section and optical photograph of the CMOS devices on PEN are shown in Fig. 1a and b, respectively. The detailed process is as follows. After planarization of the flexible substrate (PEN) the nMOS TFTs (a-Si:H) are fabricated using an inverted staggered architecture with
the gate underneath and the semiconductor and source/ drain on top (Fig. 1a). The components of the a-Si:H TFTs are: molybdenum as gate metal, Si3N4 gate dielectric, and aluminum as the source-drain metallization. Data lines and contacts are formed by deposition and patterning the n+ doped a-Si:H via PECVD and Al metal by DC sputtering. The maximum process temperature for nMOS fabrication was 180 °C. This process is completed at the Flexible Display Center at Arizona State University. Typical current voltage characteristics for the resulting n-channel a-Si:H TFTs are shown in Fig. 2. From Fig. 2a we extracted a saturation mobility of 0.75 cm2/V s with an Ion/Ioff current ratio >108. Subthreshold slope is approximately 0.35 V/decade and threshold voltage of 1.14 V. Fig. 2b shows a typical IDS–VDS family of curves for the nchannel a-Si:H process described above. Well behaved transistors characteristics are observed. After nMOs fabrication, pentacene-based pMOS TFTs are fabricated at UT-Dallas. pMOS TFTs are fabricated using a bottom gate approach. In our process, the gate insulator (parylene) is deposited after the inter-level dielectric (ILD) [12,25,26]. This fabrication process includes aluminum as gate metal, parylene as ILD (500 nm), parylene (100 nm) as gate dielectric and gold as source-drain contacts and interconnect metallization. The pMOS fabrication process starts with the ILD (0.5 lm of parylene) deposition over Al gate metal formed during nMOS fabrication. The ILD is deposited at room temperature and patterned to define the metal gate vias and channel region (Fig. 1a). Next, gold (100 nm) is deposited by e-beam evaporation and patterned to form source-drain contacts and interconnects. Pentacene (150 nm) is then deposited at room temperature to create the active channel [27]. Finally, the devices are capped using a parylene encapsulation process and vias are opened for device testing. As we reported, this approach provides a pristine and hydrophobic surface, which provides a favorable surface for pentacene growth [25,26]. If the gate dielectric layer is patterned before patterning the ILD layer the gate dielectric surface becomes hydrophilic due to exposure to the RIE oxygen resulting in degraded pentacene performance [25].
Fig. 1. (a) Cross-section of the integrated flexible CMOS. (b) Photograph of flexible CMOS fabricated on PEN.
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Fig. 2. (a) IDS–VGS for a-Si:H nMOS TFTs. (b) IDS–VDS for a-Si:H nMOS TFTs.
Fig. 3. (a) IDS–VGS for pentacene pMOS TFTs. (b) IDS–VDS for pentacene pMOS TFTs. Excellent transistor behavior is observed.
Fig. 3b shows typical IDS–VDS for the pMOs transistors obtained using the process described above. From these results we extracted a hole mobility of (0.05 cm2/V s) and threshold voltage of 1.4 V. Fig. 3b shows the IDS–VDS curve-family, where drain-source voltage (VDS) is swept from 0 V to 25 V for different gate voltages (VGS). Excellent transistor characteristics are observed. The resulting circuits fabricated with the integration approach described above are discussed next. Fig. 4a shows an optical image of a CMOS inverter, fabricated with the process described above. A typical voltage transfer curve for inverters is shown in Fig. 4b. The CMOS inverter has W/L for pMOS and nMOS of 500/5 and 100/ 11 lm, respectively. The inverter transition point is at VDD/2, as expected from our circuit simulations, and shows a maximum DC gain of 16. Figs. 5a and b show optical images and input–output characteristics for 2-input NAND and NOR gates, respectively. In both cases, for input A, a square wave with a 20 ms period and 50% duty cycle is used; for input B, a square wave with a 40 ms period and 50% duty cycle is used. As expected for a NAND gate, the output stays high except when both A and B are logic high.
On the other hand, for NOR gates the output stays low except when both A and B are logic low, as expected. These results demonstrate that with our integration approach we can achieve working CMOS devices on flexible substrates. It is well known that many types of TFTs are electrically unstable, and their performance degrades with electrical usage and/or ambient conditions [28]. We have performed initial electrical stress testing of the integrated devices and the results are shown in Fig. 6. Fig. 6a (top) shows an optical image of a pMOS device from an inverter before stress; no noticeable defects observed. However, after stress, defects in the dielectric appear and are likely due to weak spots present in the parylene dielectric. Recently, we reported detailed time dependent dielectric breakdown (TDDB) studies of parylene [29]. We demonstrated that TDDB has a power law distribution and that the parylene breakdown is mainly driven by defects in the dielectric. This is likely the cause of the parylene gate dielectric breakdown observed in the pMOS devices used to fabricate our CMOS circuits (Fig. 6b). Nevertheless, the devices functioned for approximately 8 h before failure (50% duty cycle).
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Fig. 4. (a) Optical image of the resulting CMOS inverter. (b) Voltage transfer curve and gain of the hybrid CMOS inverter.
Fig. 5. (a) Optical image of the resulting NAND (top) and logic verification (bottom). (b) Optical image of the resulting NOR (top) and logic verification (bottom).
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Fig. 6. (a) Optical image showing as fabricated (top) and stressed devices (bottom). (b) Area and voltage dependence for parylene TDDB. For a given stress voltage the larger the area the lower the time to breakdown. This indicates the presence of defects in the parylene dielectric.
3. Conclusions We have demonstrated a novel integration approach for pentacene pMOS and a-Si:H nMOS. These TFTs were integrated on a flexible PEN substrate to fabricate CMOS circuits including inverters, NAND and NOR gates. The maximum processing temperatures are 180 °C for nMOS and 120 °C for the pMOS. Inverters with a gain of 16 were demonstrated and 2-input NAND and NOR gates with excellent logic behavior were demonstrated. Initial reliability of these devices indicates that the parylene gate dielectric in the pMOS limits device lifetime due to electrical stress. We are currently evaluating alternate gate dielectrics to improve CMOS device reliability. References [1] T. Aoyama, K. Ogawa, Y. Mochizuki, N. Konishi, Inverse staggered poly-Si and amorphous Si double structure TFT’s for LCD panels with peripheral driver circuits integration, IEEE Transactions on Electron Devices 43 (1996) 701–705. [2] M. Yamano, H. Takesada, M. Yamasaki, Y. Okita, H. Hada, The 5-inch size full color liquid-crystal television addressed by amorphoussilicon thin-film transistors, IEEE Transactions on Consumer Electronics 31 (1985) 39–46. [3] M.C. LeMieux, Z.N. Bao, Flexible electronics stretching our imagination, Nature Nanotechnology 3 (2008) 585–586. [4] M. Hamedi, R. Forchheimer, O. Inganas, Towards woven logic from organic electronic fibres, Nature Materials 6 (2007) 357–362. [5] A. Dodabalapur, J. Baumbach, K. Baldwin, H.E. Katz, Hybrid organic/ inorganic complementary circuits, Applied Physics Letters 68 (1996) 2246–2248. [6] L. Han, P. Mandlik, K.H. Cherenack, S. Wagner, Amorphous silicon thin-film transistors with field-effect mobilities of 2 cm2/V s for electrons and 0.1 cm2/V s for holes, Applied Physics Letters 94 (2009) 162105. [7] M. Bonse, D.B. Thomasson, H. Klauk, D.J. Gundlach, T.N. Jackson, Integrated a-Si:H/pentacene inorganic/organic complementary circuits, Presented at International Electron Device Meeting, 1998. [8] H. Iechi, Y. Watanabe, H. Yamauchi, K. Kudo, Characterization of zinc oxide and pentacene thin film transistors for CMOS inverters, IEICE Transactions on Electronics E91C (2008) 1843–1847. [9] J.H. Na, M. Kitamura, Y. Arakawa, Complementary two-input NAND gates with low-voltage-operating organic transistors on plastic substrates, Applied Physics Express (2008) 1021803.
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