A novel SLS ELA crystallization process and its effects on polysilicon film defectivity and TFT performance

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Microelectronic Engineering 85 (2008) 1447–1452 www.elsevier.com/locate/mee

A novel SLS ELA crystallization process and its effects on polysilicon film defectivity and TFT performance Despina C. Moschou a,*, M.A. Exarchos b, D.N. Kouvatsos a, G.J. Papaioannou b, A.T. Voutsas c a b

Institute of Microelectronics, NCSR ‘‘Demokritos’’, Aghia Paraskevi, Athens 15310, Greece Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece c LCD Process Technology Laboratory, Sharp Labs of America, Camas, WA 98607, USA

Received 1 October 2007; received in revised form 21 January 2008; accepted 23 January 2008 Available online 5 February 2008

Abstract Polysilicon TFTs fabricated in films crystallized with a novel SLS ELA technique were investigated. The TFT channels were oriented along the preferential direction and vertical to it, probing both directions’ grain quality. DLTS assessment was conducted on unstressed TFTs in order to probe the film’s defect nature. DC hot-carrier stress was applied for both channel orientations, in order to elucidate the effect of the crystallization procedure on TFT reliability. A dimensional optimization of the TFTs was found. Ó 2008 Elsevier B.V. All rights reserved. Keywords: Polysilicon TFTs; SLS ELA crystallization; DLTS analysis; TFT reliability

1. Introduction Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronic circuits, due to their high field-effect mobility [1]. With recent polysilicon crystallization process innovations, like excimer laser anneal (ELA), TFT performance has improved [2–4]. Variations of the sequential lateral solidification (SLS) ELA process yield films with excellent intragrain quality and grains of different geometries. We also know that grain boundaries and their orientation, respectively to the TFT channel, affect device performance and reliability [6]. Therefore the crystallization process will strongly affect the operation of a TFT. In this work we investigate SLS ELA crystallized TFTs fabricated with an advanced method, termed M  N. The relationship between process characteristics and defectivity *

Corresponding author. Tel.: +30 2106503266; fax: +30 2106511723. E-mail address: [email protected] (D.C. Moschou).

0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.01.083

and reliability is probed through DLTS analysis and hotcarrier stress. 2. Experimental TFTs were fabricated in 50 nm thick SLS ELA crystallized polysilicon films, using a technique termed M  N. The procedure is conducted at room temperature, using a LPX 315i Lambda Physick excimer laser (XeCl, 308 nm, discharge frequency of 150 Hz) system, with the laser beam shaped by a mask consisting of sets of slits orthogonal to each other (Fig. 1). Grains grow first in the Y direction (via the ‘‘M” patterns) and, then, sub-boundaries are swept in the X direction (via the ‘‘N” patterns), which is the preferential direction. This process yields large rectangular grains, but of lower intragrain quality than other multishot techniques (Fig. 1). No hard grain boundaries should be included in the TFT channel in either direction. However, sub-boundaries and film protrusions are present in both directions, known to affect TFT performance [5].

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Fig. 1. Laser mask movement during the M  N crystallization procedure (left) and SEM image of the polysilicon film (right).

TFTs had a top-metal-gate structure and a PECVD SiO2 gate dielectric. DLTS analysis was conducted on unstressed TFTs with channel dimensions W/L = 8 lm/ 2 lm, immediately after the transition from OFF- to ONstate. This transition results in sufficient band bending from accumulation (OFF) to strong inversion (ON). Drain current spectra DId(T) were monitored with a modified DLTS system, consisting of an SR570 current amplifier which also provided the drain bias (VDS = 50 mV), and a PC data acquisition card (DAQ). The duration tOFF of the OFF-state was kept constant at 100 ms. Rate window values e ranged from 800 s 1 to 6.25 s 1. The temperature range was 110 K–400 K. Devices were stressed and characterized using a HP4140B semiconductor analyzer. TFTs were characterized in both directions, their channel lengths ranging from L = 0.5 lm to L = 2 lm for widths W = 2 lm and W = 8 lm. Hot-carrier stress was applied to devices with W/L = 2/2, for a maximum of 16 h. The Ids Vgs curves were taken after each stress cycle and the device parameters extracted from them were: extrapolated threshold voltage Vth, maximum transconductance Gm,max and subthreshold slope S. 3. Results and discussion Fig. 2 shows typical DLTS spectra of TFTs, the channel being oriented in both directions. Although measurements

were conducted under the same bias conditions, the DId(T) magnitude differs. For the X-oriented devices, the drain current is higher because the energy barrier height of the grain boundaries EB(X), is lower than that of Y direction EB(Y). Thus, the electron concentration within the channel of the X-oriented TFTs is larger than that of Y-oriented ones, since carriers have to overcome a lower energy barrier. In Fig. 3, Arrhenius plots of Id at steady state are depicted. The slope of the linear portion represents the energy barrier height EB [7]. For both orientations, the DLTS spectra structure is rather complex. Further decomposed, the X orientation spectrum manifested three thermally activated contributions corresponding to discrete traps lying deep in the polysilicon energy gap; TLT, TMT and THT traps are observed in low, medium and high temperatures, respectively (Fig. 4). Each of these traps is associated with an Arrhenius plot that yields its corresponding activation energy (Fig. 5). A comparison between the detected traps and those reported in the literature revealed that the most probable candidates for TLT, TMT and THT are hole trapping/detrapping mechanisms originating from dislocations and rapid thermal annealing defects. The former are labeled as DE2, DE3, DH3, DislC2, DH(56%) (dot lines in Fig. 6) and the latter as Qb542, H1(D), H1(B87) (dash lines in Fig. 5). As far as reliability is concerned, while for Vdstress = 8 V the degradation of X oriented TFTs is substantial, we hardly see any deterioration of the Y oriented ones. Applying Vdstress = 10 V to a Y direction TFT we see some worsening of the device performance, less pronounced than that of the X one (Figs. 6–8). The fact that stressing effects are more intense in the X orientation could be attributed to the ‘‘softer” sub-boundaries, possibly decreasing the carrier mobility. By the calculation of S, parameter proportional to the interface states, as a function of stress time (Fig. 6), we can see that indeed the X oriented TFT shows the most severe degradation. However, observing in Fig. 7 the evo-

Fig. 2. DTLS spectra (e = 100 s 1) for X- and Y-oriented TFTs.

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Fig. 3. Energy barrier height for X- and Y-oriented TFTs.

Fig. 4. DLTS spectra decomposition (e = 100 s 1) to three components, for X-oriented TFTs.

Fig. 5. Arrhenius plots associated to DLTS spectra of Fig. 3. (h) X-oriented TFTs, (h) Y-oriented TFTs.

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X direction Vgstress =4V Vdstress =8V Y direction Vgstress =4V Vdstress =8V Y direction Vgstress =5V Vdstress =10V

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0.24 X direction W=2 X direction W=8 Y direction W=2 Y direction W=8

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Fig. 9. Subthreshold slope S as a function of channel length L.

lution of Vth with stress time we see a similar behavior for both orientations. So, Vth shift for the Y direction TFT can be mainly attributed to hot electrons injected in the gate oxide, since interface degradation is not probed through S, while for the X direction TFT to interface degradation. Considering the nature of the polysilicon channel, this is something expected, since for the Y orientation the harder sub-boundaries, obstructing the current flow, locally intensify the vertical field [6], and so induce the hot electrons to be injected in the gate dielectric. For the X direction, the degradation is mainly caused by the scattering of electrons on the interface. As for the field-effect mobility l degradation, in Fig. 8 we can see its evolution with stress time. Both orientations show a decrease of their mobility of about 20%. The difference is that for the Y direction this decrease is monotonous, while for the X one we see an initial increase, followed by a decrease after 1 h stress. This behavior has been attributed to ‘‘channel shortening” effects [8], caused by localized electron injection near the drain. As degradation proceeds, the damage extends further in the channel region and so the channel shortening effect is suppressed. Such an effect is not observed in the Y direction, which is possibly explained if we consider again the harder grain boundaries within the channel region, causing increased electron injection near them, thus making the damaged areas less strictly localized. Characterizing TFTs of different dimensions, we attempted to find the optimum gate length for M  N TFTs. As can be seen in Fig. 9, for larger or smaller channel lengths than 1.2 lm the TFT performance seems to deteriorate. The increasing S with increasing L is something expected, since, observing the SEM image (Fig. 1), we see that more sub-boundaries are included within the channel region for longer channel lengths. The increase of S with decreasing channel length is an electrical effect, ascribed to the increased channel charge in the subthreshold regime [9] due to the additional drain bias control of

the channel region. So the deterioration of the TFT performance for small channel lengths is an electrical effect while the deterioration for large channel lengths is process related. These two effects define the optimum L. 4. Conclusions SLS ELA polysilicon TFTs fabricated in films crystallized with a novel technique termed M  N, yielding large rectangular crystal domains, were characterized and stressed with the TFT channels oriented along both directions. The DLTS analysis of the devices showed larger energy barrier height in the Y direction, a result verified by the superior field-effect mobility of the X oriented TFTs. Discrete traps deep in the polysilicon energy gap were detected, originating from dislocations and rapid thermal annealing defects. As for reliability, the degradation seemed to be less pronounced in the Y direction, due to the harder sub-boundaries obstructing the stress current. The main degradation mechanism for the X direction was interface state generation, while for the Y direction the gate oxide charge injection. We also observed a channel shortening effect only in the X direction. Finally, an optimum channel length was found, defined both by the process related sub-boundary characteristics and by electrical effects. Acknowledgments The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek General Secretariat for Research and Technology. References [1] T. Matsuo, T. Muramatsu, Proc. SID Intern. Sympos. (2004) 856. [2] R.S. Sposili, J.S. Im, Appl. Phys. Lett. 69 (1996) 2864. [3] A.T. Voutsas, IEEE Trans. Electron Dev. ED. 50 (2003) 1494.

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[4] M.A. Crowder, M. Moriguchi, Y. Mitani, A.T. Voutsas, Thin Solid Films. 427 (2003) 101. [5] A.T. Voutsas, A. Limanov, J.S. Im, J. Appl. Phys. 94 (2003) 7445. [6] P.T. Liu, H.Y. Lu, Yu C. Chen, S. Chi, IEEE Electr. Dev. Lett. EDL. 28 (2007) 401.

[7] Y. Morimoto et al., J. Electrochem. Soc. 144 (7) (1997) 2495–2501. [8] F.V. Farmakis et al., Int. Semiconductor Conf. CAS ‘99 Proc. 1 (1999) 157–160. [9] A.G. Lewis et al., IEDM ‘89 Proc. (1999) 349–352.