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Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique
Microelectronics Reliability 48 (2008) 1544–1548
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique D.C. Moschou a,*, M.A. Exarchos b, D.N. Kouvatsos a, G.J. Papaioannou b, A. Arapoyanni c, A.T. Voutsas d a
Institute of Microelectronics, NCSR Demokritos, Patriarchou Grigoriou and Neapoleos Strs, Aghia Paraskevi 15310, Greece Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece c Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Athens 15784, Greece d Material and Device Applications Laboratory, Sharp Labs of America, Camas, WA 98607, USA b
a r t i c l e
i n f o
Article history: Received 10 June 2008 Available online 3 August 2008
a b s t r a c t SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented both along the preferential and the non-preferential direction. The degradation mechanisms proved very different between n- and p-channel devices, while the channel orientation had a larger effect on n-channel devices than on p-ones. In order to probe the reasons causing this effect we applied DLTS analysis to both n- and p-channel devices oriented along both directions, receiving valuable information about the defectivity differences in n- and p-polysilicon films. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics, VLSI technology and high performance flat panel display applications [1]. The primary advantage of polysilicon TFTs over a:Si ones is their higher field effect mobility and consequently higher drive current. For the fabrication of novel commercial products to be possible, high reliability CMOS circuitry using LTPS TFTs should be available. With recent polysilicon crystallization process breakthroughs, using various excimer laser anneal (ELA) methods such as sequential lateral solidification (SLS), TFT performance has substantially increased [2–6]. Several variations of the SLS technique allow the manufacturing of polysilicon films with excellent intragrain quality and grains of different geometry. However, n- and p-channel devices fabricated in the same film, both required for CMOS circuitry, show much different degradation characteristics [7,8]. In this work, SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented along the preferential and the non-preferential direction. We probed through DC stress their reliability differences and attempted to relate them to their defectivity characteristics, obtained through drain current transient investigation. 2. Experimental The TFTs studied were fabricated in 50 nm thick polysilicon films, formed by ELA crystallization of a:Si, using the M N SLS * Corresponding author. Tel.: +30 210 6503239; fax: +30 210 6511723. E-mail address: [email protected] (D.C. Moschou). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.06.006
technique, specifically described elsewhere [9]. The procedure is conducted at room temperature, using a LPX 315i Lambda Physik excimer laser (XeCl, 308 nm, discharge frequency of 150 Hz) system, with the laser beam shaped by an appropriate mask. This SLS procedure results in larger rectangular domain sizes than other similar multi-shot techniques. The crystal domain being much larger than the TFT channel, no hard grain boundaries are likely to be included in either direction. Moreover, this technique yields a film with fewer sub-boundaries obstructing the current flow in the X orientation of the film (preferential) than in the Y (non-preferential) [9]. However, sub-boundaries are present in both directions, along with nanoprotrusions, known to affect n-channel TFT reliability [9,10]. Both n-channel and p-channel TFTs had a top-metal-gate structure and a PECVD SiO2 gate dielectric. Devices were stressed and characterized using a HP4140B semiconductor analyzer. DC stress was applied to both n- and p-channel devices with L = 2 lm and W = 2 lm and also in p-channel devices with L = 2 lm and W = 1 lm for further investigation. The maximum stress duration was 16 h under the DC stress condition of Vgstress = Vdstress/2. The Ids–Vgs transfer characteristics were taken after each stress cycle and the device parameters extracted from them were the extrapolated threshold voltage Vth, the field effect mobility l and the subthreshold slope S. In order to investigate differences in film defectivity of n- and pchannel TFTs that could explain their reliability characteristics, deep level transient spectroscopy (DLTS) was implemented to record drain current spectra DId(T) (T: temperature), immediately after the transition from OFF- to ON-state. This transition results in sufficient polysilicon band bending from accumulation (OFFstate) to strong inversion (ON-state) condition. DLTS spectra DId(T)
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were extracted for rate window e values ranging from 6.25 s1 to 800 s1. Switch-ON drain current transients DId(t) (t: time) were also recorded. Transients were sampled in the 0–256 ms time interval (tON) with a 1 ms sampling rate. The OFF-state duration (tOFF) was constant at 100 ms, for both DLTS spectra DId(T) and transient DId(t) recording. All measurements extended in the thermal range of 110–400 K. 3. Results and discussion In order to investigate the reliability differences between nchannel and p-channel devices of the same dimensions (W/ L = 2 lm/2 lm), we applied analogous stress biases for Vgs and Vds, utilizing the stress condition Vgstress = Vdstress/2, as mentioned before. For the n-channel devices the stress biases used were Vgstress = 4 V, Vdstress = 8 V [9]. The analogous stress biases used for p-channel devices, observing that their absolute Vth value was about 1 V higher than the n-channel ones, were Vgstress = 5 V, Vdstress = 10 V. In Fig. 1, we see the evolution of the extrapolated threshold voltage Vth for both n-channel and p-channel devices, oriented both along the preferential X and the non-preferential Y direction. For the n-channel devices we see a large difference between the two orientations. For the p-channel devices, on the other hand, the two channel orientations show similar behavior. The largest Vth degradation is observed for the X oriented n-channel device, that has the largest carrier mobility of all the investigated devices [9]. As for the subthreshold slope S of the devices (Fig. 2), the only device showing an increase is again the X oriented n-channel device. All the other devices show almost no S variation, indicating insignificant interface state generation. The previous observation that for the p-channel devices the channel orientation plays a smaller role is further supported considering their mobility values (Fig. 3). While for the n-channel devices the X direction mobility is approximately double than the Y one, p-channel X direction mobility is only about 10% higher than the Y one. Also, both p-channel devices show similar l degradation, with a slight increase for large stressing times, indicating a minor channel shortening effect. This behavior is much different than that of the n-channel TFTs, for which the Y direction shows no degradation at all, but the X direction shows an initial, much swifter channel shortening effect, followed by a large decrease. In order to further investigate whether the degradation mechanisms are similar for more intense stressing, we applied larger
Fig. 1. Evolution of extrapolated threshold voltage Vth Vth0 with stress time for both n- and p-channel devices under analogous stress conditions.
Fig. 2. Evolution of Subthreshold slope S S0 with stress time for both n- and pchannel devices under analogous stress conditions.
Fig. 3. Evolution of field effect mobility l with stress time for both n- and pchannel devices under analogous stress conditions.
stress biases, again under the same Vgstress/Vdstress ratio as previously (Vgstress = 6 V, Vdstress = 12 V), to p-channel devices of both orientations with similar dimensions (W/L = 1 lm/2 lm). Observing the threshold voltage degradation of both X and Y oriented p-channel devices (Fig. 4), we see again very similar behavior for both devices: a small initial increase followed by a logarithmic decrease. The stress gate bias being larger, Vth degradation is also more intense than before. The initial electron trapping, implied by the increase of Vth, has been simulated by Yamagata et al. [8] and attributed to a high vertical electric field under the gate, near the drain junction, attracting hot electrons. For large stressing times, the trapped negative charges increase the potential barrier. Thus electron injection tends towards saturation, allowing hot hole injection, along the whole channel area, to dominate, causing the subsequent logarithmic decrease of Vth. We also see that the subthreshold slope of the devices is again not affected by the stress (Fig. 5), even though the stressing condition is more intense, implying that interface state generation is not favored at this stressing condition for p-channel devices [11]. The stress intensity, however, seems to affect significantly the field effect mobility degradation, since we see a much larger increase for longer stressing times than before (Fig. 6). Despite this larger degradation, we still do not see any decrease of l. This increase of the field effect mobility has been attributed to channel
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Fig. 4. Evolution of extrapolated threshold voltage Vth Vth0 with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
Fig. 5. Evolution of subthreshold slope S S0 with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
Fig. 7. Switch-ON drain current transient behavior for X oriented p-TFTs. The scatter symbols represent the experimental data. The continuous and dot lines, represent the fit process based on PSEL (Eq. (1)) and DSEL (Eq. (3)) formulas respectively.
vices the spreading of the degraded region along the rest of the channel takes longer times, due to a lower lateral electric field [8]. In order to investigate the very similar degradation behavior between the two channel orientations, observed only for p-channel devices and not for n-channel ones, we tried to probe the differences in n- and p- film defectivities applying the DLTS method to unstressed n- and p-channel TFTs (W/L = 8 lm/2 lm). The switch-ON drain current transients of n- and p-channel TFTs exhibited analogous temperature dependence behavior. A transition from undershoot to overshoot effect was observed as the temperature increased. Further analyzing, we observed that there were three regimes (Fig. 7); the first one extended within the range 110–290 K where undershoot-like transients were monitored. The second one, between 290 and 340 K, where the switchON transient behavior is complex, with undershoot and overshoot effect coexisting. Finally, for temperatures within the range 340– 400 K overshoot-like transient behavior was monitored. Fitting analysis based on the stretched exponential law was examined in order to analyze this complex transient behavior [12]. For the first regime transients relaxed through the plain stretched exponential law (PSEL) described by Eq. (1), where DId(t) is the drain current transient, DId(0) the drain current transient at t = 0 (transient amplitude), s the relaxation time and b the stretch exponential factor (0 6 b 6 1). The factor b stands for the complexity of the process through which the transient relaxes. Relaxation time s represents a thermally activated mechanism with a corresponding activation energy EA, described by Eq. (2). Theoretically, s equals s0 for infinite temperature
DId ðtÞ ¼ DId ð0Þ exp½ðt=sÞb s ¼ s0 expðEA =kTÞ
Fig. 6. Evolution of field effect mobility l with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
shortening effects [7,8], due to the aforementioned hot electron injection near the drain region. The fact that this channel shortening effect is observed at much larger stressing times, compared to n-channel devices, can be explained if we consider that in these de-
ð1Þ ð2Þ
For the second and third regime, transients relaxed through the dual stretched exponential law (DSEL) described by Eq. (3), denoting that the transient relaxation follows complex mechanisms due to highly disordered material 0
DId ðtÞ ¼ DId ð0Þ exp½ðt=sÞb þ DId ð0Þ0 exp½ðt=s0 Þb
ð3Þ
Drain current transient fitting results with Eqs. (1) and (3) disclosed that relaxation time s consists of two components s1 and s2 (Fig. 8). Each component represents a thermally activated mechanism characterized by an activation energy EAS, derived from an Arrhenius plot according to Eq. (2) (Table 1).
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The first thermally activated mechanism (s1, EAS(1)) is ascribed to polarization of gate oxide [13]. This phenomenon is more pronounced in n-channel TFTs whose polysilicon film was crystallized mainly under 2-shot and 26-shot, as well as under M N#8, laser irradiation schemes [10,14]. In that case, the polysilicon film exhibited enhanced protrusion density. For the present devices studied, advanced M N polysilicon film is marked out for low surface roughness and for small domains, smaller than those of the aforementioned technologies. However, asperities whose height is comparable to the polysilicon film thickness are still monitored. Consequently, the subsequent dielectric film growth on the polysilicon film, would meet high asperities, originating from domains small in size but increased in density. As a result, regions within the gate dielectric film are formed, characterized by the presence of strong electric field, causing dielectric polarization. The latter is more intense for devices, having their channel aligned in vertical (Y) direction to the grains. Thus, the EAS(1) values of Y components are greater than those of X components (Table 1). Switch-ON drain current transients undergo distortion as temperature increases. For temperatures higher than 200 K transient behavior is no longer solely governed by gate oxide polarization. Overshoot effect also comes into play [15,16]; that is a carrier trapping/detrapping process related to the second (s2, EAS(2)) thermally activated mechanism, presented in Fig. 8. To probe the origin of traps contributing to this process, we conducted DLTS measurements. For n-TFTs, the DLTS spectra envelope curve is decomposed in more than one components, each corresponding to a hole trapping/detrapping mechanism likely stemming from grain boundaries within the channel area (Fig. 9). Their activation energies (Table 2) were extracted from the respective Arrhenius plots (Fig. 10). Fig. 10 also includes the closer Arrhenius signatures. The latter
Fig. 8. Arrhenius plots (Eq. (2)), extracted by the fitting analysis data (scattered symbols) according to PSEL (Eq. (1)) and DSEL (Eq. (3)) formulas. The dot lines represent the linear fit process from which activation energies were calculated.
Table 1 Activation energies associated to Arrhenius plot Eq. (2) of Fig. 2 Channel type
Direction
EAS(1) (eV)
EAS(2) (eV)
n n p p
X Y X Y
0.07 0.19 0.08 0.11
0.46 0.40 0.35 0.36
In EAS, S stands for stretched exponential law.
Fig. 9. DLTS spectra of n-TFTs, the channel of which is aligned in parallel (X) direction to the grains.
Table 2 Activation energies derived from DLTS measurements Channel type
Direction
EAD(1) (eV)
EAD(2) (eV)
EAD(3) (eV)
n n p p
X Y X Y
0.46 0.53 0.35 0.35
0.39 0.40 – –
0.52 0.46 – –
In EAD, D stands for DLTS technique.
Fig. 10. Arrhenius plot (derived from DLTS analysis) of n-TFTs, whose channel is aligned: (a) in parallel (X), (b) in perpendicular (Y), direction to the grains. Arrhenius signatures related to: (c) dislocations (dot lines), (d) RTA defects (dash lines).
are associated to: (a) dislocations (DE3, DH3, DISLC2, DH(56%)), which are planar (extended) defects and presented with dot lines, and (b) rapid thermal annealing (RTA) defects (H1(B87), H1(D), QB542) presented with dash lines. For the temperature range between 220 and 350 K, DLTS and stretched exponential law results overlap, if we take into account their respective activation energies. EAS(2) values (Table 1) are within the range of EAD(2) EAD(3) (Table 2). However, stretched exponential analysis cannot predict trapping/detrapping mechanisms for temperatures lower than 220 K.
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4. Conclusions SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented both along the preferential and the non-preferential direction. We observed a non monotonous Vth degradation only for p-channel devices and also channel shortening effects at much longer times, while no significant interface state generation was observed. The reliability dependence on channel orientation proved minor for p-channel TFTs, as opposed to n-channel ones. In order to probe the differences in nand p-film defectivities causing this effect we applied DLTS analysis for n- and p-channel TFTs oriented along both directions. Indeed, the defect nature between the films proved different, featuring similar behavior of both orientations only for p-channel TFTs. Acknowledgement
Fig. 11. DLTS spectra comparison for n- and p-TFTs with their channel oriented in X direction.
The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek General Secretariat for Research and Technology. References
Fig. 12. Arrhenius plot (derived from DLTS analysis) of p-TFTs, whose channel is aligned: (a) in parallel (X), (b) in perpendicular (Y), direction to the grains.
For p-TFTs, DLTS and stretched exponential analysis results are in full accordance. For the temperature range 230–350 K, activation energy values EAS(2) (Table 1) and EAD(1) (Table 2) coincide. These results refer to trapping/detrapping mechanisms probably ascribed to dangling bonds of Poly-Si/SiO2 interface states (PolySi: Polycrystalline silicon). The latter are acceptor-like traps. It has been reported that Poly-Si/SiO2 interface traps are acceptorlike in the upper half and donor-like in the lower half of the Poly-Si band gap [17,18]. While p-TFTs are biased in strong inversion, the fraction of the interface traps associated with the trapping/detrapping mechanisms previously mentioned, is that between mid gap Ei and Fermi level EF [17,18]. This fraction is characterized by unoccupied donors, leading to positively charged interface traps [17,18]. In Fig. 11, an indicative comparison of DLTS spectra, for X oriented n- and p-TFTs, is demonstrated. Their differentiation reflects the origin of the detected defects. The same behavior is extracted for respective TFTs in the Y direction, as shown in the Arrhenius plot of both channel orientations (Fig. 12).
[1] Matsuo T, Muramatsu T. CG silicon technology and development of system on panel. Proc SID Int Symp 2004:856. [2] Sposili RS, Im JS. Sequential lateral solidification of thin silicon films on SiO2. Appl Phys Lett 1996;69:2864. [3] Brotherton SD, McCulloch DJ, Clegg JB, Gowers JP. Excimer-laser-annealed poly-Si thin-film transistors. IEEE Trans Electron Dev 1993;40:407. [4] Voutsas AT. Assessment of the performance of laser-based lateralcrystallization technology via analysis and modeling of polysilicon thin-filmtransistor mobility. IEEE Trans Electron Dev 2003;50:1494. [5] Crowder MA, Moriguchi M, Mitani Y, Voutsas AT. Parametric investigation of SLS-processed poly-silicon thin films for TFT applications. Thin Solid Films 2003;427:101. [6] Voutsas AT, Limanov A, Im JS. Effect of process parameters on the structural characteristics of laterally grown, laser-annealed polycrystalline silicon films. J Appl Phys 2003;94:7445. [7] Farmakis FV, Brini J, Kamarinos G, Dimitriadis CA, Gueorguiev VK, Ivanov TzE. Electrical stress in n- and p-channel undoped-hydrogenated polysilicon thin film transistors (TFTs). Int Semiconduct Conf CAS’99 Proc 1999;1:157. [8] Yamagata M, Satoh T, Tango H. Hot-carrier-induced degradation under current saturation bias in p-channel low-temperature polycrystalline silicon thin-film transistors. Jpn J Appl Phys 2007;46(8A):5044. [9] Moschou DC, Exarchos MA, Kouvatsos DN, Papaioannou GJ, Voutsas AT. A novel SLS ELA crystallization process and its effects on polysilicon film defectivity and TFT performance. Microelectron Eng 2008;85:1447. [10] Moschou DC, Exarchos MA, Kouvatsos DN, Papaioannou GJ, Voutsas AT. Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques. Microelectron Reliab 2007;47:1378. [11] Di Gaspare A, Mariucci L, Pecora A, Fortunato G. Stable p-channel polysilicon thin film transistors fabricated by laser doping technique. Thin Solid Films 2005;487:232. [12] Papaioannou GJ, Exarchos M, Kouvatsos D, Voutsas A. Switch-on overshoot transient decay mechanism in polycrystalline silicon thin-film transistors. Appl Phys Lett 2005;87:252112. [13] Yan F, Migliorato P, Ishihara R. Influence of trap states on dynamic properties of single grain silicon thin film transistors. Appl Phys Lett 2006;88:153507. [14] Exarchos MA, Moschou DC, Papaioannou GJ, Kouvatsos DN, Voutsas AT. Performance of thin-film transistors fabricated by sequential lateral solidification crystallization techniques. In: Proceedings of 3rd international conference micro & nano 2007, Athens, Greece. p. II.23. [15] Exarchos MA, Papaioannou GJ, Kouvatsos DN, Voutsas AT. Drain current overshoot transient in polycrystalline silicon transistors: the effect of hole generation mechanism. J Appl Phys 2006;99:024511. [16] Papaioannou GJ, Voutsas AT, Exarchos MA, Kouvatsos DN. The effect of generation-recombination mechanisms on the transient behavior of polycrystalline silicon transistors. Thin Solid Films 2005;487:247. [17] Schroder DK, Babcock JA. Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 2003;94:1. [18] Schroder DK. Negative bias temperature: what do we understand? Microelectron Reliab 2007;47:841.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique D.C. Moschou a,*, M.A. Exarchos b, D.N. Kouvatsos a, G.J. Papaioannou b, A. Arapoyanni c, A.T. Voutsas d a
Institute of Microelectronics, NCSR Demokritos, Patriarchou Grigoriou and Neapoleos Strs, Aghia Paraskevi 15310, Greece Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece c Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Athens 15784, Greece d Material and Device Applications Laboratory, Sharp Labs of America, Camas, WA 98607, USA b
a r t i c l e
i n f o
Article history: Received 10 June 2008 Available online 3 August 2008
a b s t r a c t SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented both along the preferential and the non-preferential direction. The degradation mechanisms proved very different between n- and p-channel devices, while the channel orientation had a larger effect on n-channel devices than on p-ones. In order to probe the reasons causing this effect we applied DLTS analysis to both n- and p-channel devices oriented along both directions, receiving valuable information about the defectivity differences in n- and p-polysilicon films. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics, VLSI technology and high performance flat panel display applications [1]. The primary advantage of polysilicon TFTs over a:Si ones is their higher field effect mobility and consequently higher drive current. For the fabrication of novel commercial products to be possible, high reliability CMOS circuitry using LTPS TFTs should be available. With recent polysilicon crystallization process breakthroughs, using various excimer laser anneal (ELA) methods such as sequential lateral solidification (SLS), TFT performance has substantially increased [2–6]. Several variations of the SLS technique allow the manufacturing of polysilicon films with excellent intragrain quality and grains of different geometry. However, n- and p-channel devices fabricated in the same film, both required for CMOS circuitry, show much different degradation characteristics [7,8]. In this work, SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented along the preferential and the non-preferential direction. We probed through DC stress their reliability differences and attempted to relate them to their defectivity characteristics, obtained through drain current transient investigation. 2. Experimental The TFTs studied were fabricated in 50 nm thick polysilicon films, formed by ELA crystallization of a:Si, using the M N SLS * Corresponding author. Tel.: +30 210 6503239; fax: +30 210 6511723. E-mail address: [email protected] (D.C. Moschou). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.06.006
technique, specifically described elsewhere [9]. The procedure is conducted at room temperature, using a LPX 315i Lambda Physik excimer laser (XeCl, 308 nm, discharge frequency of 150 Hz) system, with the laser beam shaped by an appropriate mask. This SLS procedure results in larger rectangular domain sizes than other similar multi-shot techniques. The crystal domain being much larger than the TFT channel, no hard grain boundaries are likely to be included in either direction. Moreover, this technique yields a film with fewer sub-boundaries obstructing the current flow in the X orientation of the film (preferential) than in the Y (non-preferential) [9]. However, sub-boundaries are present in both directions, along with nanoprotrusions, known to affect n-channel TFT reliability [9,10]. Both n-channel and p-channel TFTs had a top-metal-gate structure and a PECVD SiO2 gate dielectric. Devices were stressed and characterized using a HP4140B semiconductor analyzer. DC stress was applied to both n- and p-channel devices with L = 2 lm and W = 2 lm and also in p-channel devices with L = 2 lm and W = 1 lm for further investigation. The maximum stress duration was 16 h under the DC stress condition of Vgstress = Vdstress/2. The Ids–Vgs transfer characteristics were taken after each stress cycle and the device parameters extracted from them were the extrapolated threshold voltage Vth, the field effect mobility l and the subthreshold slope S. In order to investigate differences in film defectivity of n- and pchannel TFTs that could explain their reliability characteristics, deep level transient spectroscopy (DLTS) was implemented to record drain current spectra DId(T) (T: temperature), immediately after the transition from OFF- to ON-state. This transition results in sufficient polysilicon band bending from accumulation (OFFstate) to strong inversion (ON-state) condition. DLTS spectra DId(T)
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were extracted for rate window e values ranging from 6.25 s1 to 800 s1. Switch-ON drain current transients DId(t) (t: time) were also recorded. Transients were sampled in the 0–256 ms time interval (tON) with a 1 ms sampling rate. The OFF-state duration (tOFF) was constant at 100 ms, for both DLTS spectra DId(T) and transient DId(t) recording. All measurements extended in the thermal range of 110–400 K. 3. Results and discussion In order to investigate the reliability differences between nchannel and p-channel devices of the same dimensions (W/ L = 2 lm/2 lm), we applied analogous stress biases for Vgs and Vds, utilizing the stress condition Vgstress = Vdstress/2, as mentioned before. For the n-channel devices the stress biases used were Vgstress = 4 V, Vdstress = 8 V [9]. The analogous stress biases used for p-channel devices, observing that their absolute Vth value was about 1 V higher than the n-channel ones, were Vgstress = 5 V, Vdstress = 10 V. In Fig. 1, we see the evolution of the extrapolated threshold voltage Vth for both n-channel and p-channel devices, oriented both along the preferential X and the non-preferential Y direction. For the n-channel devices we see a large difference between the two orientations. For the p-channel devices, on the other hand, the two channel orientations show similar behavior. The largest Vth degradation is observed for the X oriented n-channel device, that has the largest carrier mobility of all the investigated devices [9]. As for the subthreshold slope S of the devices (Fig. 2), the only device showing an increase is again the X oriented n-channel device. All the other devices show almost no S variation, indicating insignificant interface state generation. The previous observation that for the p-channel devices the channel orientation plays a smaller role is further supported considering their mobility values (Fig. 3). While for the n-channel devices the X direction mobility is approximately double than the Y one, p-channel X direction mobility is only about 10% higher than the Y one. Also, both p-channel devices show similar l degradation, with a slight increase for large stressing times, indicating a minor channel shortening effect. This behavior is much different than that of the n-channel TFTs, for which the Y direction shows no degradation at all, but the X direction shows an initial, much swifter channel shortening effect, followed by a large decrease. In order to further investigate whether the degradation mechanisms are similar for more intense stressing, we applied larger
Fig. 1. Evolution of extrapolated threshold voltage Vth Vth0 with stress time for both n- and p-channel devices under analogous stress conditions.
Fig. 2. Evolution of Subthreshold slope S S0 with stress time for both n- and pchannel devices under analogous stress conditions.
Fig. 3. Evolution of field effect mobility l with stress time for both n- and pchannel devices under analogous stress conditions.
stress biases, again under the same Vgstress/Vdstress ratio as previously (Vgstress = 6 V, Vdstress = 12 V), to p-channel devices of both orientations with similar dimensions (W/L = 1 lm/2 lm). Observing the threshold voltage degradation of both X and Y oriented p-channel devices (Fig. 4), we see again very similar behavior for both devices: a small initial increase followed by a logarithmic decrease. The stress gate bias being larger, Vth degradation is also more intense than before. The initial electron trapping, implied by the increase of Vth, has been simulated by Yamagata et al. [8] and attributed to a high vertical electric field under the gate, near the drain junction, attracting hot electrons. For large stressing times, the trapped negative charges increase the potential barrier. Thus electron injection tends towards saturation, allowing hot hole injection, along the whole channel area, to dominate, causing the subsequent logarithmic decrease of Vth. We also see that the subthreshold slope of the devices is again not affected by the stress (Fig. 5), even though the stressing condition is more intense, implying that interface state generation is not favored at this stressing condition for p-channel devices [11]. The stress intensity, however, seems to affect significantly the field effect mobility degradation, since we see a much larger increase for longer stressing times than before (Fig. 6). Despite this larger degradation, we still do not see any decrease of l. This increase of the field effect mobility has been attributed to channel
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Fig. 4. Evolution of extrapolated threshold voltage Vth Vth0 with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
Fig. 5. Evolution of subthreshold slope S S0 with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
Fig. 7. Switch-ON drain current transient behavior for X oriented p-TFTs. The scatter symbols represent the experimental data. The continuous and dot lines, represent the fit process based on PSEL (Eq. (1)) and DSEL (Eq. (3)) formulas respectively.
vices the spreading of the degraded region along the rest of the channel takes longer times, due to a lower lateral electric field [8]. In order to investigate the very similar degradation behavior between the two channel orientations, observed only for p-channel devices and not for n-channel ones, we tried to probe the differences in n- and p- film defectivities applying the DLTS method to unstressed n- and p-channel TFTs (W/L = 8 lm/2 lm). The switch-ON drain current transients of n- and p-channel TFTs exhibited analogous temperature dependence behavior. A transition from undershoot to overshoot effect was observed as the temperature increased. Further analyzing, we observed that there were three regimes (Fig. 7); the first one extended within the range 110–290 K where undershoot-like transients were monitored. The second one, between 290 and 340 K, where the switchON transient behavior is complex, with undershoot and overshoot effect coexisting. Finally, for temperatures within the range 340– 400 K overshoot-like transient behavior was monitored. Fitting analysis based on the stretched exponential law was examined in order to analyze this complex transient behavior [12]. For the first regime transients relaxed through the plain stretched exponential law (PSEL) described by Eq. (1), where DId(t) is the drain current transient, DId(0) the drain current transient at t = 0 (transient amplitude), s the relaxation time and b the stretch exponential factor (0 6 b 6 1). The factor b stands for the complexity of the process through which the transient relaxes. Relaxation time s represents a thermally activated mechanism with a corresponding activation energy EA, described by Eq. (2). Theoretically, s equals s0 for infinite temperature
DId ðtÞ ¼ DId ð0Þ exp½ðt=sÞb s ¼ s0 expðEA =kTÞ
Fig. 6. Evolution of field effect mobility l with stress time for p-channel devices with Vgstress = 6 V and Vdstress = 12 V.
shortening effects [7,8], due to the aforementioned hot electron injection near the drain region. The fact that this channel shortening effect is observed at much larger stressing times, compared to n-channel devices, can be explained if we consider that in these de-
ð1Þ ð2Þ
For the second and third regime, transients relaxed through the dual stretched exponential law (DSEL) described by Eq. (3), denoting that the transient relaxation follows complex mechanisms due to highly disordered material 0
DId ðtÞ ¼ DId ð0Þ exp½ðt=sÞb þ DId ð0Þ0 exp½ðt=s0 Þb
ð3Þ
Drain current transient fitting results with Eqs. (1) and (3) disclosed that relaxation time s consists of two components s1 and s2 (Fig. 8). Each component represents a thermally activated mechanism characterized by an activation energy EAS, derived from an Arrhenius plot according to Eq. (2) (Table 1).
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The first thermally activated mechanism (s1, EAS(1)) is ascribed to polarization of gate oxide [13]. This phenomenon is more pronounced in n-channel TFTs whose polysilicon film was crystallized mainly under 2-shot and 26-shot, as well as under M N#8, laser irradiation schemes [10,14]. In that case, the polysilicon film exhibited enhanced protrusion density. For the present devices studied, advanced M N polysilicon film is marked out for low surface roughness and for small domains, smaller than those of the aforementioned technologies. However, asperities whose height is comparable to the polysilicon film thickness are still monitored. Consequently, the subsequent dielectric film growth on the polysilicon film, would meet high asperities, originating from domains small in size but increased in density. As a result, regions within the gate dielectric film are formed, characterized by the presence of strong electric field, causing dielectric polarization. The latter is more intense for devices, having their channel aligned in vertical (Y) direction to the grains. Thus, the EAS(1) values of Y components are greater than those of X components (Table 1). Switch-ON drain current transients undergo distortion as temperature increases. For temperatures higher than 200 K transient behavior is no longer solely governed by gate oxide polarization. Overshoot effect also comes into play [15,16]; that is a carrier trapping/detrapping process related to the second (s2, EAS(2)) thermally activated mechanism, presented in Fig. 8. To probe the origin of traps contributing to this process, we conducted DLTS measurements. For n-TFTs, the DLTS spectra envelope curve is decomposed in more than one components, each corresponding to a hole trapping/detrapping mechanism likely stemming from grain boundaries within the channel area (Fig. 9). Their activation energies (Table 2) were extracted from the respective Arrhenius plots (Fig. 10). Fig. 10 also includes the closer Arrhenius signatures. The latter
Fig. 8. Arrhenius plots (Eq. (2)), extracted by the fitting analysis data (scattered symbols) according to PSEL (Eq. (1)) and DSEL (Eq. (3)) formulas. The dot lines represent the linear fit process from which activation energies were calculated.
Table 1 Activation energies associated to Arrhenius plot Eq. (2) of Fig. 2 Channel type
Direction
EAS(1) (eV)
EAS(2) (eV)
n n p p
X Y X Y
0.07 0.19 0.08 0.11
0.46 0.40 0.35 0.36
In EAS, S stands for stretched exponential law.
Fig. 9. DLTS spectra of n-TFTs, the channel of which is aligned in parallel (X) direction to the grains.
Table 2 Activation energies derived from DLTS measurements Channel type
Direction
EAD(1) (eV)
EAD(2) (eV)
EAD(3) (eV)
n n p p
X Y X Y
0.46 0.53 0.35 0.35
0.39 0.40 – –
0.52 0.46 – –
In EAD, D stands for DLTS technique.
Fig. 10. Arrhenius plot (derived from DLTS analysis) of n-TFTs, whose channel is aligned: (a) in parallel (X), (b) in perpendicular (Y), direction to the grains. Arrhenius signatures related to: (c) dislocations (dot lines), (d) RTA defects (dash lines).
are associated to: (a) dislocations (DE3, DH3, DISLC2, DH(56%)), which are planar (extended) defects and presented with dot lines, and (b) rapid thermal annealing (RTA) defects (H1(B87), H1(D), QB542) presented with dash lines. For the temperature range between 220 and 350 K, DLTS and stretched exponential law results overlap, if we take into account their respective activation energies. EAS(2) values (Table 1) are within the range of EAD(2) EAD(3) (Table 2). However, stretched exponential analysis cannot predict trapping/detrapping mechanisms for temperatures lower than 220 K.
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4. Conclusions SLS ELA n- and p-channel polysilicon TFTs fabricated with a novel technique were investigated, oriented both along the preferential and the non-preferential direction. We observed a non monotonous Vth degradation only for p-channel devices and also channel shortening effects at much longer times, while no significant interface state generation was observed. The reliability dependence on channel orientation proved minor for p-channel TFTs, as opposed to n-channel ones. In order to probe the differences in nand p-film defectivities causing this effect we applied DLTS analysis for n- and p-channel TFTs oriented along both directions. Indeed, the defect nature between the films proved different, featuring similar behavior of both orientations only for p-channel TFTs. Acknowledgement
Fig. 11. DLTS spectra comparison for n- and p-TFTs with their channel oriented in X direction.
The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek General Secretariat for Research and Technology. References
Fig. 12. Arrhenius plot (derived from DLTS analysis) of p-TFTs, whose channel is aligned: (a) in parallel (X), (b) in perpendicular (Y), direction to the grains.
For p-TFTs, DLTS and stretched exponential analysis results are in full accordance. For the temperature range 230–350 K, activation energy values EAS(2) (Table 1) and EAD(1) (Table 2) coincide. These results refer to trapping/detrapping mechanisms probably ascribed to dangling bonds of Poly-Si/SiO2 interface states (PolySi: Polycrystalline silicon). The latter are acceptor-like traps. It has been reported that Poly-Si/SiO2 interface traps are acceptorlike in the upper half and donor-like in the lower half of the Poly-Si band gap [17,18]. While p-TFTs are biased in strong inversion, the fraction of the interface traps associated with the trapping/detrapping mechanisms previously mentioned, is that between mid gap Ei and Fermi level EF [17,18]. This fraction is characterized by unoccupied donors, leading to positively charged interface traps [17,18]. In Fig. 11, an indicative comparison of DLTS spectra, for X oriented n- and p-TFTs, is demonstrated. Their differentiation reflects the origin of the detected defects. The same behavior is extracted for respective TFTs in the Y direction, as shown in the Arrhenius plot of both channel orientations (Fig. 12).
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