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A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky Barrier FET
Superlattices and Microstructures 93 (2016) 40e49
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky Barrier FET Sangeeta Singh*, Ruchir Sinha, P.N. Kondekar Nanoelectronics and VLSI Lab., Indian Institute of Information Technology, Design and Manufacturing (IIITDM), Jabalpur 482005, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 7 February 2016 Accepted 22 February 2016 Available online 3 March 2016
In this paper, an ultra steep, symmetric and dynamically configurable, electrostatically doped silicon nanowire Schottky FET (E-SiNW-SB-FET) based on dopant-free technology is investigated. It achieves the ultra steep sub-threshold slope (SS) due to the cumulative effect of weak impact-ionization induced positive feedback and electrostatic modulation of Schottky barrier heights at both source and drain terminals. It consists of axial nanowire heterostructure (silicide-intrinsic silicon-silicide) with three independent all-around gates, two gates are polarity control gates for dynamically reconfiguring the device polarity by modulating the effective Schottky barrier heights and a control gate switches the device ON and OFF. The most interesting features of the proposed structure are simplified fabrication process as the state-of-the-art for ion implantation and high thermal budget no more required for annealing. It is highly immune to process variations, doping control issues and random dopant fluctuations (RDF) and there are no mobility degradation issues related to high doping. A calibrated 3-D TCAD simulation results exhibit the SS of 2 mV/dec for n-type E-SiNW-SB-FET and 9 mV/dec for p-type E-SiNW-SB-FET for about five decades of current. Further, it resolves all the reliability related issues of IMOS as hot electron effects are no more limiting our device performance. It offers significant drive current of the order of 105-104 A and magnificently high ION/IOFF ratio of ~108 along with the inherent advantages of symmetric device structure for its circuit realization. © 2016 Elsevier Ltd. All rights reserved.
keywords: Symmetric structure Schottky Barrier FET (SB-FET) Dopant-free Dynamic reconfigurability Random dopant fluctuations (RDF)
1. Introduction Due to the various fundamental challenges at sub-22 nm CMOS scaling, M. Y. Vardi et al. “The Moore's Law & Sand Heap Paradox” [1]. It suggests that due to enormous detrimental effects at this scaled dimensions such as, reduced gate controllability resulting in short channel effects (SCEs), low drive current, sub-threshold leakage as a result of the non-scalability of supply voltage and exponentially increasing leakage power, it is difficult to sustain this law of scaling [2e4]. Hence, he concluded that “Moore's Law is Dying” [1]. Thus, in order to complement or replace the conventional CMOS, several charge based beyond CMOS device architectures such as impact ionization MOS (IMOS) [5,6] and tunnel FETs (TFETs) [7e9] are explored. These devices have fascinated researchers due to their ability to combat the fundamental “Boltzmann Tyranny” of conventional FETS. Hence, they have the potential to scale sub-threshold slope (SS) below 60 mV/dec at room temperature (300 K). This scalability of SS leads to the scalability of supply voltage as well. Further, steep SS is the most feasible solution to reduce the leakage current exponentially as, leakage current (ILeak) is governed by
* Corresponding author. E-mail address: [email protected] (S. Singh). http://dx.doi.org/10.1016/j.spmi.2016.02.039 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
S. Singh et al. / Superlattices and Microstructures 93 (2016) 40e49
ILeak ¼ ID
VTh
VGS ¼VTh
:10 SS
41
(1)
where, ID is drive current, VGS is applied gate-to-source voltage and VTh denotes threshold voltage. Despite of these advantages these devices have major drawbacks as IMOS has high operating voltage and hot electron effects adversely affecting the device reliability [6]. In addition to this, both IMOS and TFET have asymmetric p-i-n structure restricting their circuit level realization in bidirectional current flow paths. TFET's low drive current is the major issue due to which it is still not matured enough to complement CMOS technology. Further, the inclusion of a lateral impact ionization region (I-region) involves the formidable lithography challenges related to the alignment error. These alignment errors, introduced during lithography also affects the device characteristics and reliability negatively [10]. Moreover, as the scaling prevails the ultra-steep doping profile is required for source/drain regions realization in p-i-n structure. As a result of complex fabrication process flow, the scalability of both of these asymmetric devices is detrimental to their electrical characteristics. Moreover, at such aggressively scaled device dimensions, dopant fluctuations [11,12] and dopant activation [13] of highly doped source and drain regions also leads to higher thermal budget. To combat these doping related issues, the electrostatic doping concept is explored for reconfigurable-FET (RFET), apart from the dopant-free nature it also exhibits dynamic reconfigurability, as RFETs can behave either as n or p-FET depending on the biases applied at various gates. It is also investigated experimentally [14e17]. Interestingly, same device can also act either as TFET or IMOS [18]. The concept of dual polarity and symmetric electrical characteristics is explored for its various aspects [19e25]. Still, they suffer from the fundamental thermodynamic limit (kT/q limit) of non-scalable SS. Hence, to combine the dopant-free and symmetric nature with ultra steep SS behavior in single device structure, we investigate an ultra steep, symmetric, dynamically configurable (either as n-type or as p-type) silicon nanowire (SiNW) electrostatically doped Schottky barrier FET (E-SiNW-SB-FET). For the first time, we report ultra steep behavior for the reconfigurable SB-FET. It achieves the ultra steep SS due to the cumulative effect of weak impact-ionization induced positive feedback and electrostatic modulation of Schottky barrier heights at both source and drain terminals. It consists of axial nanowire heterostructure (silicide(source)-intrinsic silicon(channel)-silicide(drain)) having three independent all-around gates (TIGs) for dynamic configuration of Schottky barriers at both source and drain sides. Out of these three gates two gates are polarity control gates (PCGs), employed for dynamically reconfiguring the device polarity by modulating the effective Schottky barrier heights and a control gate (CG) is used for switching the device ON and OFF. To elucidate the potentials of proposed device and physics for device working mechanism in-detail, 3D-TCAD simulations are used. The most interesting features of the proposed structure is its ultra steep SS along with dynamic switching of device polarity and simplified fabrication process. It offers reduced the thermal budget of the device fabrication process, hence it facilitates its fabrication even on single crystal silicon-on-glass substrate by wafer scale epitaxy transfer [26,27]. It promotes the devices potential bio and opto compatibility [28]. TCAD simulation results exhibit the SS of 2 mV/dec for n-type E-SiNW-SB-FET and 9 mV/dec for p-type E-SiNW-SB-FET. All these device performance parameters are in accordance with the requirements of circuit realization along with symmetric structure. Hence, it demonstrates the immense potential as a futuristic low power fast switching symmetric transistors. The remaining parts of this paper are organized as follows: Section 2 incorporates the device structure and simulation methodology. Section 3 focuses on comprehensive analysis of device operating mechanism, and simulation results and discussion. Finally, Section 4 concludes the key findings of this investigation. 2. Device structure and simulation set-up The 3-D schematic, cross-sectional view and proposed circuit symbol of E-SiNW-SB-FET are shown in Fig. 1 (a)-(c) respectively. It consists of axial SiNW having background doping (NIn) as 1 1015 cm3 of radius 10 nm and 170 nm long having heterostructure (silicide(source)-intrinsic silicon(channel)-silicide(drain)). Source and drain contacts are made up of nickel-silicide (NiSi) having barrier height (fB) of 0.45 eV. The orientation of SiNW is considered as 〈110〉. This axial SiNW also enabled future nano-circuits with added performance and functional values based on electrostatic doping, enhanced packaging density and excellent gate controllability due to the gate-all-around (GAA) structure. It has three independent allaround gates, PCGs dynamically reconfigure the device polarity by modulating the Schottky barrier heights and realizes two independent charge injection valves at both source and drain sides. CG turns the device ON and OFF by controlling the channel potential barriers for both n/p-type device. Structurally, both n/p-type devices are similar but they differ in their applied biases at the TIGs. The use of midgap Schottky-barrier source/drain contacts are the key enablers for this device concept to be efficiently functional, hence the affinity of SiNW is considered as cSiNW as 4.05 eV in order to maintain an identical mid-gap Schottky barrier height as 0.41 eV. Further, the midgap Schottky-barrier source and drain configuration promotes its robustness against high temperature environments and atomic abruptness of a Schottky-barrier compared to a conventional PN-junction shows immense potential for the long-term scalability of the devices. In conventional SB-FETs each type of transistor (n/p-type device) has its dedicated metal, corresponding to a specific metal-semiconductor work-function. This obstructs the on-the fly selectivity of the device polarity. Whereas, in the proposed E-SiNW-SB-FET device polarity is electrostatically controlled or voltage-selectable. This on-the fly selectivity of the device polarity facilitates the enhance device design in integrated circuits (ICs) and easy fabrication. Further, in order to isolate the impact of different applied biases
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Fig. 1. (a) 3-D view, (b) schematic cross-sectional view and (c) circuit symbol of n/p-E-SiNW-SB-FET.
at TIGs, we have considered a spacer of silicon nitrite (Si3N4) on both sides of CG. The detailed polarity conditions for the dynamic reconfigurability of these devices polarity by modulating the effective Schottky barrier heights at the source/drain is enlisted in Table 1. The detailed simulation parameters are summarized in Table 2. To investigate the device behavior, we have used the 3D-ATLAS device simulator [29]. This electrostatically induced doping is reported to be well compatible with SB-FETs [30]. To model the Schotkky tunneling and atomic abruptness at the source and drain terminals, Universal Schottky Tunneling (UST) model is included. To incorporate the weak impact ionization resulting in steeper SS behavior of the device, the local electric field model, Selberherr's Impact Ionization model, is also used. The nonlocal dead space effects are being canceled by the velocity overshoot effects in small p-i-n (<100 nm) junctions [31], hence use of local impact ionization is valid at the considered devices dimensions. Further, as the voltages applied at all the TIGs of E-SiNW-SB-FET are much less than the bias required for conventional IMOS, this guarantees only weak impactionization and hence the hot electron effects cannot degrade the device reliability for the proposed device. In addition to this, the default MOS models, to account the doping and field dependent mobility effects Lombardi's Mobility model (CVT), Schottky-Read-Hall (SRH) model for the carrier recombination and Fermi Statistics (FERMI) model for accounting carrier statistics are also used. We have also used the Klaassen (KLA) and Klaassen Band Gap Narrowing (BGN.KLA) models. The simulation framework developed here is calibrated using model [14] as shown in Ref. [31] as well. We have considered this simulation framework to model the dynamic polarity reconfigurability. But our proposed device has NiSi (instead of NiSi2) source and drain with Schottky barrier height is tuned to ensures the thermionic emission region. To get the specific value of Schottky contact barrier height (specifically for thermionic emission region), the activation energy approach is also used for the experimentally fabricated device [17]. For this experimental device there is a linearly decreasing slope of Arrhenius plot, that they have fitted it within 5% error in experimental data with a measured ideality factor of h ¼ 1.84, it clearly indicates the thermionic regime. 2.1. Conduction mechanism of n/p-E-SiNW-SB-FET The conduction mechanism for both n/p-E-SiNW-SB-FET involves on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow is shown in Fig. 2. In order to induce electrostatic doping at the source and the drain side appropriate biases (VPCGs>0V for n-type and VPCGg<0V for p-type devices) are applied at PCGs near source and drain electrodes that realizes highly doped source and drain regions due to electric fields. Now in OFF state of n-type device, a positive drain-to-source bias (VDS) is applied and CG bias is less than the threshold voltage, i.e., VDS>0V and VGS
Table 1 Polarity Conditions for dynamic reconfigurability of polarity for n/p-E-SiNW-SB-FET. Reconfigurable device
VPCG1
VPCG2
VDS
n-E-SiNW-SB-FET p-E-SiNW-SB-FET
3V 3 V
3V 3 V
2V 2V
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Table 2 Simulation Parameters for E-SiNW-SB-FET. Parameters
E-SiNW-SB-FET
Silicon thickness (TSi) Gap spacer length (LGap) Background Doping (NIn) Mid-gate length (LMG) Source gate length (LS) Drain gate length (LD) Gate-oxide thickness (Tox) Source work-function (fS) Drain work-function (fD)
20 nm (diameter of SiNW) 10 nm 11015cm3 50 nm 50 nm 50 nm 15 nm 4.46 eV 4.46 eV
source into the channel thereby it triggers a positive feedback between the control gate bias and the charge flow. Finally, a fraction of generated holes are swept to the source region, this results in lower energy band at the silicide-channel interface of source region. Hence, the effective Schottky barrier is now dynamically reduced and it assists further electrons tunneling towards the channel. This dynamic modulation of Schottky barrier and impact ionization triggered positive feedback is the key enabler of ultra steep SS behavior. Detailed working principle for n-type and p-type E-SiNW-SB-FET are illustrated in Fig. 2(a) and (b), respectively. Here, red color signifies transition point, i.e., VGS¼VTh, blue color indicates VGS>VTh condition and black color is used to show completely ON state, i.e. VGS[VTh. 3. Results and discussions 3.1. n-E-SiNW-SB-FET mode of operation In order to develop the comprehensive understanding of operating mechanism of E-SiNW-SB-FET, the analysis of its charge concentration profile and energy band diagram under different bias conditions is indispensable. Fig. 3(a) depicts charge carrier concentration profile along the device length with horizontal cut-plane (X-X0 ) at the radial top and center of the SiNW for n-E-SiNW-SB-FET under thermal equilibrium state. By applying bias at the two independent PCGs (VPCG1,2) the respective charge carriers are induced in the undoped SiNW. Interestingly, it is noticed that nþ-i-nþ structure is realized on an undoped SiNW even without any metallurgical doping using the electrostatic doping and the concentration profile does not change significantly along the radius of the NW. Hence, the charge plasma formation due to the electrostatic bias is found in congruence with the 3D-TCAD simulation. Fig. 3(b) shows the electron and hole concentration under OFF state (VGS ¼ 0 V, VDS > 2 V) along the X-X0 cut-plane at the radial top and center of SiNW. In OFF state charge carrier concentrations are comparable to the intrinsic SiNW. Fig. 3(c) illustrates the carrier concentration in ON state along the same cut-plane (X-X0 ) at the radial top and center of SiNW. A remarkable increase in the concentration of electrons in the intrinsic channel region is observed under the ON state due to the weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow. Hence, effectively whole undoped SiNW is converted into nþ-nþ-nþ structure in ON state. Fig. 3(d) represents energy band diagram along the device length at the radial top and center of SiNW for n-E-SiNW-SB-FET under thermal equilibrium. The energy band profile corresponds to the nþ-i-nþ structure similar to the conventional FET. Fig. 3(e) exhibits the OFF state energy band diagram along the device length at the radial top and center of the SiNW. In OFF state, as VDS is applied it enhances the injection barriers for the electrons and holes, thereby blocking their flow in OFF state. A positive gate voltage (VGS>VTh) turns the device ON by initiating the weak impact ionization in the channel region, creating huge number of charge carriers. Generated electrons are drifted towards the drain whereas, holes are still accumulated in the channel region, reducing the potential barrier of the channel, and triggers a positive feedback between the control gate bias and the charge flow. ON state energy band diagram along the device length at the radial top and center of the SiNW for n-E-SiNW-SB-FET is shown in Fig. 3(f). It corresponds to the nþ-nþ-nþ structure. This verifies the fact that the electrostatically induced charges are retained in both thermal equilibrium and biased conditions. In order to exemplify the primary requisite of n-E-SiNW-SB-FET to show reliable device behavior (unlike of conventional IMOS), it is imperative to comprehend the weak impact ionization process triggering the positive feedback between gate controlled carrier injection barrier and carrier flow in detail. Hence, the impact ionization carrier generation rate for n-SiNWSB-FET just before and after ON state is shown in Fig. 4(a). As the voltage applied at VDS of n-E-SiNW-SB-FET is only 2 V, it is much less than the bias applied for conventional IMOS (for IMOS devices it is nearly 5 V). This pledges only weak impactionization and hence the hot electron effects cannot degrade the device reliability for the proposed device. Further, due to the GAA nature of the device the impact ionization carrier generation for n-E-SiNW-SB-FET is adequate only for weak impact ionization even at lower operating voltage. It can be observed that impact ionization carrier generation rate is of the order of 1021 charges/cm3.sec, it is clearly in the range of weak impact ionization, as the impact ionization carrier generation rate for conventional IMOS is of the order of 1032 charges/cm3 sec. In addition to this, to envision the steep switching behavior of the device due to positive feedback we have also analyzed the surface potential profile of the device just before and after ON state for n-E-SiNW-SB-FET as depicted in Fig. 4(b). This sudden change in the potential profile under the control gate region advocates the steep transitions of the device. The detailed analysis of hole concentration in the channel region of n-E-SiNW-SB-
Fig. 2. Conduction mechanism of E-SiNW-SB-FET involves on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback, (a) n-type and (b) p-type.
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Fig. 3. Electron and hole concentration of n-E-SiNW-SB-FET along the device length with X-X0 cut-plane at the radial top and center of SiNW under (a) thermal equilibrium (b) OFF state (c) ON state. Energy band diagram for (d) thermal equilibrium (e) OFF state (f) ON state. Thermal equilibrium state is defined as (VCG ¼ 0 V, VDS ¼ 0 V, VPCG1,2 ¼ 3 V). In OFF state VCG ¼ 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V. Under ON state (VCG > 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V.
FET just before and after ON state also reveals the holes accumulation in the channel region, which realizes steep SS behavior as shown in Fig. 5 (a)-(b). To investigate the impact of supply bias (VDS) on electrical characteristics of n-E-SiNW-SB-FET, Fig. 6(a) compares its transfer characteristics (IDVGS) at different values of VDS. It can be inferred from the figure that steep SS behavior of n-E-SiNW-SB-FET is retained with the variation in Ref. VDS. Despite of this, figure also depicts that the drive current and steepness of the transfer characteristics of n-E-SiNW-SB-FET increases significantly with VDS increase. Moreover, VDS variation also has the potential to slightly enhance the ION/IOFF ratio and decrease threshold voltage. The point SS for n-ESiNW-SB-FET is reported as 5.7, 2.3 and 2 mV/dec for VDS as 2, 3 and 4 V, respectively. Further, ION/IOFF ratio for all three biases considered is approximately 108-109. The output characteristics of n-E-SiNW-SB-FET at different values of VCGs are illustrated in Fig. 6(b). As the polarity control gate biases (VPCG1,2) are also expected to alter the device behavior considerably, the transfer characteristics of the device is compared in Fig. 7 (a) for different values of VPCGs. This shows that higher values of VPCGs are desirable for the optimum device drive current and SS is comparatively independent of VPCGs variation. Hence, these characteristics exhibits that supply and control gate have the potential to optimize the device performance. Further, Fig. 7 (b) depicts variation of point SS as a function of drain current at different values of VDS for E-SiNW-SB-FET. Interestingly, the proposed device shows steep SS behavior (< 30 mV/dec) for about five decades of current, i.e., from Ref. 1013 A to 108 A.
Fig. 4. (a) Impact ionization rate (II rate) and (b) surface potential profile for n-E-SiNW-SB-FET just before and after ON state.
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Fig. 5. Holes concentration in the channel region of n-E-SiNW-SB-FET (a) just before and (b) after ON state.
Fig. 6. (a) Transfer characteristics of n-E-SiNW-SB-FET for different values of VDS, (b) effect of CGs bias on the output characteristics (IDVDS) of n-E-SiNW-SB-FET.
Thus, the average SS (SSavg) comes out to be 23 mV/dec for VDS ¼ 2 V. This indicates towards faster transitions over full range of device operation.
Fig. 7. (a) Transfer characteristics of n-E-SiNW-SB-FET for different values of VPCGs (b) variation of point SS as a function of drain current at different values of VDS for n-E-SiNW-SB-FET.
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Fig. 8. Electron and hole concentration of p-E-SiNW-IMOS along the device length with X-X0 cut-plane at the radial top and center of SiNW under (a) thermal equilibrium (b) OFF state (c) ON state. Energy band diagram for (d) thermal equilibrium (e) OFF state (f) ON state. Thermal equilibrium state is defined as (VCG ¼ 0 V, VDS ¼ 0 V, VPCG1,2 ¼ 3 V). In OFF state VCG ¼ 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V.
3.2. p-E-SiNW-SB-FET mode of operation The most promising property of this device is its dynamic reconfigurability along with steep SS behavior and enables bidirectional symmetric current flow, i.e., same device is showing dual polarity decided by the biases at the three independent gates. For n-type E-SiNW-SB-FET VPCG1,2 > 0 V, whereas for p-type E-SiNW-SB-FET VPCG1,2 < 0 V. It is worth mentioning that source and drain terminals will be retained in both n and p-type devices. To comprehend the dynamic reconfigurability of device polarity it is essential to analyze the swapping of charge carriers concentration with swapping of PCGs bias. Fig. 8(a) illustrates the charge carriers profile along the device length with horizontal cut-plane (X-X0 ) at the radial top and center of the SiNW for p-E-SiNW-SB-FET under thermal equilibrium state (VPCG1,2 ¼ 3 V). Interestingly it is noticed that pþ-i-pþ structure is realized even without any metallurgical doping. This on-the fly swapping of the charge carrier is observed as now the polarity of the two PCGs are swapped. Fig. 8(b) and (c) shows the carrier concentration along the device length under OFF and ON state respectively. It is noticeable that the induced charge due to electrostatic doping is retained here as well under both thermal equilibrium and biased states. Fig. 8(c) depicts the electrons accumulation in the region under the control gate. This reduces the potential barrier under the gate, thereby initiating positive feedback between gate controlled carrier
Fig. 9. (a) Transfer characteristics of p-E-SiNW-SB-FET for different values of (a) VDS and (b) VPCGs.
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Fig. 10. Double sweep analysis for the transfer characteristics of (a) n-type and (b) p-type E-SiNW-SB-FET.
injection barrier and carrier flow. Fig. 8(d) depicts energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET. Under thermal equilibrium, the energy band diagram of p-E-SiNW-SB-FET corresponds to the pþ-pþ-pþ structure as expected from the carrier concentration profile. Fig. 8(e) shows the OFF state energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET. ON state energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET is illustrated in Fig. 8(f). It is expected that all other device electrical characteristics such as impact ionization process and surface potential distribution for p-E-SiNW-SBFET will be complementing the n-E-SiNW-SB-FET. Hence to be more precise, Fig. 9 (a) and (b) depicts transfer characteristics of p-E-SiNW-SB-FET for at different values of VDS and VPCGs, respectively. It exhibits the subthreshold slope as 9 mV/dec along with very high ION/IOFF ratio approximately of the order of 108 and average SS (SSavg) comes out to be 37 mV/dec at VDS ¼ 2 V. Further, in order to get symmetric device characteristic compressive strain can also be envisaged in the SiNW to get symmetric device behavior as suggested by Heinzig et al. [25]. This investigation exhibits the enhanced gate controllability and process as well as voltage resilient behavior. Reconfigurability enables easy complementary boolean logic realization and enhances integration density due to symmetric behavior [31]. 3.3. Hysteretic reliability analysis of n/p E-SiNW-SB-FET As these reconfigurable devices are less explored hence the reliability analysis of these reconfigurable devices becomes increasingly important. As hysteresis has emerged as the major hindrance for the successful realization of these steep switching devices. Hence, we have compared the positive and negative voltage sweeps for both the device configuration to get in-detail analysis of hysteretic losses. It is evident from Fig. 10(a) and (b) depict that the positive voltage sweep coincides with the negative voltage sweep for both the configurations. Thus, non-hysteretic behavior of E-SiNW-SB-FET is verified with the TCAD simulations as well. It has magnificently reduced hysteretic losses compared to counterparts with significant hysteresis [31e33]. These double sweeps confirm the negligible hysteresis in the characteristics of the proposed device. In addition to this, the proposed structure offers simplified fabrication process as the state-of-the-art for ion implantation and high thermal budget no more required for annealing. It is highly immune to process variations, doping control issues and RDFs and there are no mobility degradation issues related to high doping. This facilitates its fabrication even on single crystal silicon-on-glass substrate by wafer scale epitaxy transfer along with potential bio and opto compatibility. NW structure combined with the Schottky contacts, excludes the possibility of process variation due to doping fluctuations, low parasitic S/ D resistance, elimination of bipolar action, and low temperature processing. This in turn results in highly reliable and scalable device behavior. 4. Conclusion We have demonstrated the concept of electrostatic biasing based dynamic reconfigurability of the symmetric device polarity with steep switching behavior based on dopant-free technology. Here, we have proposed and investigated an ultra steep, symmetric and dynamically configurable, electrostatically doped silicon nanowire Schottky FET (E-SiNW-SB-FET) by exploiting electrostatic doping. The significant contribution of proposed structure is its dynamic modulation of Schottky barrier height that enables dynamic reconfigurability with an ultra steep SS. Principally, E-SiNW-SB-FET works on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow. This reconfigurability enables easy complementary boolean logic realization and higher integration density due to tunable symmetric behavior. Calibrated 3DTCAD study exhibits SS of 2 mV/dec (n-type) and 9 mV/dec (p-type) for wide range of drain current (over five decades) and ION/IOFF ratio of the order of 108. It avoids the reliability degradation due to hot electron effects (related to I-MOS),
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demonstrates excellent electrostatic control at low voltages and less variation in parameters over a wide range of bias variations, non-hysteretic behavior and its structure assures very low process variability and mobility degradation issues related to high doping. Hence, it demonstrates immense potential as a futuristic low power fast switching symmetric, duallyfunctional devices on a single chip for multifaceted applications. Acknowledgments Authors are thankful to Dr. Neeraj K. Jaiswal, faculty of Physics at PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India, for his guidance in device physics. We also thank PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur for providing infrastructure facilities. References [1] M.Y. Vardi, Moore's law and the sand-heap paradox, Commun. ACM 57 (5) (2014) 5. [2] K.J. Kuhn, Considerations for ultimate CMOS scaling, IEEE Trans. Electron Devices 59 (7) (2012) 1813e1828. [3] P.F. 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Weber, Reconfigurable silicon nanowire transistors, Nano Lett. 12 (1) (2011) 119e124. [15] W. Tang, S.A. Dayeh, S.T. Picraux, J.Y. Huang, K.N. Tu, Ultrashort channel silicon nanowire transistors with nickel silicide source/drain contacts, Nano Lett. 12 (8) (2012) 3979e3985. [16] W.M. Weber, A. Heinzig, J. Trommer, M. Grube, F. Kreupl, T. Mikolajick, Reconfigurable Nanowire Electronics-Enabling a Single CMOS Circuit Technology, IEEE Trans. Nanotechnol. 13 (6) (2014) 1020e1028. [17] M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P. Gaillardon, Y. Leblebici, G. De Micheli, Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs, IEEE Int. Electron Devices Meet. (IEDM) (2012), 8e4. [18] M. Kim, Y. Jeon, Y. Kim, S. Kim, Impact-ionization and tunneling FET characteristics of dual-functional devices with partially covered intrinsic regions, IEEE Trans. Nanotechnol. 14 (4) (2015) 633e637. [19] L. Amaru, P.E. Gaillardon, J. Zhang, G. De Micheli, Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors, IEEE Transaction Circuit Systems- II Express Breifs 60 (10) (2013) 672e676. [20] J. Zhang, M. De Marchi, D. Sacchetto, P.E. Gaillardon, Y. Leblebici, G. De Micheli, Polarity-controllable silicon nanowire transistors with dual threshold voltages, IEEE Trans. Electron Devices 61 (11) (2014) 3654e3660. [21] J. Trommer, A. Heinzig, T. Baldauf, S. Slesazeck, T. Mikolajick, W. Weber, Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors, IEEE Trans. Nanotechnol. 14 (4) (2015) 689e698. [22] M. De Marchi, J. Zhang, S. Frache, D. Sacchetto, P.E. Gaillardon, Y. Leblebici, G. De Micheli, Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs, IEEE Electron Device Lett. 35 (8) (2014) 880e882. [23] J. Zhang, M. De Marchi, D. Sacchetto, P.E. Gaillardon, Y. Leblebici, G. De, Micheli,Polarity-controllable silicon nanowire transistors with dual threshold voltages, IEEE Trans. Electron Devices 61 (11) (2014) 3654e3660. [24] J. Trommer, A. Heinzig, S. Slesazeck, T. Mikolajick, W.M. Weber, Elementary aspects for circuit implementation of reconfigurable nanowire transistors, IEEE electron device Lett. 35 (1) (2014) 141e143. [25] A. Heinzig, T. Mikolajick, J. Trommer, D. Grimm, W.M. Weber, Dually active silicon nanowire transistors and circuits with equal electron and hole transport, Nano Lett. 13 (9) (2013) 4176e4181. [26] W.H. Teh, A. Trigg, C.H. Tung, 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of siliconon-insulator wafers, Appl. Phys. Lett. 87 (7) (2005) 073107. [27] K. Nadda, M.J. Kumar, Thin-film bipolar transistors on recrystallized polycrystalline silicon without impurity doped junctions: proposal and investigation, J. Disp. Technol. 10 (7) (2014) 590e594. [28] H.S. Kima, R.H. Blick, D.M. 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A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky Barrier FET Sangeeta Singh*, Ruchir Sinha, P.N. Kondekar Nanoelectronics and VLSI Lab., Indian Institute of Information Technology, Design and Manufacturing (IIITDM), Jabalpur 482005, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 7 February 2016 Accepted 22 February 2016 Available online 3 March 2016
In this paper, an ultra steep, symmetric and dynamically configurable, electrostatically doped silicon nanowire Schottky FET (E-SiNW-SB-FET) based on dopant-free technology is investigated. It achieves the ultra steep sub-threshold slope (SS) due to the cumulative effect of weak impact-ionization induced positive feedback and electrostatic modulation of Schottky barrier heights at both source and drain terminals. It consists of axial nanowire heterostructure (silicide-intrinsic silicon-silicide) with three independent all-around gates, two gates are polarity control gates for dynamically reconfiguring the device polarity by modulating the effective Schottky barrier heights and a control gate switches the device ON and OFF. The most interesting features of the proposed structure are simplified fabrication process as the state-of-the-art for ion implantation and high thermal budget no more required for annealing. It is highly immune to process variations, doping control issues and random dopant fluctuations (RDF) and there are no mobility degradation issues related to high doping. A calibrated 3-D TCAD simulation results exhibit the SS of 2 mV/dec for n-type E-SiNW-SB-FET and 9 mV/dec for p-type E-SiNW-SB-FET for about five decades of current. Further, it resolves all the reliability related issues of IMOS as hot electron effects are no more limiting our device performance. It offers significant drive current of the order of 105-104 A and magnificently high ION/IOFF ratio of ~108 along with the inherent advantages of symmetric device structure for its circuit realization. © 2016 Elsevier Ltd. All rights reserved.
keywords: Symmetric structure Schottky Barrier FET (SB-FET) Dopant-free Dynamic reconfigurability Random dopant fluctuations (RDF)
1. Introduction Due to the various fundamental challenges at sub-22 nm CMOS scaling, M. Y. Vardi et al. “The Moore's Law & Sand Heap Paradox” [1]. It suggests that due to enormous detrimental effects at this scaled dimensions such as, reduced gate controllability resulting in short channel effects (SCEs), low drive current, sub-threshold leakage as a result of the non-scalability of supply voltage and exponentially increasing leakage power, it is difficult to sustain this law of scaling [2e4]. Hence, he concluded that “Moore's Law is Dying” [1]. Thus, in order to complement or replace the conventional CMOS, several charge based beyond CMOS device architectures such as impact ionization MOS (IMOS) [5,6] and tunnel FETs (TFETs) [7e9] are explored. These devices have fascinated researchers due to their ability to combat the fundamental “Boltzmann Tyranny” of conventional FETS. Hence, they have the potential to scale sub-threshold slope (SS) below 60 mV/dec at room temperature (300 K). This scalability of SS leads to the scalability of supply voltage as well. Further, steep SS is the most feasible solution to reduce the leakage current exponentially as, leakage current (ILeak) is governed by
* Corresponding author. E-mail address: [email protected] (S. Singh). http://dx.doi.org/10.1016/j.spmi.2016.02.039 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
S. Singh et al. / Superlattices and Microstructures 93 (2016) 40e49
ILeak ¼ ID
VTh
VGS ¼VTh
:10 SS
41
(1)
where, ID is drive current, VGS is applied gate-to-source voltage and VTh denotes threshold voltage. Despite of these advantages these devices have major drawbacks as IMOS has high operating voltage and hot electron effects adversely affecting the device reliability [6]. In addition to this, both IMOS and TFET have asymmetric p-i-n structure restricting their circuit level realization in bidirectional current flow paths. TFET's low drive current is the major issue due to which it is still not matured enough to complement CMOS technology. Further, the inclusion of a lateral impact ionization region (I-region) involves the formidable lithography challenges related to the alignment error. These alignment errors, introduced during lithography also affects the device characteristics and reliability negatively [10]. Moreover, as the scaling prevails the ultra-steep doping profile is required for source/drain regions realization in p-i-n structure. As a result of complex fabrication process flow, the scalability of both of these asymmetric devices is detrimental to their electrical characteristics. Moreover, at such aggressively scaled device dimensions, dopant fluctuations [11,12] and dopant activation [13] of highly doped source and drain regions also leads to higher thermal budget. To combat these doping related issues, the electrostatic doping concept is explored for reconfigurable-FET (RFET), apart from the dopant-free nature it also exhibits dynamic reconfigurability, as RFETs can behave either as n or p-FET depending on the biases applied at various gates. It is also investigated experimentally [14e17]. Interestingly, same device can also act either as TFET or IMOS [18]. The concept of dual polarity and symmetric electrical characteristics is explored for its various aspects [19e25]. Still, they suffer from the fundamental thermodynamic limit (kT/q limit) of non-scalable SS. Hence, to combine the dopant-free and symmetric nature with ultra steep SS behavior in single device structure, we investigate an ultra steep, symmetric, dynamically configurable (either as n-type or as p-type) silicon nanowire (SiNW) electrostatically doped Schottky barrier FET (E-SiNW-SB-FET). For the first time, we report ultra steep behavior for the reconfigurable SB-FET. It achieves the ultra steep SS due to the cumulative effect of weak impact-ionization induced positive feedback and electrostatic modulation of Schottky barrier heights at both source and drain terminals. It consists of axial nanowire heterostructure (silicide(source)-intrinsic silicon(channel)-silicide(drain)) having three independent all-around gates (TIGs) for dynamic configuration of Schottky barriers at both source and drain sides. Out of these three gates two gates are polarity control gates (PCGs), employed for dynamically reconfiguring the device polarity by modulating the effective Schottky barrier heights and a control gate (CG) is used for switching the device ON and OFF. To elucidate the potentials of proposed device and physics for device working mechanism in-detail, 3D-TCAD simulations are used. The most interesting features of the proposed structure is its ultra steep SS along with dynamic switching of device polarity and simplified fabrication process. It offers reduced the thermal budget of the device fabrication process, hence it facilitates its fabrication even on single crystal silicon-on-glass substrate by wafer scale epitaxy transfer [26,27]. It promotes the devices potential bio and opto compatibility [28]. TCAD simulation results exhibit the SS of 2 mV/dec for n-type E-SiNW-SB-FET and 9 mV/dec for p-type E-SiNW-SB-FET. All these device performance parameters are in accordance with the requirements of circuit realization along with symmetric structure. Hence, it demonstrates the immense potential as a futuristic low power fast switching symmetric transistors. The remaining parts of this paper are organized as follows: Section 2 incorporates the device structure and simulation methodology. Section 3 focuses on comprehensive analysis of device operating mechanism, and simulation results and discussion. Finally, Section 4 concludes the key findings of this investigation. 2. Device structure and simulation set-up The 3-D schematic, cross-sectional view and proposed circuit symbol of E-SiNW-SB-FET are shown in Fig. 1 (a)-(c) respectively. It consists of axial SiNW having background doping (NIn) as 1 1015 cm3 of radius 10 nm and 170 nm long having heterostructure (silicide(source)-intrinsic silicon(channel)-silicide(drain)). Source and drain contacts are made up of nickel-silicide (NiSi) having barrier height (fB) of 0.45 eV. The orientation of SiNW is considered as 〈110〉. This axial SiNW also enabled future nano-circuits with added performance and functional values based on electrostatic doping, enhanced packaging density and excellent gate controllability due to the gate-all-around (GAA) structure. It has three independent allaround gates, PCGs dynamically reconfigure the device polarity by modulating the Schottky barrier heights and realizes two independent charge injection valves at both source and drain sides. CG turns the device ON and OFF by controlling the channel potential barriers for both n/p-type device. Structurally, both n/p-type devices are similar but they differ in their applied biases at the TIGs. The use of midgap Schottky-barrier source/drain contacts are the key enablers for this device concept to be efficiently functional, hence the affinity of SiNW is considered as cSiNW as 4.05 eV in order to maintain an identical mid-gap Schottky barrier height as 0.41 eV. Further, the midgap Schottky-barrier source and drain configuration promotes its robustness against high temperature environments and atomic abruptness of a Schottky-barrier compared to a conventional PN-junction shows immense potential for the long-term scalability of the devices. In conventional SB-FETs each type of transistor (n/p-type device) has its dedicated metal, corresponding to a specific metal-semiconductor work-function. This obstructs the on-the fly selectivity of the device polarity. Whereas, in the proposed E-SiNW-SB-FET device polarity is electrostatically controlled or voltage-selectable. This on-the fly selectivity of the device polarity facilitates the enhance device design in integrated circuits (ICs) and easy fabrication. Further, in order to isolate the impact of different applied biases
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Fig. 1. (a) 3-D view, (b) schematic cross-sectional view and (c) circuit symbol of n/p-E-SiNW-SB-FET.
at TIGs, we have considered a spacer of silicon nitrite (Si3N4) on both sides of CG. The detailed polarity conditions for the dynamic reconfigurability of these devices polarity by modulating the effective Schottky barrier heights at the source/drain is enlisted in Table 1. The detailed simulation parameters are summarized in Table 2. To investigate the device behavior, we have used the 3D-ATLAS device simulator [29]. This electrostatically induced doping is reported to be well compatible with SB-FETs [30]. To model the Schotkky tunneling and atomic abruptness at the source and drain terminals, Universal Schottky Tunneling (UST) model is included. To incorporate the weak impact ionization resulting in steeper SS behavior of the device, the local electric field model, Selberherr's Impact Ionization model, is also used. The nonlocal dead space effects are being canceled by the velocity overshoot effects in small p-i-n (<100 nm) junctions [31], hence use of local impact ionization is valid at the considered devices dimensions. Further, as the voltages applied at all the TIGs of E-SiNW-SB-FET are much less than the bias required for conventional IMOS, this guarantees only weak impactionization and hence the hot electron effects cannot degrade the device reliability for the proposed device. In addition to this, the default MOS models, to account the doping and field dependent mobility effects Lombardi's Mobility model (CVT), Schottky-Read-Hall (SRH) model for the carrier recombination and Fermi Statistics (FERMI) model for accounting carrier statistics are also used. We have also used the Klaassen (KLA) and Klaassen Band Gap Narrowing (BGN.KLA) models. The simulation framework developed here is calibrated using model [14] as shown in Ref. [31] as well. We have considered this simulation framework to model the dynamic polarity reconfigurability. But our proposed device has NiSi (instead of NiSi2) source and drain with Schottky barrier height is tuned to ensures the thermionic emission region. To get the specific value of Schottky contact barrier height (specifically for thermionic emission region), the activation energy approach is also used for the experimentally fabricated device [17]. For this experimental device there is a linearly decreasing slope of Arrhenius plot, that they have fitted it within 5% error in experimental data with a measured ideality factor of h ¼ 1.84, it clearly indicates the thermionic regime. 2.1. Conduction mechanism of n/p-E-SiNW-SB-FET The conduction mechanism for both n/p-E-SiNW-SB-FET involves on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow is shown in Fig. 2. In order to induce electrostatic doping at the source and the drain side appropriate biases (VPCGs>0V for n-type and VPCGg<0V for p-type devices) are applied at PCGs near source and drain electrodes that realizes highly doped source and drain regions due to electric fields. Now in OFF state of n-type device, a positive drain-to-source bias (VDS) is applied and CG bias is less than the threshold voltage, i.e., VDS>0V and VGS
Table 1 Polarity Conditions for dynamic reconfigurability of polarity for n/p-E-SiNW-SB-FET. Reconfigurable device
VPCG1
VPCG2
VDS
n-E-SiNW-SB-FET p-E-SiNW-SB-FET
3V 3 V
3V 3 V
2V 2V
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Table 2 Simulation Parameters for E-SiNW-SB-FET. Parameters
E-SiNW-SB-FET
Silicon thickness (TSi) Gap spacer length (LGap) Background Doping (NIn) Mid-gate length (LMG) Source gate length (LS) Drain gate length (LD) Gate-oxide thickness (Tox) Source work-function (fS) Drain work-function (fD)
20 nm (diameter of SiNW) 10 nm 11015cm3 50 nm 50 nm 50 nm 15 nm 4.46 eV 4.46 eV
source into the channel thereby it triggers a positive feedback between the control gate bias and the charge flow. Finally, a fraction of generated holes are swept to the source region, this results in lower energy band at the silicide-channel interface of source region. Hence, the effective Schottky barrier is now dynamically reduced and it assists further electrons tunneling towards the channel. This dynamic modulation of Schottky barrier and impact ionization triggered positive feedback is the key enabler of ultra steep SS behavior. Detailed working principle for n-type and p-type E-SiNW-SB-FET are illustrated in Fig. 2(a) and (b), respectively. Here, red color signifies transition point, i.e., VGS¼VTh, blue color indicates VGS>VTh condition and black color is used to show completely ON state, i.e. VGS[VTh. 3. Results and discussions 3.1. n-E-SiNW-SB-FET mode of operation In order to develop the comprehensive understanding of operating mechanism of E-SiNW-SB-FET, the analysis of its charge concentration profile and energy band diagram under different bias conditions is indispensable. Fig. 3(a) depicts charge carrier concentration profile along the device length with horizontal cut-plane (X-X0 ) at the radial top and center of the SiNW for n-E-SiNW-SB-FET under thermal equilibrium state. By applying bias at the two independent PCGs (VPCG1,2) the respective charge carriers are induced in the undoped SiNW. Interestingly, it is noticed that nþ-i-nþ structure is realized on an undoped SiNW even without any metallurgical doping using the electrostatic doping and the concentration profile does not change significantly along the radius of the NW. Hence, the charge plasma formation due to the electrostatic bias is found in congruence with the 3D-TCAD simulation. Fig. 3(b) shows the electron and hole concentration under OFF state (VGS ¼ 0 V, VDS > 2 V) along the X-X0 cut-plane at the radial top and center of SiNW. In OFF state charge carrier concentrations are comparable to the intrinsic SiNW. Fig. 3(c) illustrates the carrier concentration in ON state along the same cut-plane (X-X0 ) at the radial top and center of SiNW. A remarkable increase in the concentration of electrons in the intrinsic channel region is observed under the ON state due to the weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow. Hence, effectively whole undoped SiNW is converted into nþ-nþ-nþ structure in ON state. Fig. 3(d) represents energy band diagram along the device length at the radial top and center of SiNW for n-E-SiNW-SB-FET under thermal equilibrium. The energy band profile corresponds to the nþ-i-nþ structure similar to the conventional FET. Fig. 3(e) exhibits the OFF state energy band diagram along the device length at the radial top and center of the SiNW. In OFF state, as VDS is applied it enhances the injection barriers for the electrons and holes, thereby blocking their flow in OFF state. A positive gate voltage (VGS>VTh) turns the device ON by initiating the weak impact ionization in the channel region, creating huge number of charge carriers. Generated electrons are drifted towards the drain whereas, holes are still accumulated in the channel region, reducing the potential barrier of the channel, and triggers a positive feedback between the control gate bias and the charge flow. ON state energy band diagram along the device length at the radial top and center of the SiNW for n-E-SiNW-SB-FET is shown in Fig. 3(f). It corresponds to the nþ-nþ-nþ structure. This verifies the fact that the electrostatically induced charges are retained in both thermal equilibrium and biased conditions. In order to exemplify the primary requisite of n-E-SiNW-SB-FET to show reliable device behavior (unlike of conventional IMOS), it is imperative to comprehend the weak impact ionization process triggering the positive feedback between gate controlled carrier injection barrier and carrier flow in detail. Hence, the impact ionization carrier generation rate for n-SiNWSB-FET just before and after ON state is shown in Fig. 4(a). As the voltage applied at VDS of n-E-SiNW-SB-FET is only 2 V, it is much less than the bias applied for conventional IMOS (for IMOS devices it is nearly 5 V). This pledges only weak impactionization and hence the hot electron effects cannot degrade the device reliability for the proposed device. Further, due to the GAA nature of the device the impact ionization carrier generation for n-E-SiNW-SB-FET is adequate only for weak impact ionization even at lower operating voltage. It can be observed that impact ionization carrier generation rate is of the order of 1021 charges/cm3.sec, it is clearly in the range of weak impact ionization, as the impact ionization carrier generation rate for conventional IMOS is of the order of 1032 charges/cm3 sec. In addition to this, to envision the steep switching behavior of the device due to positive feedback we have also analyzed the surface potential profile of the device just before and after ON state for n-E-SiNW-SB-FET as depicted in Fig. 4(b). This sudden change in the potential profile under the control gate region advocates the steep transitions of the device. The detailed analysis of hole concentration in the channel region of n-E-SiNW-SB-
Fig. 2. Conduction mechanism of E-SiNW-SB-FET involves on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback, (a) n-type and (b) p-type.
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Fig. 3. Electron and hole concentration of n-E-SiNW-SB-FET along the device length with X-X0 cut-plane at the radial top and center of SiNW under (a) thermal equilibrium (b) OFF state (c) ON state. Energy band diagram for (d) thermal equilibrium (e) OFF state (f) ON state. Thermal equilibrium state is defined as (VCG ¼ 0 V, VDS ¼ 0 V, VPCG1,2 ¼ 3 V). In OFF state VCG ¼ 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V. Under ON state (VCG > 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V.
FET just before and after ON state also reveals the holes accumulation in the channel region, which realizes steep SS behavior as shown in Fig. 5 (a)-(b). To investigate the impact of supply bias (VDS) on electrical characteristics of n-E-SiNW-SB-FET, Fig. 6(a) compares its transfer characteristics (IDVGS) at different values of VDS. It can be inferred from the figure that steep SS behavior of n-E-SiNW-SB-FET is retained with the variation in Ref. VDS. Despite of this, figure also depicts that the drive current and steepness of the transfer characteristics of n-E-SiNW-SB-FET increases significantly with VDS increase. Moreover, VDS variation also has the potential to slightly enhance the ION/IOFF ratio and decrease threshold voltage. The point SS for n-ESiNW-SB-FET is reported as 5.7, 2.3 and 2 mV/dec for VDS as 2, 3 and 4 V, respectively. Further, ION/IOFF ratio for all three biases considered is approximately 108-109. The output characteristics of n-E-SiNW-SB-FET at different values of VCGs are illustrated in Fig. 6(b). As the polarity control gate biases (VPCG1,2) are also expected to alter the device behavior considerably, the transfer characteristics of the device is compared in Fig. 7 (a) for different values of VPCGs. This shows that higher values of VPCGs are desirable for the optimum device drive current and SS is comparatively independent of VPCGs variation. Hence, these characteristics exhibits that supply and control gate have the potential to optimize the device performance. Further, Fig. 7 (b) depicts variation of point SS as a function of drain current at different values of VDS for E-SiNW-SB-FET. Interestingly, the proposed device shows steep SS behavior (< 30 mV/dec) for about five decades of current, i.e., from Ref. 1013 A to 108 A.
Fig. 4. (a) Impact ionization rate (II rate) and (b) surface potential profile for n-E-SiNW-SB-FET just before and after ON state.
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Fig. 5. Holes concentration in the channel region of n-E-SiNW-SB-FET (a) just before and (b) after ON state.
Fig. 6. (a) Transfer characteristics of n-E-SiNW-SB-FET for different values of VDS, (b) effect of CGs bias on the output characteristics (IDVDS) of n-E-SiNW-SB-FET.
Thus, the average SS (SSavg) comes out to be 23 mV/dec for VDS ¼ 2 V. This indicates towards faster transitions over full range of device operation.
Fig. 7. (a) Transfer characteristics of n-E-SiNW-SB-FET for different values of VPCGs (b) variation of point SS as a function of drain current at different values of VDS for n-E-SiNW-SB-FET.
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Fig. 8. Electron and hole concentration of p-E-SiNW-IMOS along the device length with X-X0 cut-plane at the radial top and center of SiNW under (a) thermal equilibrium (b) OFF state (c) ON state. Energy band diagram for (d) thermal equilibrium (e) OFF state (f) ON state. Thermal equilibrium state is defined as (VCG ¼ 0 V, VDS ¼ 0 V, VPCG1,2 ¼ 3 V). In OFF state VCG ¼ 0 V, VDS ¼ 2 V and VPCG1,2 ¼ 3 V.
3.2. p-E-SiNW-SB-FET mode of operation The most promising property of this device is its dynamic reconfigurability along with steep SS behavior and enables bidirectional symmetric current flow, i.e., same device is showing dual polarity decided by the biases at the three independent gates. For n-type E-SiNW-SB-FET VPCG1,2 > 0 V, whereas for p-type E-SiNW-SB-FET VPCG1,2 < 0 V. It is worth mentioning that source and drain terminals will be retained in both n and p-type devices. To comprehend the dynamic reconfigurability of device polarity it is essential to analyze the swapping of charge carriers concentration with swapping of PCGs bias. Fig. 8(a) illustrates the charge carriers profile along the device length with horizontal cut-plane (X-X0 ) at the radial top and center of the SiNW for p-E-SiNW-SB-FET under thermal equilibrium state (VPCG1,2 ¼ 3 V). Interestingly it is noticed that pþ-i-pþ structure is realized even without any metallurgical doping. This on-the fly swapping of the charge carrier is observed as now the polarity of the two PCGs are swapped. Fig. 8(b) and (c) shows the carrier concentration along the device length under OFF and ON state respectively. It is noticeable that the induced charge due to electrostatic doping is retained here as well under both thermal equilibrium and biased states. Fig. 8(c) depicts the electrons accumulation in the region under the control gate. This reduces the potential barrier under the gate, thereby initiating positive feedback between gate controlled carrier
Fig. 9. (a) Transfer characteristics of p-E-SiNW-SB-FET for different values of (a) VDS and (b) VPCGs.
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Fig. 10. Double sweep analysis for the transfer characteristics of (a) n-type and (b) p-type E-SiNW-SB-FET.
injection barrier and carrier flow. Fig. 8(d) depicts energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET. Under thermal equilibrium, the energy band diagram of p-E-SiNW-SB-FET corresponds to the pþ-pþ-pþ structure as expected from the carrier concentration profile. Fig. 8(e) shows the OFF state energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET. ON state energy band diagram along the device length at the radial top and center of the SiNW for p-E-SiNW-SB-FET is illustrated in Fig. 8(f). It is expected that all other device electrical characteristics such as impact ionization process and surface potential distribution for p-E-SiNW-SBFET will be complementing the n-E-SiNW-SB-FET. Hence to be more precise, Fig. 9 (a) and (b) depicts transfer characteristics of p-E-SiNW-SB-FET for at different values of VDS and VPCGs, respectively. It exhibits the subthreshold slope as 9 mV/dec along with very high ION/IOFF ratio approximately of the order of 108 and average SS (SSavg) comes out to be 37 mV/dec at VDS ¼ 2 V. Further, in order to get symmetric device characteristic compressive strain can also be envisaged in the SiNW to get symmetric device behavior as suggested by Heinzig et al. [25]. This investigation exhibits the enhanced gate controllability and process as well as voltage resilient behavior. Reconfigurability enables easy complementary boolean logic realization and enhances integration density due to symmetric behavior [31]. 3.3. Hysteretic reliability analysis of n/p E-SiNW-SB-FET As these reconfigurable devices are less explored hence the reliability analysis of these reconfigurable devices becomes increasingly important. As hysteresis has emerged as the major hindrance for the successful realization of these steep switching devices. Hence, we have compared the positive and negative voltage sweeps for both the device configuration to get in-detail analysis of hysteretic losses. It is evident from Fig. 10(a) and (b) depict that the positive voltage sweep coincides with the negative voltage sweep for both the configurations. Thus, non-hysteretic behavior of E-SiNW-SB-FET is verified with the TCAD simulations as well. It has magnificently reduced hysteretic losses compared to counterparts with significant hysteresis [31e33]. These double sweeps confirm the negligible hysteresis in the characteristics of the proposed device. In addition to this, the proposed structure offers simplified fabrication process as the state-of-the-art for ion implantation and high thermal budget no more required for annealing. It is highly immune to process variations, doping control issues and RDFs and there are no mobility degradation issues related to high doping. This facilitates its fabrication even on single crystal silicon-on-glass substrate by wafer scale epitaxy transfer along with potential bio and opto compatibility. NW structure combined with the Schottky contacts, excludes the possibility of process variation due to doping fluctuations, low parasitic S/ D resistance, elimination of bipolar action, and low temperature processing. This in turn results in highly reliable and scalable device behavior. 4. Conclusion We have demonstrated the concept of electrostatic biasing based dynamic reconfigurability of the symmetric device polarity with steep switching behavior based on dopant-free technology. Here, we have proposed and investigated an ultra steep, symmetric and dynamically configurable, electrostatically doped silicon nanowire Schottky FET (E-SiNW-SB-FET) by exploiting electrostatic doping. The significant contribution of proposed structure is its dynamic modulation of Schottky barrier height that enables dynamic reconfigurability with an ultra steep SS. Principally, E-SiNW-SB-FET works on-the fly modulation of effective Schottky barrier heights at both source and drain terminals and weak impact ionization induced positive feedback between gate controlled carrier injection barrier and carrier flow. This reconfigurability enables easy complementary boolean logic realization and higher integration density due to tunable symmetric behavior. Calibrated 3DTCAD study exhibits SS of 2 mV/dec (n-type) and 9 mV/dec (p-type) for wide range of drain current (over five decades) and ION/IOFF ratio of the order of 108. It avoids the reliability degradation due to hot electron effects (related to I-MOS),
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demonstrates excellent electrostatic control at low voltages and less variation in parameters over a wide range of bias variations, non-hysteretic behavior and its structure assures very low process variability and mobility degradation issues related to high doping. Hence, it demonstrates immense potential as a futuristic low power fast switching symmetric, duallyfunctional devices on a single chip for multifaceted applications. Acknowledgments Authors are thankful to Dr. Neeraj K. Jaiswal, faculty of Physics at PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India, for his guidance in device physics. We also thank PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur for providing infrastructure facilities. References [1] M.Y. Vardi, Moore's law and the sand-heap paradox, Commun. ACM 57 (5) (2014) 5. [2] K.J. Kuhn, Considerations for ultimate CMOS scaling, IEEE Trans. Electron Devices 59 (7) (2012) 1813e1828. [3] P.F. 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