s high speed serial link

Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

Contents lists available at ScienceDirect

International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Regular paper

A power efficient active inductor-based receiver front end for 20 Gb/s high speed serial link Javed S. Gaggatur ⇑, Deepanraj Thulasiraman High Speed Circuits Group, Terminus Circuits Pvt Ltd, Bengaluru 560094, Karnataka, India

a r t i c l e

i n f o

Article history: Received 27 May 2019 Accepted 25 August 2019

Keywords: Receiver front end Continuous time linear equalization SerDes Active inductor

a b s t r a c t A low-power receiver front end (RFE) with 2-tap continuous time linear equalization (CTLE) was designed in 28 nm CMOS technology. The CTLE uses a transconductance-based active inductor for high frequency operation and for area reduction. The active inductor can be tuned around 10 GHz while consuming 7.57 mW from 0.9 V power supply. The CTLE compensates about 7 dB of attenuation due to the channel at a data rate of 20 Gb/s per link, with a power efficiency of 12.6 fJ/bit/dB, nearly 4X better power efficiency than the previous works reported in the literature. It shows prominence in the receivers used for wireline I/O interfaces like USB 3.2 and PCI Express 4.0. Ó 2019 Elsevier GmbH. All rights reserved.

1. Introduction In modern day communications systems consisting of multiple integrated circuits (IC), high-bandwidth communication between these ICs, e.g. between the high-performance microprocessors, computer servers and large storage devices, is one the most critical design issues that the engineers face. With the continuous scaling of feature sizes in the chip manufacturing technology, the speed of on-chip data processing as well as integration have scaled, but the packaging has not scaled at the same rate limiting the interconnect bandwidth. The limitations imposed by the electrical channel (channel noise and attenuation in the received signal) are increasing in significance as per I/O data rates, Fig. 1. A significant contributor to this effect is that the dielectric and resistive losses of the printed circuit board (PCB) traces increase as the operation frequency increases [1]. At speeds of tens of gigabits per second, the loss on FR4 or Rogers boards pose a great challenge, requiring heavy equalization. From the circuit point of view, it is simpler to employ the linear equalization in transmitter (TX) and receiver (RX), consider noise amplification and cross talk (XT). Some of the popular equalization techniques include Feed Forward Equalizer (FFE) used in TX and Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE) in RX. The Inter-symbol interference (ISI) can be effectively reduced by the DFE, but the circuit becomes complex for high speeds. At higher speeds, the

⇑ Corresponding author. E-mail addresses: [email protected] (J.S. Gaggatur), deepanraj. [email protected] (D. Thulasiraman). https://doi.org/10.1016/j.aeue.2019.152886 1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.

received signal strength after the channel gets attenuated to about 32 dB at 8 GHz (PCI Express) [2]. On the other hand, CTLE can compensate full frequency band and does not require clock signals. This paper describes the design of CTLE using active inductor load for bandwidth extension. The rest of the paper is organized as follows: Section 2 describes the principle of equalization and the active-inductor topologies for high speed designs. Section 3 discusses the circuits design of the proposed modified active-inductor and the simulation results are discussed in Section 4. Section 5 summarizes and concludes the paper.

2. Principle of equalization 2.1. Basics of equalizers The Equalizers compensate the channel bandwidth limitations by adding the inverse frequency response of channel and consequently removing the effects of ISI. The inverse frequency response is obtained by amplifying the high frequency components in advance to compensate the channel loss, as shown in Fig. 2. The receiver equalization can be classified as linear and non-linear equalization. The linear equalizers have finite impulse response, and have a feed forward structure where the equalizer output is not fed back to its input. The non-linear equalizers have infinite impulse response, and have a feedback structure where the equalizer output is fed back to its input. This type of equalizers are used when there is a severe channel distortion, and mainly used in removal of ISI. The linear equalizers are further classified as

2

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

Fig. 1. Block Diagram of a typical high speed serial link transceiver with the channel characteristics (inset) [3] for known data rates of 3.125 G.Hz to 12.5 GHz.

Fig. 2. Basic concept of equalization is to compensate the high frequency attenuation by the channel.

discrete time linear equalizer (DTLE) and continuous time linear equalizer (CTLE). The DTLE are constructed on FIR structures, and requires clocks recovered from the received data. And thus a clock and data recovery (CDR) circuit is required. As data rate increases the number of taps in FIR increases, due to which the circuit becomes complex and consumes more power. This codependency of CDR and high power consumption can be eliminated by using CTLE. The CTLE is a simple structure and hence comparably consumes less power.

gives
20 dB/decade, thus in total this circuit gives
40 dB/decade. The transfer function is given as [4,5],

s þ RS1C S   s þ RD1CD s þ RS C S

HðsÞ ¼

gm
CL

HðsÞ ¼

gm s þ xZ C L ðs þ xP1 Þðs þ xP2 Þ

ð1Þ

g R 1þ m2 S

ð2Þ

where 2.2. Continuous time linear equalizer The structure of traditional CTLE is source degenerated differential pair as shown in Fig. 3a where g m is the transconductance of input transistors, RD and C L are load resistance and capacitance, RS and C S are source degeneration resistance and capacitance. This circuit is two pole and a zero system, which provides peaking at Nyquist frequency. The zero gives a +20 dB/decade slope and a pole

xZ ¼

1 RS C S

xP1 ¼

1 þ gm2RS RS C S

xP2 ¼

1 RD C D

ð3Þ

The pole and zero frequency values can be adjusted by varying the RS and CS values. Increasing RS moves zero to lower frequencies thus reducing DC gain and increasing CS moves zero and first pole to lower frequencies as shown in Fig. 4. However this topology suffers from bandwidth limitations and thus lacking compensation

Fig. 3. Continuous Time Linear Equalization for SerDes Receiver: (a) with resistive load (b) with passive inductor load.

3

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

negative transconductance and the CG and CD stages offers positive transconductance. Hence a single ended grounded active inductor can be implemented by using CS-CG stages or CS-CD stages, as shown in Fig. 6a. The parameters of the RLC equivalent circuit are derived from the small signal equivalent circuit of the nMOS version, as shown in Fig. 6b. The input impedance is given as,




Z in ¼

sRC gs þ 1 sRC gs þ g m



ð8Þ

From Z in , we notice that zero frequency xz ¼ RC1gs and pole fre-

quency xP ¼ Cgmgs . And similarly the input admittance, Y in is given by,

1 Y in ¼ þ R s Y in ¼ Fig. 4. Tunability of CTLE.

1 RC gs g m
1R

ð9Þ

þ g 1
1 m

R

1 1 þ Rp ðsL þ Rs Þ

ð10Þ

The equation of Yin can be represented by a RL circuit where at higher frequencies. This problem was rectified by using inductor load as shown in Fig. 3b. The addition of inductive load increases the bandwidth of the CTLE by inductive peaking technology. The transfer function of the inductive load CTLE is given by,

HðsÞ ¼

g m RD 1þ

g m RS 2

:

1 þ xsZ1 1 þ xP1 s

:

1þ s   xZ2   2 1 þ x2fn s þ xs 2

ð4Þ

RC gs ; g m
1R

RS ¼

1 g m
1R

ð11Þ

For the transconductance g m to behave as an inductance L, at the desired frequency of 10 GHz, it has to satisfy the condition g m < 1R (Fig. 6b). The next section discusses the design and implementation of the active inductor and the CTLE.

n

where

xZ2

RP ¼ R; L ¼

3. Circuit design

sffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
sffiffiffiffiffiffiffiffiffiffiffiffi RD CD 1 ; xn ¼ ¼ 2fxn ; f ¼ ðC D LD Þ 2 LD

ð5Þ

2.3. Folded transconductance-based active inductor The active inductor can be realized by the traditional Gyrator-C topology as shown in Fig. 5a. Where the Gm1 ; Gm2 and GO1 ; GO2 are linear transconductance and their corresponding output conductance respectively, and C 1 ; C 2 are port capacitances. At frequencies less than the selfresonance, the input impedance Z in is equivalent to the passive circuit shown in Fig. 5,b

C1 ; CP ¼ C2 Gm1 Gm2 GO1 1 R1 ¼ ; RP ¼ GO2 Gm1 Gm2 L¼

ð6Þ ð7Þ

In order to attain high frequency operation, the Gm1 and Gm2 are realized using single-transistor amplifiers, such as common source (CS), common gate (CG) and common drain (CD) stages and their intrinsic capacitances acts as C1 and C2. The CS stage offers

(a) Traditional Gyrator-C

In high frequency circuit design, passive inductors are used to increase the selectivity of the signal and act as a tuned load [9]. Fig. 3b shows an implementation of a CTLE using passive inductors as the load. The Q-factor and the selectivity is high due to the usage of a passive inductor, but at the cost of large area and less tuning range. As the design integration is getting easier with scaling of the feature sizes of the CMOS technology, area comes at a premium. The CTLE topology in Fig. 3b consumes more area due to the use a passive inductor. To make the CTLE area efficient, the passive inductor is replaced with an active inductor, a PMOS current-reuse transconductance. The proposed alternative solution saves the chip area and also increases the bandwidth, with a minor penalty in the phase noise. The value of the inductance for the desired frequency (10 GHz) can be tuned by the RD transistor and the inductance range is given by g m < 1=RD (11), that depends on the g m and RD values. The proposed CTLE is designed in 28 nm low power CMOS technology and the simplified schematic is shown in Fig. 7. The input transistors M1 -M 2 in the first stage, provide the peaking and DC gain along with the active-inductor based load M 3 -M 4 -RD . In order to provide increased gain for the high frequencies (7 GHz to 10 GHz), an additional peaking amplifier stage is implemented by

(b) Gyrator-C equivalent circuit

Fig. 5. The traditional Gm-C circuits with its small signal equivalent [6,7].

4

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

Fig. 6. Wu Folded active inductor, (a) nMOS and pMOS implementations, (b) Small signal equivalent circuit of nMOS version of Wu AI [8].

Fig. 7. The proposed area-efficient active inductor load-based continuous time linear equalization (CTLE) for 20 Gbps SerDes Receiver including with tunable resistors RS and RD with the capacitor filter bank C S .

a cross coupled nMOS pair M 5 -M 6 , and also a RS0
S2 ; RD0
D1 and C S0
S1 banks are added and rearranged to provide better performance and while consuming less power. The RS and RD are realized by the drain to source resistance (RDS ) due to the voltage

Table 1 Device dimensions. Device

Geometry/ Value

M1-M2 M3-M4 M5-M6 M7-M10 RD0 RD1 RS CS

60 lm/30 nm 50 lm/60 nm 20 lm/30 nm 70 lm/100 nm 1.4 KX 2.14 KX 30–70X 10-20fF

Fig. 8. Layout screenshot of the Continuous Time Linear Equalizer designed to operate at 10 GHz with tunable DC gain stages and high frequency gain.

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

5

Fig. 9. The simulation test-bench to measure the performance of the receiver equalizer using PRBS31 data as input, fed through the channel (FR4 s-parameter model) having 30 dB attenuation at 10 GHz frequency and an input terminated receiver front end.

applied at the gate. The geometries of the transistors and the values of the resistance and capacitance are presented in Table 1. The sizes of M 1 -M 2 are kept high to operate at high frequencies with a large g m . Digital tuning is provided to control the gain and peaking frequencies which allows the circuit to be tuned during post-silicon operation. Fig. 8 shows the layout screenshot of the CTLE operating for 20 Gb/s data rate, but occupying an area of 53lm  26lm. 4. Results and discussions The proposed CTLE with active inductor was implemented in the CMOS 28 nm in low power (LP) process technology where

the devices are optimized to operate with lower leakage in the standard cells, which impacts the operation of the transistors in high frequency range. It impacts the output linearity due to a narrow range of operation [10,11]. Fig. 9 shows the simulation test-bench for the DUT (CTLE) where TP1 and TP2 are the test probe points for the input and output of the DUT, respectively. The signal at TP1 is the output from the channel, package and electrostatic discharge (ESD) device. The far end of the channel at the receiver is terminated with a resistance of 50 X. The channel is expected to have as low-pass characteristic, with the high frequency components of the signal getting attenuated and the low frequency signal not facing any attenuation, as shown in the upper half of Fig. 10a.

Fig. 10. (a) Transient simulation of a typical high speed serial link receiver, (b) CTLE gain across PVT corners.

6

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

frequency components having a boost in the gain with the low frequency signals attenuated to match the gain of the high frequency components. The CTLE allow the signal amplitude recovery without affecting the timing of received data. Fig. 10b shows the variation of process, voltage and temperature (PVT). The simulations for the noise in the supply voltage and the thermal noise of the devices were performed and overlaid with the PVT variations. The impact of the cumulative variations are summarized below: 1. Fig. 10b shows the CTLE gain across all PVT corners where the peak gain ranges from 2.88 dB to 7.3 dB for a frequency range of 10 GHz to 20 GHz and the DC gain spread of 2.5 dB. 2. The DC gain tunability of 2.5 dB, while keeping the peaking frequency constant, the design is achieved by varying RS , as shown Fig. 11a. 3. The peak gain tunability by RD gives a gain variation from 5.5 dB to 9.5 dB at 10 GHz, keeping the DC gain constant, is as shown in Fig. 11b.

Fig. 11. Gain for different settings (a) RS (b) RD .

The Fig. 10a shows signals as seen at TP1 and TP2, the input and output of the CTLE, respectively. At TP1, the bits are shown not to have an overlap with the differential signal and have the potential to lose the bit information, and are critical to keep the bit error rate (BER) under 10
12 . These critical signals (highlighted in Fig. 10a) have been equalized and show overlap at TP2, with the high

The transfer function of the CTLE with active inductance given by (2) and the response is shown in Fig. 12. It can be observed that 18 dB out of the 30 dB channel attenuation at 10 GHz has been recovered. The CTLE output is sufficient for the decision feedback equalizer (DFE) and the sampler in the receiver of the SerDes to recover the data without any inter-symbol interference (ISI) (see Fig. 13). Fig. 14a and b show the eye-diagrams of the received signals at a data rate of 20 Gb/s before and after the CTLE. Refer Fig. 9 for the test probe points TP1 and TP2. It can be observed that the amplitude difference between the high frequency and low frequency components have been equalized to maintain the same amplitudes, thereby increasing the eye height and width and reducing the jitter at the signal crossovers. Table 2 shows the summary of the CTLE at the data rates of 10 Gb/s and 20 Gb/s with the respective eye openings. The current implementation is compared with the other stateof-the-art works given in Table 3. The performance of the proposed active-inductor based CTLE for 20 Gb/s receiver compensates a higher loss in the channel and without any eye monitoring circuit. The figure of merit (FoM) is defined as

FoM ¼

Total Power Data Rate  Channel Loss

ð12Þ

Fig. 12. The transfer function of the channel and the high-frequency gain-compensated response after the CTLE. It can be observed that 18 dB out of the 30 dB channel attenuation at 10 GHz has been recovered.

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

Fig. 13. Eye Diagrams as seen at the 10 Gb/s receiver (a) Before CTLE (TP1) (b) After CTLE (TP2), in Fig. 9.

Fig. 14. Eye Diagrams as seen at the 20 Gb/s receiver (a) Before CTLE (TP1) (b) After CTLE (TP2), in Fig. 9.

7

8

J.S. Gaggatur, D. Thulasiraman / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152886

Table 2 Summary of the eye opening at 10 Gb/s and 20 Gb/s data rates Figure

Data Rate

UI

Eye Height (mV)

Eye Width (ps)

Absolute Jitter (ps)

Fig. 13b Fig. 14b

10 Gb/s 20 Gb/s

100 ps 50 ps

33.5 43.5

82.12 30.72

17.53 18.95

Acknowledgement

Table 3 Performance Comparison with the state-of-the-art. References Technology Equalization Adaptation Data Rate (Gb/s) Channel loss (dB) Supply (V) Power (mW) FOM (fJ/bit/dB)

[12]

[13]

[4]

This Work

65 nm DFE YES 10 16.2 1.2 24 148

65 nm CTLE + DFE YES 10 25 – 66 264

28 nm CTLE YES 1.25–12.5 6–21 0.9/1.8 12 46

28 nm CTLE NO NO 10 20 16.2 30 0.9 0.9 4.1 7.57 25.3 12.6

The proposed figure of merit normalizes the channel loss, transmission data frequency, and power consumption, which compares the system performance under the same evaluation index, and can make a more comprehensive measurement [4]. The activeinductor peaking technology expands the compensation ability of the equalizer, which can achieve the signal frequency range to 20 Gbps, and channel losses range from
24 dB to
30 dB. The FoM of the equalizer, with a power efficiency of 12.6 fJ/bit/dB is clearly superior to the other designs, which means that this design achieves better compensation ability for same data rate. 5. Summary and conclusion This paper shows the implementation of a continuous time linear equalizer for a 20 Gb/s high speed serial link receiver with an area efficient active-inductor load. In high speed serial receivers, inductors are used in CTLE to enhance the bandwidth of operation, but the passive inductors consume more chip area. In this work, the passive inductors are replaced by active inductors for area efficiency and tunablity in the inductance value at the desired frequency. The CTLE is designed and implemented in 28 nm low power CMOS technology, with a supply voltage of 0.9 V and power consumption of 4.1 mW for single stage CTLE and 7.57 mW for complete 2-stage CTLE. The CTLE compensates 19.5 dB due to the channel with a power efficiency of 12.6 fJ/bit/dB, nearly 4X better power efficiency than the previous works reported in literature. The proposed CTLE shows prominence in low power implementations of receivers for high speed wireline I/O interfaces like USB 3.2 and PCI Express 4.0 and above. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

The authors would like to thank the members of Terminus Circuits Pvt Ltd for the technical discussions and funding the research project and the management of the PESIT-South Campus for allowing the internship in Terminus Circuits Pvt Ltd. References [1] Emami-Neyestanak A, Varzaghani A, Bulzacchelli JF, Rylyakov A, Yang CK, Friedman DJ. A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE. IEEE J Solid-State Circ 2007;42(4):889–96. https://doi.org/ 10.1109/JSSC.2007.892156. [2] SIG P. PCI Express 4.0 Specifications 1.0, https://pcisig.com/specifications, Oct 2017. [3] Weber C, He J, Zhong L, Liu H. Multiband architecture for high-speed serdes 2011;3:1674–90. [4] Cai C, Zhao J-Z, Zhou Y-M. A 1.25-12.5 Gbps Adaptive CTLE with asynchronous statistic eye-opening monitor. J Electr Comput Eng 2018. [5] Pantoli L, Stornelli V, leuzzi G. A low-voltage low-power 0.25m integrated single transistor active inductor-based filter. Analog Integ Circ Signal Process 2016;87. https://doi.org/10.1007/s10470-016-0727-z. [6] Thanachayanont A. CMOS transistor-only active inductor for IF/RF applications. 2002 IEEE International Conference on Industrial Technology, 2002. IEEE ICIT’02, vol. 2. IEEE; 2002. p. 1209–12. [7] Wu Y, Ding X, Ismail M, Olsson H. RF bandpass filter design based on CMOS active inductors. IEEE Trans Circ Syst II: Analog Digital Signal Process 2003;50 (12):942–9. [8] Wu C-H, Liao J-W, Liu S-I. A 1V 4.2 mW fully integrated 2.5 Gb/s CMOS limiting amplifier using folded active inductors. 2004 IEEE International symposium on circuits and systems, vol. 1. IEEE; 2004. p. I–1044. [9] Lee Y-SM, Sheikhaei S, Mirabbasi S. A 10Gb/s active-inductor structure with peaking control in 90nm CMOS. In: 2008 IEEE asian solid-state circuits conference. IEEE; 2008. p. 229–32. [10] Gaggatur JS, Raja I, Banerjee G. On-chip non-intrusive temperature detection and compensation of a fully integrated CMOS RF power amplifier. In: 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID). p. 21–6. https://doi.org/10.1109/ VLSID.2017.35. [11] Gaggatur JS, Banerjee G. Noise analysis in ring oscillator-based capacitance sensor interface. In: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS). p. 1–4. https://doi.org/10.1109/ MWSCAS.2016.7870078. [12] Yuan S, Wang Z, Zheng X, Wu L, Zhang C, Wang Z. A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology. In: 2014 IEEE international conference on electron devices and solid-state circuits. IEEE; 2014. p. 1–2. [13] Dolan M, Yuan F. An adaptive edge decision feedback equalizer with 4PAM signalling. In: 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE; 2017. p. 535–8.