A review of III–V semiconductor based metal-insulator-semiconductor structures and devices

Thhz Solid Films, 231 (1993) 107-124

107

A review of I I I - V semiconductor based metal-insulatorsemiconductor structures and devices D. S. L. Mui*, Z. Wang and H. Morkoq University of Illinois, Materials Research Laboratory, 104 South Goodwin Avenue, Urbana, IL 61801 (USA)

Abstract

Recent breakthroughs in the deposition of multilayer semiconductor/dielectric systems have potentially paved the way for metal-insulator-semiconductor (MIS) structures with excellent interface properties to be achieved. In this paper, we review the recent progress in I I I - V MIS structures and devices. The semiconductors of interest are Ino.53Gao.47As, lnP, and GaAs with their excellent electrical properties. These I I I - V semiconductor based MIS structures have shown steady progress over the past few years, taking advantage of the in situ deposited heteromorphic insulators that led to insulator/III-V compound semiconductor (ICS) interfaces with low interface trap density. Though preliminary in nature, with Si3N 4 gate dielectric, minimum interface state densities in the region of low 10~°eV-t cm -2 have been obtained in GaAs albeit with some frequency shift and a deep interface trap. The structures in InGaAs have so far shown minimum interface state densities in the low 10tt eV -~ cm -2 region and very little frequency dispersion. They are void of mid-gap interface traps, and given the recent ongoing developments, it is extremely likely that interface state densities similar to those in GaAs should be possible shortly. Metal-insulator-semiconductor field effect transistors with transconductances of over 200 mS mm- ~ have already been fabricated in InGaAs channels. In situ insulator deposition has been demonstrated to be very effective in avoiding interfacial contamination, for example, oxygen, water vapor, and carbon, a scheme deemed extremely pivotal in the eventual realization of high quality ICS interfaces. Apart from technological difficulties in realizing I I I - V semiconductor MIS devices, interpretation of the electrical properties of ICS interfaces is still not well understood. Also discussed in this paper are the issues involved in characterizing ICS interfaces.

1. Introduction

The pivotal role played by the silicon m e t a l - o x i d e semiconductor field effect transistor ( M O S F E T ) is well established both in the market place and the technical literature. The almost ideal SiO2-Si interface has made the integration of over a million silicon transistors on a single chip possible. To date, the SiO2-Si interface is the best understood semiconductor dielectric interface, and it is rather routine to obtain interface trap densities on the order of 10~°eV-~cm -2 at least part way through processing. Analogous devices in c o m p o u n d semiconductor structures, having more favorable characteristics over silicon, have not come to full fruition because of the absence of a good quality dielectric and dielectric-semiconductor interface. The lack of a viable technology to produce high quality interfaces has prevented reliable investigations and comprehensive understanding of compound semiconductor dielectric interfaces. Recent developments in the deposition of high quality in situ insulator/semiconductor stacks have

*Present address: Department of Electrical Engineering and Computer Science. University of California, Santa Barbara, CA 93106, USA.

fortuitously made it possible to obtain i n s u l a t o r / I I I - V c o m p o u n d semiconductor (ICS) interfaces with an interface trap density below 10 tl eV -t cm -2. It is the purpose of this article to review the recent progress on I I I - V m e t a l - i n s u l a t o r - s e m i c o n d u c t o r (MIS) structures. Because surface contaminants, such as oxygen and water vapor, readily react with an otherwise defect-free I I I - V semiconductor surface and form a high density of surface defects, it is therefore crucial to avoid contamination of the I I I - V semiconductor surfaces before the gate dielectric deposition. There has been a plethora of approaches by which to accomplish dielectric I I I - V c o m p o u n d interfaces suitable for device applications. Naturally, it is not possible to include, in this review, each approach taken up to present. Instead, we will concentrate on recent results obtained utilizing in situ deposited MIS samples because in situ deposition appears to have the promise of gate quality dielectric. Here the phrase "in situ deposition" means that the gate insulator is deposited onto either as-grown or cleaned I I I - V surface. It should be pointed out that in both cases the I I I - V surface is maintained under vacuum after growth or cleaning for the ensuing insulator deposition to take place. The promise of in situ deposition will be established by drawing comparisons with e x situ deposited dielectrics.

Elsevier Sequoia

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D. S. L. Mui et al. / II1- V semicomhwtor M I S devices

The organization of this paper is as follows. First, the general characteristics of ICS interfaces are discussed, followed by a brief discussion of the experimental setup for performing in s i t u deposition in Section 3. Because of a variety of electrical characteristics of ICS interfaces, compared with the SiO2-Si interface, most interface characterization techniques which were developed for SiO2-Si cannot be applied directly to ICS interfaces. Therefore, in order to compare results obtained from different research groups which may use a plethora of characterization techniques, the salient features of several of the well established interface characterization techniques when applied to ICS interfaces are discussed in Section 4. This is followed by a discussion of the characteristics of various in s i t u deposited ICS interfaces, namely insulator/Ino.53Gao.47As , insulator/ Si/Ino.53Gao.47As, insulator/InP, and insulator/Si/GaAs, in Section 5. Comparisons between in situ and e x situ deposited samples are also made in Section 5. Finally, recent results of MIS field effect transistors (FET) are discussed in Section 6.

2. The insulator/lll-V semiconductor interface When I I I - V MIS research began, the majority of the work was expended on the use of native oxides of I I I - V semiconductors [1, 2]. However, it was observed that these native oxides are very leaky and ICS interfaces generally possess a high density of traps. In some semiconductors, notably GaAs, the density of interface traps is so high that the interface Fermi energy is pinned at a fixed energy. A high density of interface traps does not only degrade the performance of MISFETs, it also makes electrical characterization more difficult to perform. Furthermore, the electrical behavior of ICS interfaces is such that the interface characterization methods developed for the SiO2-Si interface are not directly applicable. This may result in questionable interpretations of the measured data. In addition, the leaky native oxides were not conducive for electrical characterization of these interfaces. Owing to these difficulties with native oxides, attention was turned to deposited insulators. Widely used examples include Si3N 4 [3-5], SiO2 [6-9], and AleO 3 [10, 11]. Recently, more novel materials [12-15] have also been used as gate insulators on I I I - V semiconductors. It is useful to discuss here the sequence of process steps which generally takes place in the growth of I I I - V MIS structures. The growth sequence turns out to be just as important as the conditions under which the insulator is deposited. In conventional approaches, the I I I - V semiconductor is grown first by one of the several crystal growth methods, i.e. molecular beam epitaxy (MBE), metal-organic chemical vapor deposi-

tion (MOCVD), and liquid phase epitaxy (LPE) to name a few. The sample is then transferred to another chamber for insulator deposition. However, during sample transfer the sample surface is exposed to air, resulting in uncontrollable oxidation and contamination. This e x situ deposition process is most probably the source of the typically high density of traps at ICS interfaces. Strictly speaking, the insulator is inevitably deposited onto residual native oxides rather than onto an atomically clean I I I - V semiconductor surface. However, it is interesting to note that ICS interfaces obtained with deposited insulators have been reported to be of higher quality than those formed exclusively with native oxides [7, 16]. This observation can be explained partially by the fact that leakage current through the deposited insulators is virtually eliminated, making measured data more reflective of the real interface properties. In addition, high quality insulators imply that the current with trap assisted tunneling [17] is likely to be less in deposited insulators compared with native oxides. This could also account for the difference in interface properties. The use of deposited insulators has improved the qualities of the ICS structure to a point at which operational MISFETs have been demonstrated [5, 8, 18, 19]. However, it should be mentioned that most improvements have been achieved in In0.53Ga0.47As and InP, while GaAs has shown much less improvement. It can be inferred that the trap density of the insulator-indium I I I - V semiconductor interfaces is much lower than that of the insulatorGaAs interface. Measurements have been performed on various clean semiconductor surfaces to establish either the presence or absence of intrinsic band gap states. Some of these experiments measure directly the surface Fermi energy by X-ray photoemission spectroscopy (XPS) while others rely on the measured barrier heights of Schottky contacts formed on clean surfaces followed by indirect correlation with intrinsic band gap states. It has been confirmed that the surface Fermi energy of vacuum cleaved GaAs (110) surface [20-22] has no intrinsic band gap states. Using soft XPS, it has been confirmed [23] that the surface Fermi energy of clean MBE grown InxGam _,.As (x > 0) (100) surface is not pinned. This conclusion is consistent with that of refs. 5 and 24. The fact that the surface Fermi energy of both the GaAs (110) and In,.Ga~_,.As surfaces is not pinned makes these surfaces suitable for MIS applications. However, photoemission spectroscopy measurements on GaAs (I00) surface [25] have shown that the surface Fermi energy is pinned around the mid gap. Svensson et al. [25] observed this pinned behavior on MBE grown (100) GaAs with several surface reconstructions. It should be pointed out that a pinned surface does not necessarily imply that it is not suitable for MIS applica-

109

D. S. L. Mui et al. / I H - V semiconductor M I S devices

tions because on insulator deposition the insulatorsemiconductor interface may be unpinned. A very good example is the well known SiO2-Si interface. Grant and Waldrop [26] demonstrated experimentally that the surface Fermi energy of pinned GaAs (100) surface can be varied over a wide range of energies by depositing either a thin layer of germanium or silicon onto GaAs. Sambell and Wood [27] argued theoretically, based on electrostatic considerations alone, that heavily doped pseudomorphic silicon cap layers deposited onto GaAs can indeed unpin the surface. The most recent investigations involving III-V MIS structures entail a silicon interlayer between the insulator and the semiconductor [5, 24, 28-32]. In addition to unpinning the surface Fermi energy, it was observed that the silicon interlayer helps to reduce the density of tunneling-related traps [17]. The above results suggest that the GaAs and In0.53Gao.a7As (100) surfaces can be suitable for MIS applications. However, the fact that the Fermi level is pinned at some ICS interfa,ces indicates that defects are created after growth of the I I I - V semiconductors. In addition, submonolayer adsorption of oxygen on an unpinned GaAs (110) surface has been shown [33] to pin the surface Fermi energy. It is therefore concluded that oxygen reacts with GaAs, creating a very high density of surface defects. By contrast, air exposed In0.53Ga0.a7As surfaces do not display strong Fermi level pinning, implying that this material may be more pliable for use in insulator/semiconductors for devices. Since a high density of surface defects exists in airexposed samples, these surfaces are generally not suitable for the formation of ICS interfaces. To alleviate the deleterious effects of oxidized surfaces, removal of surface native oxides by a hydrogen plasma has been employed [3, 34, 35]. Similar approaches using an NH3 plasma have also been demonstrated as effective in improving the physical and electrical properties of the interface [36]. An interesting experiment was performed by Licoppe et al. [37] where cleaning action of Sill 4 on an oxidized InP surface was observed. Another approach [3, 7] used wet chemical etching followed by immediate loading of the sample into the insulator deposition chamber in an attempt to form an ICS interface free of native oxides. However, surface oxidation still occurred during loading owing to rapid surface reaction. The best approach to solve the problems related to the presence of native oxides and contaminants at ICS interfaces is not to let the as-grown III-V surface leave the vacuum system before deposition of the insulator. In situ deposition has attracted considerable attention in recent years [5, 29, 34, 38, 39]. This technique has demonstrated the formation of very high quality interfaces which resulted in stable MISFETs with high transconductances [5, 38, 39].

SiGe MBE

~S

111.

Gas Source III-V MBE

"

UHV ECRCVD

Fig. 1. Layout of a complete growth system designed to perform in situ insulator deposition. In this example, the I I I - V semiconductors are grown by MBE and the insulator by electron cyclotron resonance plasma-assisted ultrahigh vacuum chemical vapor deposition.

3. Growth apparatus for in situ insulator deposition The importance of in situ insulator deposition in eliminating surface contamination of the as-grown I I I V semiconductor surface was discussed in Section 2. The layout of a typical system designed for in situ insulator deposition is shown in Fig. 1. In this particular example, several III-V MBE growth chambers and an ultrahigh vacuum chemical vapor deposition chamber for insulator deposition are connected together by ultrahigh vacuum transfer tubes. Sample transfer between any of the chambers takes place under ultrahigh vacuum conditions making it ideal for MIS investigations. Besides avoiding surface contamination, the system is also very suitable for experimenting with insulators deposited onto surfaces of various reconstructions which is difficult if not impossible to perform ex situ.

4. Interface characterization methods In this section, several commonly used interface characterization methods based on capacitance and conductance measurements are discussed. At the outset, we should point out that these methods were originally developed for the SiOz-Si interface. Owing to the different behavior of ICS interfaces compared with SiO2-Si, analyses with these characterization methods on ICS interfaces are more difficult. In addition, the properties of the semiconductor used also affect the validity of these methods. This section also discusses a few of the misconceptions associated with these "well established" SiO2-Si interface characterization techniques when applied to ICS interfaces. It has been shown [40] that conventional circuit models for analyzing insulator-semiconductor interfaces are not applicable when tunneling-related traps occur at the interface.

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D. S. L. M u i et al. / I I I - V s e m i c o m h t c t o r

Instead a new circuit model appropriate for this brand of traps must be used as will be addressed below, following a brief discussion of the conventional methods.

4.1. Conventional methods of &terface characterization Several conventional interface characterization metho d s - - T e r m a n ' s , quasi-static capacitance-voltage (CV), and c o n d u c t a n c e - - a r e discussed in this paper. These methods when applied to the SiO2-Si interface have been shown to yield good quantitative agreement on the interface trap density [41]. Of these methods, all except the quasi-static CV method use a small a.c. signal superimposed on a d.c. bias. The a.c. signal is used to empty and fill traps which are located within a few k~T of the Fermi energy, where kB is the Boltzmann constant and T is the absolute temperature. Because of the time taken in the emission and capture processes, this entails a capacitive effect induced by the traps. Accompanying this capacitive effect is a loss due to a difference in energy between the traps and the equilibrium Fermi energy. Both the trap capacitance and the loss are capable of providing information regarding the interface trap density. Since the capacitance and loss are caused by interface traps which are located within a few kB T of the Fermi energy, the interface trap density at any energy within the band gap, in principle, can be measured provided that the interface Fermi energy is not pinned. All of the conventional interface characterization methods are based on an equivalent circuit diagram of the insulator-semiconductor (IS) interface. This conventional circuit diagram in depletion is shown in Fig. 2(a). The circuit is composed of the insulator capacitance CN in series with the parallel combination of the

I 1

C N ~

C$

+

Rs

(a)

CN

L

(b) Fig. 2. Conventional circuit diagrams of the insulator-semiconductor interface in (a) depletion and (b) accumulation.

MIS

det,ices

semiconductor capacitance Cs and the trap admittance Yr. The latter is itself a parallel combination of the trap capacitance C~l and the trap conductance Gt. This circuit diagram is derived from Gauss' law assuming that the IS interface under consideration is atomically abrupt. The problem with this assumption is that real interfaces are spatially extended. As a result, tunnelingrelated trapping can dominate the measured response of the interface, especially in accumulation. This necessitates the use of the new circuit diagram appropriate for tunneling-related trapping [40]. However, for device grade interfaces in depletion and weak inversion, tunneling-related trapping is relatively unimportant and the circuit diagram shown in Fig. 2(a) is sufficiently accurate. Therefore, in the following discussion of Terman's, quasi-static CV, and conductance methods, the circuit diagram of Fig. 2(a) is used. It is important to realize that for interfaces which possess a high density of tunneling-related traps, tunneling-related trapping is important at all biases and Fig. 2(a), under this circumstance, cannot be used even in depletion.

4.1. I. Terman's method As the name suggests, this method was originally conceived by Terman [42]. For this method to work, a measured true high frequency CV curve is necessary. The interface trap density is determined by recognizing that interface traps cause a change in slope of measured CV curve (this is known as stretchout), and comparing the measured slope with that of a theoretically calculated ideal CV curve. This method has the advantage of obtaining the interface trap density over a large range of energies. Since only a single trace of CV curve measured at a single frequency is required, rapid characterization of the interface trap density is provided. Although this method can lead to erroneous results when applied to ICS interfaces, it has nevertheless been quite widely used. A true high frequency CV curve is one that is measured at a sufficiently high frequency that no interface trap responds to the a.c. signal. Owing to complications arising from parasitic resistances and inductances at high frequencies, 1 M H z is generally chosen for this task. While parasitic effects are usually negligibly small at this frequency, it is not high enough to eliminate the response of shallow interface traps entirely. Whether interface traps react depends on the trap response time which is a function of both the semiconductor surface potential and the intrinsic carrier concentration. For small band gap materials such as Ino.53Ga0.ayAs and germanium, inherent large intrinsic carrier concentrations result in a significant surface carrier concentration even in depletion. Consequently, the trap response time is sufficiently short that traps can respond to frequencies above 1 MHz [43]. However, whether the response

D. S. L. Mui et al. / H I - V semiconductor M I S devices

of the traps can be measured depends on the semiconductor capacitance. For example, in accumulation the trap response is screened by the extremely large C~. The semiconductor capacitance effectively short-circuits the trap admittance and the corresponding simplified circuit, Fig. 2(b), results. However, in bias regimes where C~ is not sufficiently large, the response of the traps contributes to the measured admittance. In this case, the trap capacitance compensates for the stretchout effect by increasing the slope of the measured CV curve. Under these circumstances, Terman's method yields an interface trap density which is lower than the actual value. If the amount of traps which responds to the a.c. signal is high enough, it is possible for the slope of the experimental CV curve to be larger than that of the ideal curve. This would then result in a fictitious negative interface trap density. Another possible source of error in applying Terman's method may result from the dynamic change in slope of a CV curve occurring during measurement. This may happen for interfaces which display a large CV hysteresis. Such large hysteresis can be caused by the presence of either bulk traps in the insulator or tunneling-related traps. These traps have very long response times and they capture or emit carriers as the d.c. bias is changed. As a result, the slope of the CV curve is not only a function of the d.c. bias but also its sweep rate. This again introduces errors in extraction of the interface trap density.

4.1.2. Quasi-static CV method In contrast to Terman's method in which a high frequency CV curve is measured, the quasi-static (QS) CV method produces the capacitance voltage characteristics at very low frequencies. In contrast to the high frequency limit where traps do not respond, all of the traps present can respond in the QS case. For convenience in practice, a slowly changing ramp voltage is used instead of a low frequency a.c. signal. In this case, the ramp voltage causes a displacement current to flow whose magnitude is proportional to the ramp rate, and the differential quasi-static capacitance Cos is measured. Mathematically, it is expressed as dQ C ° s - dVg

dQ dt id dt d ~ - ~

(1)

where ~ is the ramp rate, id is the displacement current, and Q is the charge. From Fig. l(a), CQs is given by 1

1 - -

CQs -- Cs + C~,

1 +

CN

(2)

The interface trap capacitance Cit is related to the density of interface traps Dit simply by Dit = C'it/q. By rearranging eqn. (2), the interface trap density can be expressed as

=

S

I 11

-

c~

(3)

A theoretical ideal low frequency CV curve is generally used to find Cs. Using the quasi-static CV curve, the total change in the semiconductor surface potential A~b~as the gate bias Vg is swept from accumulation to inversion [44] can be measured:

v'i c

N //

where Vgnv and Vgcc are the gate voltages causing inversion and accumulation respectively. It is to be noted that q A4~s is the change in Fermi energy at the interface when Vg is swept from accumulation to inversion. It has been observed that for some ICS interfaces, q AqSs is much smaller than the band gap of the semiconductor owing to the presence of a high density of interface traps which "block" the movement of the Fermi level at the interface. However, for an interface with low trap density across the entire band gap of the semiconductor, A~b~should be close to or even larger than the semiconductor band gap. For the QS method to be reliable, it is imperative that the insulator has very low leakage current to assure that the displacement current, which contains information about the interface traps, is not overwhelmed by the leakage current. Owing to the smallness of the displacement current, to minimize the error introduced by the leakage current, the resistivity of the insulator is generally required to be no smaller than 1016~'~cm. This stringent condition is not always satisfied by deposited insulators which may explain why many authors do not use the QSCV technique for characterizing MIS devices with deposited insulators.

4.1.3. Conductance method The methods discussed above are based on measuring capacitances and extracting the interface trap density from them. An alternative approach for characterizing interface traps is the conductance method [45], which relies on measurement of the conductance instead of the capacitance. The experimental set-up for this method is identical with that of the high frequency CV method, i.e. a small a.c. signal is superimposed on a d.c. bias. However, in obtaining D,, the d.c. bias is held constant while the frequency of the a.c. signal is varied. At sufficiently large frequencies, no trap responds to the a.c. signal and there is no loss due to the interface traps. Traps can however be in thermodynamic equilibrium with the low frequency a.c. signal, and again no loss in the system is measured. However, at intermediate frequencies, interface traps respond to the a.c. signal and

I 12

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Mui et al. / I11- V semiconductor M I S devices

a loss peak is developed. The height and width of the loss peak are related to the interface trap density, and the frequencyfp at which the loss is maximum is related to the trap response time. By fitting the measured loss vs. frequency curve with the statistical model [45], the interface trap density can be obtained. The problem with whether a true high frequency signal is obtainable is not an issue in the conductance method because frequency dispersion of the traps is already factored into the equations.

4.2. A new circuit model for interface characterization The conventional methods of interface characterization discussed above are all based on an atomically abrupt IS interface. With this kind of interface, traps are assumed to be present at the IS interface and tunneling of carriers into these traps does not occur. However, interfaces obtained in the laboratory are not atomically abrupt. Therefore, spatial extension, usually of tens of gmgstr6ms, accompanies the interface. Despite the small thickness of the interface, the frequency response of the interface traps is dramatically altered in a spatially extended interface [40]. This is caused by trapping of carriers which tunnel into the interface. The physics of the capture of tunneling electrons by interface traps has been described by Heiman and Warfield [46]. In this model, the electrically active interface is assumed to extend from the crystallographic IS interface into the insulator, and interface traps are assumed to exist in this spatially extended interface. The capture process is depicted in Fig. 3 using the energy band

--~16

t~

Tunneling

Ec EF

I I I I I I I I I I

Metal

f

Ei

f-

av

diagram of an MIS capacitor biased into accumulation. The conductive and capacitive frequency dispersion for tunneling-related trapping has been shown to be given by the following expressions [40]: 6

qognt f z ln[1 + (o9" exp(2k0z)) 2] Gt ~

-

2o)'6 j

tk

dz

(5)

and 6

C t = --_qn 6 t J~z tan-I(o * ~ , ~xp~eXp(2k°z)) dz

(6)

o

where n t is the density of tunneling-related traps, z is normal to the interface, o9*--ogz with ~ the response time of the traps, ko is the electron tunnel wavevector, and 6 is the thickness of the interface. The measured admittance I'm of the MIS capacitor in accumulation is obtained as Ym = jogC,,, = G't + jog(CN + C't)

(7)

where G't = (6/tk)Gt and C't = (6/tk)Ct with tk the insulator thickness. The above derivation thus leads to a reduced trap admittance in parallel with the insulator capacitance and the appropriate circuit diagram is shown in Fig. 4. The new circuit model has been used to explain the observed frequency dispersion of various interfaces, for example Si3N4/InP [47], Si3N4/Si/GaAs, Si3N4/epi-Si/Si, and SiO2/epi-Si/Si [40], in accumulation. By matching the calculated capacitive and equivalent series resistive frequency dispersion to measured data, the density of tunneling-related traps and the effective thickness of the interface can be deduced. By using this circuit model it has been shown that in cases where a pseudomorphic silicon interlayer is used in an ICS interface, the tunneling-related trap density is reduced by an order of magnitude compared with interfaces without the silicon interlayer [17]. We should caution the reader that this method is strictly accurate

I CN

l

+

Y't=G't+jmC't

Metallurgical Interface C$

F

exp(2koz)

o

~ I

Fig. 3. The energy band diagram of an MIS capacitor biased in accumulation. The capture of tunneling electrons by interface traps occurs directly and is not preceded by an SRH process.

_

Fig. 4. New circuit model which describes the capture of tunneling electrons by interface traps. The interface trap admittance is decoupied from the large semiconductor capacitance shown by the dashed line.

D. S. L. Mui et al. / 111- V semiconductor M I S devices

only in strong accumulation. When a large density of interface traps exists near the conduction band and Fermi level is pinned, strong accumulation may not be obtainable. For samples with a low density of tunneling-related traps, for example those used in ref. 40, it can be shown that tunneling-related trapping is not important in bias regimes other than accumulation [48]. However, it is observed that for samples with a high density of tunneling-related traps, the conductance vs. frequency curves do not follow the statistical model. In that case, tunneling is important for all biases.

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5. Characteristics of various ICS interfaces 1.0

In this section, the characteristics of various interfaces--insulator/Ino.53 Gao.47As, insulator/Si/Ino.53Gao.47As, insulator/InP, and insulator/Si/GaAs--are discussed. The indium containing materials are observed to possess ICS interfaces of much higher quality than GaAs. Ino.53Gao.47As ICS interfaces have been reported [5] to have characteristics similar to those of SiO2-Si.

0.8

t~

0.6

i 0.4

~

1MI-Iz

0.2

5. I. Insulator / Ino.53 Gao. 47,4s interface

Realization of metal-insulator-semiconductor fieldeffect transistors requires a high quality ICS interface, i.e. the density of both fast and tunneling-related traps should be as low as possible. Since InGaAs is grown on InP substrates, lattice matching becomes very important, unless coherently strained, since the lattice mismatch also induces defects at the interface. This is especially important when the interface trap density is low. The low and high frequency CV curves of the in situ Si3N4-Ino.53Gao.aTAS [48] and ex situ SiO2Ino.53Gao.47As [7] interfaces are shown in Figs. 5(a) and 5(b) respectively. (Similar characteristics of the ex situ SiO2-Ino.53Gao.47As interface were observed in ref. 6.) A very small frequency dispersion, as shown in Fig. 5(b) between the 1 kHz and 1 MHz CV curves for an SiO2-InGaAs interface implies that the density of fast interface traps with response times shorter than 1 ms is small. However, the density of slow interface traps with response times longer than 1 ms is quite large, as evidenced by the large change between 1 kHz and 100 Hz CV, namely a 600 meV hysteresis and a small dip in the 100 Hz CV. The Si3Na-Ino.53Gao.47As interface exhibits some capacitive frequency dispersion. It has been shown that this kind of frequency dispersion is caused by tunneling-related trapping [ 17]. The lack of native oxides at the ICS interface of the in situ sample shows that the observed frequency dispersion is not related to native oxides but to trapping of tunneling electrons into traps which are located in the spatially extended inter-

(b) 0.0

a

-8

[

t

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~

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t

l

0

i

I

I

I

i

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4

Gate Bias, V

Fig. 5. Low and high frequency CV curves of (a) in situ Si3N 4 Ino.53Gao.47As and (b) ex situ SiO2-Ino.53Gao.47As interfaces. After

ref. 6. face [40, 46]. These traps manifest themselves as drain current drift instabilities in MISFETs; it is therefore important to reduce their densities. As will be shown, this can be achieved effectively by the use of a pseudomorphic silicon interlayer deposited between the insulator and Ino.53Gao.a7As. Because the small band gap of In0.53Gao.47As (Eg= 0.75) allows minority carriers to respond to the 1 kHz signal, the low frequency CV curve of Fig. 5(a) resembles a QSCV curve (however, it should be noted that significant discrepancies exist between the I kHz and the real QSCV curve). The interface is characterized by a large stretchout and a small dip in the low frequency CV curve. Both of these features indicate a relatively high density of traps present at the interface. To quantify the density of fast traps, the conductance method could be used. The loss of the interface is measured as a function of frequency, and the results at several biases of the in situ Si3Na-In0.53Gao.nvAs interface are shown in Fig. 6 with Si3N4 as the insulator [48]. However, the data do not follow any of the single time constant, distributed, or statistical fluctuation

114

D.S.L.

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Mui et a l . / I I I - V semiconductor M I S devices

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107

Frequency (Hz) Fig. 6. Loss vs. frequency curves of the Si3N4-lno.53Gao.47As mterface at various biases.

models. Instead, the loss vs. frequency curves suggest a significant contribution of the loss, arising from tunneling-related trapping, which is indicated by the almost fiat frequency response at the low frequency side of the loss peak. Furthermore, the effect of tunneling-related trapping is more significant when the MIS capacitor is biased closer to accumulation. This effect is observed in Fig. 6 for the Vg = -0.15 V curve; the marked deviation from the statistical model is a clear indication of the tunneling-related trapping effect. This behavior has also been reported in the GaAs anodic-MOS interface [49]. For measuring the density of tunneling-related traps, the method discussed in ref. 41 can be used. Shown in Fig. 7 are results associated with the capacitive and equivalent resistive frequency dispersions for an MIS capacitor biased in accumulation. The density of tunneling-related traps is found to be 6 × 1012 eV -t cm -2 for the interface shown in Fig. 5(a). The high density of traps is the cause of the rapid decrease in the measured capacitance as the frequency increases.

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Fig. 7. Measured capacitance ((3) and equivalent series resistance (&~) as a function of frequency in accumulation of a typical S[3N4/ Ino.53Gao47As MIS capacitor.

The apparent large stretchout of the insulatorIno.53Gao.n7As interface displayed in Fig. 5 could be interpreted, within the framework of Terman's method, as due to the presence of a relatively high density of fast interface traps. However, as discussed above, Terman's method in the presence of a high density of tunnelingrelated traps cannot be used reliably. The slow response of the tunneling-related traps allows interaction with the bias voltage dynamically, causing misinterpretation of the slope of the CV curve. It has been shown that this sort of CV stretchout is related to the density of tunneling-related traps [48]. It has also been demonstrated using an Si3Na-In0.53Gao.a7As interface that slow interface traps interact with fast traps in a complicated manner [50].

5.2. Insulator/Si/lno.53 Gao.47As interface Comparing the insulator-Ino.53Gao.47As results with those of the Si3Na-(epi-Si) [51] and SiO2-Si interfaces, the frequency dispersion of the latter set of interfaces is negligibly small and the dip in the QSCV curve is much larger. Therefore, it is interesting to investigate the effects of a pseudomorphic silicon interlayer deposited between the insulator and Ino.53Gao.aTAs on the interface characteristics. The use of a pseudomorphic silicon interlayer for passivating I I I - V semiconductors has been demonstrated by several groups [5, 17, 28-30, 52]. In the experiment discussed in ref. 17, the thickness of the silicon interlayer is changed from 0 to 4 monolayers in three different samples. The measured CV curves for the samples with 1 to 2 and 3 to 4 monolayers of silicon are shown in Figs. 8(a) and 8(b) respectively. It is obvious that CV frequency dispersion is reduced as the silicon interlayer thickness increases. This suggests that the silicon interlayer reduces the density of fast interface states which have response times shorter than 0.01 s. Capacitive and resistive frequency dispersions of these two samples are shown in Figs. 9(a) and 9(b) respectively. From these figures, the tunneling-related trap density was deduced to be 2 × 10 ~2eV -~ cm -2 and 5 × 10 II e V - l c m - 2 f o r samples with 1 to 2 and 3 to 4 monolayers of silicon respectively. A reduction in the density of tunneling-related traps can be interpreted as resulting from better bond matching between Si3N4 and silicon compared with that between Si3N 4 and In0.53Ga0.47As [24]. It has been shown that significant diffusion of the constituent atoms of Ino.53Gao.47As into the insulator occurs when the Ino.53Gao.47As MIS samples are annealed [53, 54]. This outdiffusion causes a reduction in the concentration of constituent atoms of Ino.53Gao.avAs at the interface, resulting in a change in stoichiometry of Ino.53Gao.+TAs. In relation to this finding, it has been demonstrated that the density of interface traps can be lowered by reducing the deposition temperature [17]. It

D. S. L. Mui et al. / I I I - V semiconductor M I S devices 160

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Fig. 8. Measured I kHz and l M H z C V curvcs of a typical Si3N4/Si/ Ino.53Gao47As M I S capacitor. The thickness of the silicon intcrlayer is (a) 1 to 2 and (b) 3 to 4 monolayers.

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is highly probable that outdiffusion of the constituent atoms of In0.53Gao.47As at elevated temperatures resuited in the formation of interface traps. Therefore, it is important to deposit the insulator at low temperatures. U p o n reduction of the deposition temperature, we have observed an improvement in the interface quality. The QSCV and H F C V curves of the low temperature deposited in situ Si3Na/Si/Ino.s3Gao.47As interface are shown in Fig. 10. The large dip in the QSCV curve is characteristic of an interface with very low interface trap density. This behavior is similar to that o f the SiO2-Si interface. The QS integral A~bos, defined in eqn. (4), gives the change in the semiconductor surface potential as the gate bias is swept between accumulation and inversion. For the QSCV curve shown in Fig. 10, A~bQS is 0.64 V, indicating that almost the entire band gap (Eg = 0.75) of Ino 53Ga0.a7As can be accessed. Owing to the smallness of the band gap of Ino53Gao.a7As, the minority carrier response is fast enough to allow the 100 Hz CV curve to behave somewhat like the QS curve. However, significant discrepancies exist between the two curves as is evident in Fig. 10. The results obtained from the conductance method are shown in Fig. 11. The loss peaks in depletion were observed to follow the statistical fluctua-

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tion model, indicating that tunneling-related trapping is insignificant. By evaluating the surface potential from a calculated ideal HFCV curve, the density of fast interface traps as a function of energy was obtained and is shown in Fig. 12. The minimum interface trap density was on the order of 2 x 10 I1 eV -I cm -2 [55].

1 16

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The above results were obtained on in situ deposited samples with a silicon interlayer. Although there are no published results on ex situ insulator/Si/Ino.53Gao.47As structures, it is worthwhile comparing in situ Si3N4/Si / In0.53Gao.47As results with ex situ deposited SiO2/ Ino.53Ga0.47As [6, 7] and Si3Na/Ino.53Gao.47As [56] interfaces. In these reports, the Ino.53Gao.47As surface of the samples was chemically treated to remove the native oxides on Ino.53Gao.47As before the insulator deposition. However, the formation of native oxides was unavoidable since the chemically treated surface was again exposed to air before it was loaded into the deposition chamber. As discussed above, both the small dip in the QSCV curve and the small "quasi-static" integral of refs. 6 and 7 (estimated to be 0.4 eV) indi-

cate the presence of a significant density of interface traps. The minimum interface trap density reported in ref. 6 using Berglund's method is 7 × 10 ~ eV -I cm -2 The trap density at the low-temperature ex situ deposited Si3N4-Ino.53Gao.47As interface is on the order of 10 t2 e V - I c m -2 [55]. Taking the results of ref. 6 as representative of all low-temperature ex situ deposited insulator-Ino.53Gao.47As interfaces, the improved findings reported in refs. 5 and 55 can be attributed to one of two things: (i) passivation effects of the silicon interlayer and (ii) in situ deposition. The role of the silicon interlayer is still somewhat controversial. According to the disorder-induced gap state model [24], the silicon interlayer serves better to bond-match the insulator to the underlying I I I - V semiconductor. In the case of Ino.53Ga0.4vAs, silicon derived intrinsic gap states do not exist and, therefore, the purpose of the silicon interlayer in reducing interface traps is fulfilled. It has been demonstrated [48] that the silicon interlayer reduces not only the density of slow interface traps but also the density of fast interface traps, as evidenced by the very small frequency dispersion and large QS integral. Besides reducing the interface trap density directly, the silicon interlayer serves to block oxygen from reaching the Ino.53Gao.47As surface during deposition of oxygen based insulators, for example, SIO2. However, depending on the thickness of the silicon interlayer and the deposition conditions of SiO2, complete elimination of the penetration of oxygen through the silicon interlayer may not be possible [57]. From XPS measurements, it was clearly shown that selective oxidation of gallium in Ino.53Gao.47As during deposition of SiO2 is greatly suppressed by the silicon interlayer. However, it was observed that there is slight broadening of the Ga 2p peak, indicating that slight oxidation of gallium takes place [52]. Besides oxygen containing insulators, there has been a considerable amount of work on using S i 3 N 4 a s the insulator on Ino.53Gao.47As MIS structures [5, 17, 39, 55, 58, 59]. 5.3. I n s u l a t o r - I n P interface

The insulator-InP interface exhibits a minimum trap density above the mid-gap. The interface trap density was found to be about 10~2eV -~ cm -2 in the energy range between about 0.2 V and 0.5 eV below the conduction band and decreased considerably toward the conduction band above about 0.2 eV [60]. The interface trap density increases very rapidly below about 0.6 eV from the conduction band edge. This distribution of interface traps with the band gap has resulted in the general ease for ex situ deposited n-type samples in achieving accumulation and depletion. For the same reason, strong inversion can only be observed in p-type samples. Transport measurements have been performed

D. S. L. Mui et al. / I I I - V semiconductor M I S deL'ices

on inversion-mode M I S F E T structures grown on ptype substrates [61]. The energy distribution of the interface traps can be affected significantly by surface treatment before insulator deposition [62]. By etching InP in hydrazine before deposition, the density of acceptor centers, which pin the Fermi energy around 0.5 eV below the conduction band minimum CBM, can be reduced sufficiently to prevent Fermi level pinning. The movement of the surface Fermi energy of a clean (110) InP surface with respect to the amount of oxygen exposure has been measured by XPS [33]. The surface Fermi energy was found to displace from its original position which is close to CBM, to 0.5 eV below CBM suggesting the formation of interface traps. Similar to the case of Ino.53Gao.47As in which in situ deposition is critical in achieving high quality interfaces, recent efforts on InP MIS research have also stressed the use of in situ processing. It has been demonstrated that Sill4 reduces the oxidized surface of InP [37]. Oxygen originally bonded to InP becomes bonded to silicon in silica-like bonds. This process has been used as an in situ surface cleaning step for InP MIS structures [63]. This has resulted in a strong decrease in the CV hysteresis, demonstrating an improvement in interface properties. In another attempt to reduce slow interface traps, phosphorus was added during insulator deposition [16]. It was assumed that the evaporation of phosphorus during insulator deposition was the cause of the trap states. A significant amount of phosphorus was found in the insulator even at a deposition temperature as low as 200 °C. The presence of native oxides at insulator-InP interfaces has been shown to be detrimental to the properties of the interface. This has prompted the use of nitrides as the gate insulator [13-15]. In the work of Jeong et al. [13], a photo-assisted CVD process was used for the deposition of phosphorus nitride (P3Ns). The source gas is a mixture of PC13 and N H 3. The phosphorus trichloride used in the reaction is also thought to provide a phosphorus-rich environment to subdue outdiffusion of phosphorus from the substrate. The optical absorption edge of P3N5 is around 5.2 eV and the static dielectric constant is 5.9. In situ surface pretreatment was performed by running PCI 3 on a heated substrate. This removes the native oxide which is supposed to be responsible for most of the interface instabilities and long-term drift effects. Injection type CV hysteresis of 45 mV was observed on a 1000 ,/k film. As determined from Terman's method, after a 300 °C 5 min hydrogen anneal, the interface trap density was reported to have dropped from the unannealed value of approximately 1012 eV -i cm --~ to 3.6 × 10 ~° eV -~ cm -2 In a related work [14], a nitrogen-phosphorus polymer p , Ny CI_- was deposited by plasma-enhanced CVD onto InP. With part of the activation energy provided

117

by the plasma, the deposition temperature was 250 °C. The source gas is again a mixture of PC13 and NH3. It is necessary to anneal the film to obtain good insulating properties. The best results were obtained after a 30 min 300 °C anneal in a reducing environment. The resistivity of the annealed film is higher than 10 ~3D cm and the breakdown field is 5 x 1 0 6 V c m - 1 . It was concluded in ref. 14 that the P N - I n P interface did not show significant improvement or significant degradation compared with other works on nitrides, oxides, or sulfides. The total reported interface density is about 5 x 1 0 l l c m - 2 , and the interface trap density per unit energy is in the 10 ~ eV -~ cm -2 range. Boron nitride has also been used as the gate insulator on InP [15]. The material was deposited by plasmaenhanced CVD using borane-dimethylamine and ammonia at a substrate temperature of 320 °C. The InP substrate onto which the insulator was deposited was in situ etched in HC1 similar to the process used in refs. 14 and 15. The optical band gap of the insulator was estimated to be 5.8-5.9 eV, the resistivity is of the order o f 1 0 t3 ~ cm, and the relative dielectric constant is 3.5. The interface quality was characterized by fabricating an Au/BN/InP MIS diode. The CV characteristics exhibit a bias-dependent clockwise hysteresis. For a 5 V peak-to-peak bias swing, the hysteresis was of the order of 1 V. In accumulation, tunneling-related frequency dispersion was observed. Between 100 Hz and 1 MHz, the change in capacitance did not exceed 10%. The CV curves measured at various frequencies are shown in Fig. 13. Tunneling-related trapping is clearly displayed in accumulation. Despite the presence of a significant amount of tunneling-related trapping, the density of interface traps was measured by Terman's method [15] and varied from 2 to 6 x 10 ~' eV -~ cm -2.

500

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300

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100

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-2

0

2

4

Gate bias, V

Fig. 13. CV characteristics measured from I00 Hz to l MHz of the BN-InP interface. Reprinted from ref. 13.

118

D. S. L. M u i et al. / I H ~ V s e m i c o m h w t o r M I S devices

180

5.4. The insulator/Si/GaAs interface

Similar to InP, the existence of surface Fermi level pinning in oxygen exposed GaAs MIS devices is well known [60]. However, unlike InP in which the surface Fermi level is pinned around the conduction band, the surface Fermi level of GaAs tends to be pinned around mid-gap. This behavior prevents the surface Fermi level from approaching either the conduction or valence band edge. There has been a considerable amount of work done on unpinning the GaAs surface Fermi level. These efforts include the use of light-induced photochemistry between GaAs and water [64], hydrogen plasma surface cleaning and nitrogen plasma passivation [3, 34, 36, 63, 65]. However, the method which has received the most attention in recent years is again the use of a silicon [26, 29, 30, 32, 66-69] and germanium [26, 70] interlayer deposited between the insulator and GaAs. It is commonly agreed that when a clean GaAs surface is exposed to oxygen the surface Fermi level is pinned. However, the detailed nature of the pinning effect is still under intense debate. The purpose of the hydrogen plasma in the aforementioned investigations is to remove surface native oxides and other contaminants converted to volatile gas. The effectiveness of hydrogen plasma in recovering an oxide-free surface from an oxidized surface is well documented [3, 35, 65]. XPS measurements on hydrogen plasma cleaned surfaces have shown that the deoxidization of the surface is complete together with the removal of carbon impurities, although arsenic is expected to react preferentially with hydrogen to form AsH 3 which then desorbs from surface. However, under optimized conditions, it has been demonstrated that the stoichiometry of the GaAs surface is preserved after hydrogen plasma treatment [65]. Although a clean ordered GaAs (100) surface is pinned [25, 26], from XPS and spectroscopic ellipsometry investigations unpinning of the surface Fermi level which accompanies a lowering of the surface electric field on p-type samples was observed during a H 2 plasma treatment. However, on n-type samples, the results suggest that the surface is pinned at a new level after exposure of a GaAs (100) surface to H 2 plasma [65]. Clark and Anderson [3] reported a dramatic reduction in CV frequency dispersion of an MIS device after hydrogen plasma cleaning. There is also evidence of surface Fermi level unpinning by depositing a pseudomorphic silicon or germanium layer onto GaAs. For example, Grant and Waldrop [26] have shown that such a cap layer can bring about a large range of surface Fermi energy, the surface electric field is greatly reduced, and the barrier heights of A1/Si/GaAs Schottky diodes can be varied over a wide range of energy [66]. This unpinning of the GaAs surface Fermi level is supported by theoretical

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Fig. 14. QSCV and HFCV curves measured at 1 MHz, 100 kHz, and

100 Hz of the Si3N4/Si/GaAs interface.

calculations based on electrostatics [27]. Yet there is conflicting evidence suggesting that the apparent enhancements made possible by the silicon interlayer arise not from a large reduction in interface trap density, but rather from a shift in trap energy toward the conduction band edge [31]. It is suggested in ref. 71 that epitaxial bonding at the S i - G a A s interface alone is not sufficient to eliminate Fermi level pinning, and other mechanisms affect the interfacial charge balance. Much effort has been expended on GaAs MIS devices using a silicon interlayer. These investigations invole both in situ [29, 32, 69, 72], and ex situ [28, 30, 31, 68], deposited samples. Despite the methods of deposition, CV frequency dispersion in depletion is observed, indicating that although the interface is unpinned there still exists a high density of interface traps. The CV characteristics of the in situ Si3NJSi/GaAs and ex situ S i 0 2 / S i / G a A s interfaces are shown in Figs. 14 and 15 respectively. Similar to the insulator/Si/Ino.53Ga0.47As interface, the interface trap density is the combined insulator-Si and S i - G a A s interfaces. This CV frequency dispersion has been shown to be due to the presence of a high density of traps which follow the single time constant behavior [29]. This behavior is similar to that observed at the insulator-GaAs interface [73]. It is to be noted that the samples used in ref. 29 were deposited in situ with a silicon interlayer, while those of ref. 36 were ex situ deposited and without a silicon interlayer. In situ samples showed a much reduced frequency dispersion in depletion coupled with elimination of the capacitance plateau besetting the ex situ samples.

D. S. L. Mui et al. / 111- V semiconductor M I S devices

1 19

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The presence of the capacitance plateau is indicative of Fermi level pinning. The capacitance plateau was also avoided in refs. 30 and 31 in which silicon was deposited e x situ. However, CV frequency dispersion in depletion was seen to be lower in the in situ case. For comparing the interface properties between different samples, the QSCV method is particularly useful, since a high density of discrete traps is present which potentially blocks the Fermi energy from sweeping across the entire band gap for a reasonable range of applied bias. For the in situ samples, A~b is on the order of 0.9 V, while for the e x situ samples it is between 0.6 and 0.9 V. Although A~b is comparable in both cases, the dip in the QSCV curve at the onset of inversion is much more pronounced in the in situ samples. This indicates that the minimum interface trap density is much lower in these samples. From conductance measurements, it was found that the minimum interface trap density is around 10 lj eV -I cm -2 [29]. Although the minimum interface trap density is measured to be very low in in situ samples, it was observed that the interface state density increases rapidly towards the conduction band [29]. This is further evidenced by the reappearance of a capacitance plateau in the low temperature CV curve in ref. 31, indicating that the Fermi level pinning position has shifted from the lower half of the band gap to the upper half of the b a n d gap. Therefore, how close the interface Fermi level can be brought to the vicinity of the conduction band is an important parameter for gaging the interface quality. Attainment of accumulation at 80 K and 100kHz implies that the interface Fermi level is brought within 70 meV of the conduction band [30]. However, a significant flat band voltage shift is still present between the 77 K and 300 K CV curves.

Fig. 16. Quasi-static, 1 MHz, and 100 Hz CV characteristics of the annealed Si3N4/Si/n-GaAscapacitor in the dark at room temperature.

Recently, a significant improvement has been obtained in the electrical characteristics of an Si3N4/Si/ n-GaAs capacitor with the assistance of atomic hydrogen during growth of pseudomorphic silicon on GaAs as shown in Fig. 16 [74]. The Si3N4/Si/n-GaAs capacitors investigated have shown an overall reduction in interface state density to as low as 3 x 101° eV -] cm -2. With reduction of the interface state density to the level characteristic heretofore of the SiO2/Si system, the interface Fermi level is easily modulated by the applied bias as demonstrated in Fig. 17 and CV characteristics begin to approach a level where the hysteresis and the frequency dispersion are very small, being 200 meV and

35

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Fig. 17. Loss vs. frequency curve of Si3N4/Si/n-GaAs capacitor at different biases.

D. S, L1 Mui et al. / II1- V semiconductor M I S devices

120

160

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Si3N4/Si/n-GaAs

100meV respectively. Also, the flat band shift with temperature is much reduced, a 0.74 V positive shift in the 77 K 1 M H z CV curve relative to the 3 0 0 K CV curve as shown in Fig. 18. The reduced voltage shift reflects a significant reduction of the interface state density near the conduction band. These results represent notable advances over past achievements and pave the way for the development of GaAs MIS technology.

6.

III-V

MISFETs

While great attempts have been made to achieve M I S F E T s in GaAs, the most successful efforts have been limited to Ino.53Gao.47As and InP. The problems related to the high density of interface traps even in in situ samples still limit the performance of G a A s MISFETs. Therefore, only the performance of Ino.53Gao.47As and InP M I S F E T s will be discussed. For Ino.53Gao.47As, there are several M I S F E T results which are based on in situ deposited samples. In contrast, we are not aware of such work on in situ samples in InP. Therefore, only a brief review of e x situ InP M I S F E T s will be provided.

4500 cm: V -t s -l was obtained [75]. This demonstrates the potential of Ino.53Gao.aTAs M I S F E T s in high-speed operations. The main concern with most I I I - V based M I S F E T s is the drain current drift phenomenon. This short- and long-term current drift effect has been studied in detail [40, 50, 60, 76-78]. It has been shown that the cause of the drift lies in the exchange of carriers between insulator traps, which reside in the bulk and/or very close to the interface, and the conduction band. Various methods have been employed to alleviate this drift problem [5, 17, 39, 52, 79]. The work by Liao et al. [59] represents one of the early attempts to deposit a heteromorphic gate insulator, Si3N4, onto Ino.53Gao.47As. The n-channel inversion device displayed a transconductance of 2 mS m m -t. This early work demonstrated the possibility of realizing Ino.53Gao.47As M I S F E T s using heteromorphic gate insulators. This paved the way to improved devices made possible by better surface preparation and low-temperature insulator deposition. For a review of Ino.53Gao.aTAS M I S F E T s fabricated before 1988, the interested reader is referred to ref. 80. All of the work discussed in ref. 80 utilized e x situ deposition. The M I S F E T work after 1988 can be grouped into two categories: one with SiO2 as the gate insulator and the other with S i 3 N 4 a s the gate insulator. For the case when SiO, is deposited directly onto Ino.53Gao.47As [81], the output characteristics of an I n G a A s pseudoenhancement-mode M I S F E T are shown in Fig. 19. At zero gate bias, the channel already exists and with the application of positive gate voltages the channel conductivity is enhanced. The transconductance obtained from Fig. 19 is as high as 300 mS m m -]. Similar values of transconductance were also obtained by Gardner et al. [18] for a 1 lam device, Cheng et al. [4] for a 0.5 lam

50 I 40

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The success of Ino.53Gao.47As M I S F E T s lies in the fact that the insulator-Ino.53Gao.47As interface, if properly prepared, is plagued by a low interface trap density. Interface transport measurements have been made through Ino.53Gao.aTAS/plasma oxide inversion layers and a low-field electron mobility as high as

o 3

4

5

Drain Bias ( V ) Fig. 19. Output characteristics of a GalnAs enhancement-mode SiO2/Ino.53Gao.47As MISFET. The gate bias steps for this pseudoenhancement mode device start from 0, the curve on the bottom, and go up to 0.8 V. After ref. 81.

D. S. L. Mui et a L / II1- V semiconductor M I S devk'es

device, and Schfibert et al. [82] with a transconductance of 330 mS m m - ' for a 1.2 lain device. The electron saturation velocity for MISFETs discussed in ref. 81, providing the channel is at the interface, can be estimated from the transconductance using v~ = W-~CoxJgm, where W is the width of the channel, Cox is the oxide capacitance, and gm is the transconductance. Using this expression and other known parameters, the electron saturation velocity and mobility in Ino.53Gao.47As are estimated to be 3 . 5 x 107cms -I and 5800 cm 2 V -~ s -a respectively. This value for the carrier velocity is comparable with 4 x 107cms -j of ref. 18, and is consistent with the calculated value of 4 × 107 cm s -t in ref. 83 in a 1.5 I-tm gate length device. The formula for vs is only true when the device is in strong accumulation and the channel is very close to the interface. In this sense, the capacitance in the v~ expression can be replaced by Cox. Otherwise the capacitance is a serial combination of Cox and the semiconductor capacitance. The fact that the experimental values are close to the calculated values implies that the device operates in strong accumulation and the interface Fermi level approaches the conduction band. In ref. 82, the channel is 220 A away from the interface and taking this into consideration, the electron saturation velocity is estimated to be 6.6 × 107 cm s -~. This relatively high value is attributed to the channel being in the bulk where the velocity is expected to be larger than at the interface. By the same argument the relatively lower electron velocity in ref. 81 is a result of the channel being at the interface where the electrons experience more interface scattering. The current gain cutoff frequency was measured to be 6 and 14 G H z for 3 and 1.5 lam devices respectively. The highest cutoff frequency was 32.5 G H z reported by Gardner et al. [18]. In addition to d.c. performance, In0.53Ga0.~7As MISFETs have demonstrated microwave capabilities [11, 18, 19, 81, 84]. In ref. 19, the SiO2/Si structure was again used. MISFETs with SiO2 as gate insulator exhibited moderate drift in the drain current. For example, a 10% drain current drift in 2 8 h of operation in ref. 81, and a 5% drain current drift over 10Ss in ref. 80 were observed. To obtain MISFETs with better stability, in situ deposition is necessary. It has been reported that by removing the In0.53Ga0.47As native oxides in an ultrahigh vacuum chamber, immediately prior to the in situ insulator deposition, stable device operation can be obtained [39]. The native oxides were removed by a hydrogen plasma, and a nitrogen based insulator, Si3N4, was used so as not to re-oxidize the In0.53Ga0.47As surface which would otherwise occur in the case of an oxygen based insulator. The drain current was observed to drift by less than 3% after 30 h of continuous operation. The transconductance of 2 I.tm

80

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250

.

.

.

.

.

.

.

.

.

.

.

.

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150

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Fig. 20. (a) Current-voltage characteristics of a 2.2 lain gate length, 145 pm gate width, self-aligned Si3N4/Si/Ino.53Ga0.avAs depletionmode transistor, and (b) plot of extrinsic transconductance vs. gate bias of the same device.

depletion-mode devices was 1 4 0 m S m m -~. However, the ICS interface characteristics were not discussed in ref. 39. With Si3N 4 as gate insulator, the highest transconductance was obtained with in situ deposited Si3N4/Si/Ino53Ga0.47As depletion-mode M I S F E T [5]. The device characteristics are shown in Fig. 20. The transconductance of nominal 2 tam gate length depletion-mode devices was measured to be in excess of 200 mS mm -~ [5]. The devices exhibited a current drift of about 1% after 10 h of operation. 6.2. InP M I S F E T s

In the case of InP, the interface properties allow n-channel depletion and inversion devices to be achieved. Indium phosphide is another one of the few compound semiconductors which possesses a conducive ICS interface for the realization of MISFETs. The insulator-InP interface is such that the equilibrium interface Fermi energy is located in the upper half of the band gap, allowing the realization of n-channel inversion [61], enhancement [85, 86], and depletionmode MISFETs [87]. Electron transport measurements have been performed on inversion-mode InP MISFETs [61]. S h u b n i k o v - d e Haas oscillations in the gate in-

122

D. S. L. Mui et al. / II1 - V semicomhwtor M I S devices

duced two-dimensional electron gas have been observed along with a surface electron density as high as 7 x 10 ~2 cm -2. Because of the high electron peak and saturation velocities, high thermal conductivity, and low ionization coefficient, most work on InP MISFETs has concentrated on their microwave performance. A power density of 1.8 W mm-J at a frequency as high as 30 G H z [8] was demonstrated recently. Even a higher power of 4 . 5 W m m -~ has been demonstrated at Xband frequencies [88].

7. Conclusions Recent results obtained for m e t a l - i n s u l a t o r - s e m i conductor structures with in situ deposited dielectric layers based on selected c o m p o u n d semiconductors were addressed. For a comparative analysis characteristics of various In0.53Ga0.47As, InP, and GaAs MIS capacitors and FETs where the insulator is deposited using h7 situ and ex situ means were presented. Conventional methods and a new circuit model for interface characterization were also discussed. Despite miraculous advances, I I I - V MIS structures are still in their infancy and only recently have structures with interface state densities in the same range as those routinely available in silicon technology become possible in a laboratory setting. Interface trap densities as low as mid 10~°eV-~cm --~ can now be achieved in c o m p o u n d semiconductors by in situ deposition. In cases in which a silicon interlayer is used for reduction of tunnelingrelated traps, stable MISFETs with high transconductance can be obtained.

Acknowledgments This work was supported by A F O S R under the direction o f Program monitor Dr. Jerry Witt. H. Morkoq and Z. Wang acknowledge support by the D O E and the use of Epicenter facilities. The authors would like to thank Professor G. B. Gao, J. Reed, Z. Fan, and B. Mazhari for helpful discussions and assistance.

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