A single-chip digital signal processor for telecommunication applications

A single-chip digital signal processor for telecommunication applications

World Abstracts on Microelectronics and Reliability 195 6. MICROELECTRONICS--COMPONENTS, SYSTEMS AND EQUIPMENTS the design concept, architecture, in...

126KB Sizes 2 Downloads 154 Views

World Abstracts on Microelectronics and Reliability

195

6. MICROELECTRONICS--COMPONENTS, SYSTEMS AND EQUIPMENTS the design concept, architecture, instructions, device design, and application techniques.

A single-chip digital signal processor for telecommunication applications. TAKAO NISHITANI, RIKIO MARUTA, YUICHI KAWAKAMI and HIDETO GOTO. IEEE d. Solid-St. Circuits SC-16 (4), 372 (1981). A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 ~tm n-channel E/D MOS technology, incorporates a 16 x 16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The paper describes

7. S E M I C O N D U C T O R

INTEGRATED

A simple method for modeling VLSI yields. C. H. STAPPER and R. J. RO~NER.Solid-St. Electron. 25 (6), 487 (1982). Data show that simplistic models of yield as a function of chip area are not realistic. Yield of ROS (_ReadOnly _Store) chips as a function of the number of bits results, however, in a smooth relationship. This observation appeared to hold for three manufacturing lines. The authors therefore propose that yields should be modeled by the number of circuits rather than by chip area.

CIRCUITS, DEVICES AND MATERIALS

Calculation of the electric field enhancement for a degenerate diffusion process. ALANH. MARSHAKand RITU SHRIVASTAVA. Solid-St. Electron. 25 (2), 151 (1982). The internal electric field produced by a constant source impurity diffusion is calculated using Fermi-Dirac statistics for the majority carrier. Numerical results indicate that treating the material as if it were nondegenerate always produces an underestimate in the electric field. The field enhancement factor which gives the ratio of the effective diffusion coefficient to the impurity diffusion coefficient valid for a degenerate diffusion process is clarified. Characteristics of metal/tunnel-oxide/n/p + silicon switching devices--lI. Two-dimensional effects in oxide-isolated structures. L. FARAONE,J. G. SIMMONDS,F. L. HSUEH and U. K. MISHRA. Solid-St. Electron. 25 (5), 335 (1982). Effects of oxide isolation on the two-terminal D.C. characteristics of metal/tunnel-oxide/nip + silicon switching devices have been studied. Recent experimental results have shown that the switching characteristics are strongly dependent on area, and area-toperimeter ratio of the device [1]. To carry out a systematic investigation of this phenomenon, the devices in this study were isolated using V-grooves of various areas. For a given tunnel-oxide thickness and area, it was found that the magnitude of the switching voltage and holding current of the device increased with isolation area, whereas the switching current remained essentially constant. Furthermore, it is shown that the switching current is almost completely determined by the characteristics of the tunnel-oxide; in particular, the minority carrier concentration at the SiSiO 2 interface. Physical arguments are presented which adequately explain the observed trends. It is also experimentally shown that both switching current and holding current decrease as the tunnel-oxide thickness is increased. A simple two-dimensional model for the oxide-isolated MISS device is derived which effectively explains the above area-related phenomena. In agreement with experimental results, the model predicts that for a given tunnel-oxide thickness and area, an increase in switching voltage magnitude and holding current will result as the isolated p+-n junction area is increased. Calculations based on this model are shown to be in good agreement with experimental data. Minority carrier injection and extraction in neutron bombarded germanium. G. RIEDER,J. C. MANIFACIERand H. K. HENISCH. Solid-St. Electron. 25 (2), 133 (1982). Experiments with minority carrier injection and extraction have been carried out on n-type germanium before and after neutron bombardment. The results show that bombardment followed by annealing introduces levels which respond to injected holes traps. The space charge on these traps is responsible (over a certain range of current densities) for a substantial (factor of -~ 7) increase of local resistance, as

distinct from the decrease conventionally expected. The increase is in harmony with theoretical predictions established in previous papers. Electrical characteristics and memory behavior of GE3N4GaAs MIS devices. KRISHNAP. PANDE.Solid-St. Electron. 25 (2), 145 (1982). MIS devices have been fabricated by the low temperature chemical vapor deposition of GeaN 4 on n-GaAs. From the current-voltage data an estimate of the GeaN 4 dielectric constant is made as 6.3 _+0.2 and devices exhibit a breakdown field strength of ~ 5 x 106V/cm. Capacitance and conductance measurements have been performed to investigate the electrical characteristics of the GeaN4-GaAs interface. The interface properties of the devices are found to depend on the Ge3N4 deposition parameters. No major hysteresis is observed in the C-V plot and under large negative gate bias, the capacitance increases as the measurement frequency is lowered. Interface state distribution, evaluated from the conductance data, is found to have a minimum density of states of 2 × 1011 cm-2eV -1 with a distinct shoulder between 0.4 and 0.55 eV from the conduction band. This shoulder is assigned to an electron trap level and from thermally stimulated current measurements we obtained the density of traps as 3 x 1017 cm- 3. GaAs-MNOS devices have also been fabricated and their charge storage properties have been studied. Pulse voltages as large as 30-35 V are needed to write/erase the memory in the devices. Effect of the presence of an inversion layer in an MPN structure. S. B. RoY and A. N. DAW. Solid-St. Electron. 25 (2), 169 (1982). Theoretical analysis of electric field and potential profile in an MPN structure has been made taking inversion into consideration. Modified expressions for increase in barrier height, ideality factor and capacitance have been derived. Results calculated from our theory are compared with those obtained by earlier workers ignoring the effect of inversion layer and with the experimental data available in literature. Thermally induced defect behaviour and effective intrinsic gettering sink in silicon wafers. FUMIO Sm~tURA, HIDEKI TSUYA and TSUTOMU KAWAMURA.J. Electrochem. Soc. 128 (7), 1579 (1981). Dislocation-free Czochralski silicon wafers have been subjected to a two-step annealing procedure to explore the intrinsic gettering (IG) phenomenon and the behavior of thermally induced microdefects using infrared absorption, preferential etching, and transmission electron microscopy (TEM). As a result, it is found that plastic lattice deformation introduced by dislocation and/or stacking faults is necessary for effective IG sinks. In spite of their extremely high density, microprecipitates with elastic strain but no plastic deformation do not result in effective IG. TEM observations clarify the change in density and/or structure of