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A systolic signal processor for signal-processing applications
Microprocessors An easily testable optimal-tlme VLSl-multlpller B BECKER (Univ. des Saariandes, Saarbrucken, Germany) Acta Inf. (Germany)vol. 24, no. 4, pp. 363-380 (1987) Considers the design of a 'tree-multiplier', which is a modified version of a Wallace tree-multiplier [1964] made suitable for VLSI-design by Luk and Vuillemin [1983]. It is shown that 4 log(n) q- 3 test patterns suffice to exhaustively test the multiplier with respect to the 'cellular fault model' (which includes tests for all single stuck-at faults). Some slight modifications of the multiplier prove that these tests can be applied without increasing the number of input ports substantially. (17 refs.)
The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into sub-problems that fit the array size. A technique for obtaining the partitioning and the transformation of matrix problems is presented. It is designed to minimise execution times for big problems in small arrays and to introduce very little additional complexity into the system. The technique is used to solve matrixby-vector multiplication and triangular system equation problems by means of a one-dimensional systolic array processor. It is also used to solve matrix-by-matrix multiplication, triangular matrix equations, LU decomposition and other problems by means of a two-dimensional array. Some comments are made regarding pipelined processing elements. (15 refs.)
Wave front array processors - concept to implementation S Y KUNG, S C LO, S N JEAN, J H H W A N G (Univ. of Southern California, Los Angeles, CA, USA) Computer (USA) vol. 20, no. 7, pp. 18-33 (July 1987) Four parallel-processing array architectures - SIMD, MIMD, systolic and wavefront - a r e desribed and compared. The derivation of wavefront arrays by combining systolic array and data-flow concepts is explained. Algorithm mapping and programming for wavefront arrays is discussed. The system architecture is examined. The benefits of wavefront architectures and some examples of wavefront array systems are described. (19 refs.)
The design of a GaAs systolic array for an adaptive null steering beamforming controller C E HEIN, R M Z I E G E R , J A UBARNO (RCA Adv. Technol Labs., Moorestown, N J, USA) Computer (USA)vol. 20, no. 7, pp. 92-93 (July 1987) The approach taken in the design of the array is briefly sketched. The selection of an algorithm that could adaptively generate the complex beamforming coefficient vector is discussed. The choice of architecture is considered. The advantages of using gallium arsenide are examined. (3 refs.)
SLAPP: a systolic linear algebra parallel processor B L D R A K E (US Naval Ocean Syst. Center, San Diego, CA, USA), F T LUK, J M SPEISER, J J SYMANSKI Computer (USA) vol. 20, no. 7, pp. 45-49 (July 1987) A description is given of work currently underway to build a two-dimensional systolic array, SLAPP, demonstrating efficient and modular parallelisation of key matrix computations for real-time signal and image processing problems. The discussion covers matrix-based signal processing, parallel matrix computation, noniterative matrix operations, iterative matrix operations, the triangular singular value decomposition algorithm, and the QRD algorithm. (21 refs.)
A systolic signal processor for signal-processing applications D A KANDLE (ESL Inc., Sunn)wale, CA, USA) Computer(USA) vol. 20, no. 7, pp. 94-95 (July 1987) A description is given of a systolic adaptive beamformer intended to demonstrate the applicability of systolic processing techniques to acoustic signal processing. The processor was built to perform narrow-band, passive, sonar signal processing. From a computing-architecture point of view the beamforming process can be broken down into three linear algebra problems. A custom VLS1 chip that is a systolic cell has been developed for this application. (4 refs.)
Some systolic array developments in the United Kingdom J V McCANNY (Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, N Ireland), J G McWHIRTER Computer(USA) vol. 20, no. 7, pp. 51-63 (July 1987) Two major UK systolic array projects are described. The first concerns the development of a wave front array processor for adaptive beamforming, the second concerns the design of bit-level systolic arrays for high-performance signal processing. (15 refs.)
Integrated Circuit Technology
Partitioning: an essential step in mapping algorithms into systolic array processors J J N A V A R R O , J M LLABERIA, M VALERO (Fac. de Info. de Barcelona, Univ. Politecnlca de Cataluna, Spain) Computer (USA) vol. 20, no. 7, pp. 77-89 (July 1987)
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Explicit formulation of delays in CMOS VLSI D A U V E R G N E , D DESCHACtlT, M R O B E R T (Univ. des Sci. et Technol. du Languedoc, Montpellier, France) Electron. Lett. (GB) vol. 23, no. 14, pp. 741-742 (2 July 1987) An explicit formulation for the transient response of CMOS inverters is given, including load conditions and driving waveforms. Validation of the initial hypothesis is obtained through SPICE simulations. The results obtained show clear evidence of the influence of structural and parasitic parameters on propagation times, allowing fast optimisation.on the data path. (3 refs.)
The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into sub-problems that fit the array size. A technique for obtaining the partitioning and the transformation of matrix problems is presented. It is designed to minimise execution times for big problems in small arrays and to introduce very little additional complexity into the system. The technique is used to solve matrixby-vector multiplication and triangular system equation problems by means of a one-dimensional systolic array processor. It is also used to solve matrix-by-matrix multiplication, triangular matrix equations, LU decomposition and other problems by means of a two-dimensional array. Some comments are made regarding pipelined processing elements. (15 refs.)
Wave front array processors - concept to implementation S Y KUNG, S C LO, S N JEAN, J H H W A N G (Univ. of Southern California, Los Angeles, CA, USA) Computer (USA) vol. 20, no. 7, pp. 18-33 (July 1987) Four parallel-processing array architectures - SIMD, MIMD, systolic and wavefront - a r e desribed and compared. The derivation of wavefront arrays by combining systolic array and data-flow concepts is explained. Algorithm mapping and programming for wavefront arrays is discussed. The system architecture is examined. The benefits of wavefront architectures and some examples of wavefront array systems are described. (19 refs.)
The design of a GaAs systolic array for an adaptive null steering beamforming controller C E HEIN, R M Z I E G E R , J A UBARNO (RCA Adv. Technol Labs., Moorestown, N J, USA) Computer (USA)vol. 20, no. 7, pp. 92-93 (July 1987) The approach taken in the design of the array is briefly sketched. The selection of an algorithm that could adaptively generate the complex beamforming coefficient vector is discussed. The choice of architecture is considered. The advantages of using gallium arsenide are examined. (3 refs.)
SLAPP: a systolic linear algebra parallel processor B L D R A K E (US Naval Ocean Syst. Center, San Diego, CA, USA), F T LUK, J M SPEISER, J J SYMANSKI Computer (USA) vol. 20, no. 7, pp. 45-49 (July 1987) A description is given of work currently underway to build a two-dimensional systolic array, SLAPP, demonstrating efficient and modular parallelisation of key matrix computations for real-time signal and image processing problems. The discussion covers matrix-based signal processing, parallel matrix computation, noniterative matrix operations, iterative matrix operations, the triangular singular value decomposition algorithm, and the QRD algorithm. (21 refs.)
A systolic signal processor for signal-processing applications D A KANDLE (ESL Inc., Sunn)wale, CA, USA) Computer(USA) vol. 20, no. 7, pp. 94-95 (July 1987) A description is given of a systolic adaptive beamformer intended to demonstrate the applicability of systolic processing techniques to acoustic signal processing. The processor was built to perform narrow-band, passive, sonar signal processing. From a computing-architecture point of view the beamforming process can be broken down into three linear algebra problems. A custom VLS1 chip that is a systolic cell has been developed for this application. (4 refs.)
Some systolic array developments in the United Kingdom J V McCANNY (Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, N Ireland), J G McWHIRTER Computer(USA) vol. 20, no. 7, pp. 51-63 (July 1987) Two major UK systolic array projects are described. The first concerns the development of a wave front array processor for adaptive beamforming, the second concerns the design of bit-level systolic arrays for high-performance signal processing. (15 refs.)
Integrated Circuit Technology
Partitioning: an essential step in mapping algorithms into systolic array processors J J N A V A R R O , J M LLABERIA, M VALERO (Fac. de Info. de Barcelona, Univ. Politecnlca de Cataluna, Spain) Computer (USA) vol. 20, no. 7, pp. 77-89 (July 1987)
52
Explicit formulation of delays in CMOS VLSI D A U V E R G N E , D DESCHACtlT, M R O B E R T (Univ. des Sci. et Technol. du Languedoc, Montpellier, France) Electron. Lett. (GB) vol. 23, no. 14, pp. 741-742 (2 July 1987) An explicit formulation for the transient response of CMOS inverters is given, including load conditions and driving waveforms. Validation of the initial hypothesis is obtained through SPICE simulations. The results obtained show clear evidence of the influence of structural and parasitic parameters on propagation times, allowing fast optimisation.on the data path. (3 refs.)