- Email: [email protected]
A study on the poly-Si TFT and novel pixel structure for low flicker
Microelectronics Journal Microelectronics Journal 31 (2000) 641±646
www.elsevier.com/locate/mejo
A study on the poly-Si TFT and novel pixel structure for low ¯icker Kyoung Moon Lim*, Ho Cheol Kang, Man Young Sung Semiconductor & CAD Laboratory, Department of Electrical Engineering, Korea University, 1, 5-ka Anam-Dong, Sungbuk-ku, Seoul 136-701, South Korea Accepted 23 March 2000
Abstract We propose a new pixel structure based on complementary 2-TFTs switching structure. This structure is capable of reduction of DC level shift by Cgs coupling and improvement of defect tolerance, so making large, high image quality TFT-LCD panel fabrication both easy and economical. The compensating characteristics for reducing DC level shift in complementary 2-TFTs switching architecture were investigated using a TFT equivalent model. However, the number of gate lines and TFTs doubles as compared with a fundamental structure without redundancy. To minimize this problem (reduction of aperture ratio), a new pixel structure called a complementary 2-TFTs structure, which has one contact hole, was proposed. This technology has a low hardware overhead and is very capable of redundancy for open circuit defects in a TFT-LCD panel. q 2000 Elsevier Science Ltd. All rights reserved. Keywords: Poly-Si TFT; Pixel; DC level shift; Redundancy
1. Introduction The demand for high resolution AMLCDs resulted in a considerable increase in efforts to develop poly-Si TFTs which use polycrystalline silicon ®lm as a channel. PolySi TFT technologies have been progressed by integrating peripheral driver circuits on the same substrate of TFTLCDs because it has high carrier mobility and CMOS self-alignment structure [1,2]. Recently, high-resolution TFT-LCDs with more than one million pixels and largesize TFT-LCDs have been developed, and drive methods and pixel structure for high-resolution TFT-LCDs have been proposed [3,4]. The electrode-optical characteristics of LCDs depend not only on the design parameters of the pixels, but also the driving voltages and addressing pulse duration of the pixels. When the gate pulse goes to the off state, the pixel voltage, Vp, is shifted by DVp, which is a gate-to-pixel feedthrough voltage (DC level shift voltage, kick-back voltage) caused by the gate-to-source parasitic capacitance, Cgs, of TFT. The DC level shift varies with data because the LC cell capacitance changes with data. Differences in DC level shifts among data cause residual DC components in the LC cell voltage, even with an AC drive scheme. This leads to image sticking and ¯icker. Thus, reducing DC level shift is one of * Corresponding author. Tel.: 1 82-2-3290-3782; fax: 1 82-2-9211325. E-mail address: [email protected] (K.M. Lim).
the most important problems for a high resolution and a good image quality. We propose a new TFT matrix architecture and driving scheme, featuring a compensating TFT in addition to the conventional addressing TFT (nTFT and pTFT, respectively, in Fig. 1). DC level shift is cancelled by switching a compensating TFT. This technology drastically reduces dot and line defects, enabling fabrication of large, high image quality poly-Si TFT-LCD panels at a relatively low cost. 2. Pixel structure and drive wave form The ¯aw in TFT active-matrix driving is the decrease in fabrication yield caused by the complicated fabrication process. To solve this problem, several defect tolerant methods that drive one pixel by several TFTs have been proposed. The shared duplication redundancy method are collected and compared in Table 1. Structure 1 in Table 1 was the fundamental method. Redundancy structure 2 was conceived by paying attention to the fact that major defects in the fabrication process were crossover shorts between gate lines and data lines. The TFTs with crossover short defects detected in the inspection stage are removed by laser cutting either of the bus lines. The basic concept of this construction is that each pixel receives two different signals successively through two TFTs in one frame period during normal operation. If a defective TFT is found, it is eliminated by laser trimming and the pixel is driven by only the remaining TFT.
0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved. PII: S 0026-269 2(00)00046-X
642
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
Fig. 1. Con®guration of poly-Si TFT panel and applied waveforms.
Therefore, a remarkable feature of this redundancy method is that automatic defect tolerance is not feasible but only TFT duplication is necessary and no additional gate or data lines are needs. Redundancy structure 3 is a proposed method that consists of an active matrix circuit with two input routes. TFTs and gate lines are duplicated for each pixel provided. If
one gate line in the ®gure of structure 2 in Table 1 has an open defect and/or one TFT has an defect, then normal data will be input to the pixel through the other TFT. Moreover, this defect-tolerant technology provides automatic defect tolerant capability and so defect inspection and laser maintenance are not necessary. However, as shown in Table 1, the number of gate lines and TFTs doubles as compared with a fundamental structure without redundancy. To minimize this problem (reduction of aperture ratio), a new redundancy method called a complementary 2-TFTs structure, which has one contact hole, was proposed. Fig. 1 shows the circuit diagram and drive waveforms of the proposed TFT matrix. The pixel consists of two gate lines, a data-line, a common electrode, two switching TFTs (nTFT and pTFT), a storage capacitor, and a liquid crystal capacitor. The gate of a pixel TFT is connected to the adjacent vertical scanning line, the source to the adjacent data line, and the drain to both the storage capacitor and the pixel electrode which drives the liquid crystal, respectively. The video signal is written from the data line to the pixel electrode through the TFT when the scanning line is selected. To compensate for DC level shift by the capacitive coupling voltage, DVp, an extra TFT, complementary TFT, is added to each pixel. Vck, Vst, Vgi and Vgib represent external clock, starting pulse and addressing scan pulses, respectively. nTFT and pTFT are n-channel TFT (LDD, off-set or dual gate type) and p-channel TFT (LDD, off-set or dual gate type), respectively. Fig. 2 is the top view of the new pixel structure (layout). This structure can minimize the aperture ratio reduction by the proposed `one contact hole± two TFT' structure. Increasing the number of cell dots decreases the fabrication yield of TFT-LCD panels, creating a signi®cant problem. To overcome this, a new duplication redundancy technology called a complementary 2-TFTs structure, which has defect tolerant capability, was proposed.
Table 1 Comparison of duplication redundancy structure 1 (fundamental)
2
3
1 1 Very high No No No
2 (same type) 1 High Yes Yes No
2 (different type) 2 Low Yes Yes Yes
Structure
No. of TFTs per pixel No. of gate lines per pixel Aperture ratio Redundancy for TFT Redundancy for gate lines Compensation of DC level shift
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
643
Fig. 2. The proposed pixel structure.
3. TFT fabrication and model Fig. 3 shows the cross-section of the TFT developed in this work according to the production process. 5 inch quartz wafers were used as the substrate material. A base oxide layer is deposited on a quartz wafer, and then an a-Si Ê , 4858C) is deposited on it. layer (LPCVD, Si2H6, 1200 A The a-Si layer is crystallized by furnace annealing (6008C, 24 hr). After crystallization, the device islands are patterned and etched using a standard lithography process. Then an Ê oxide layer is grown by thermal oxidation to form a 850 A gate oxide layer. Next, a gate electrode is formed with WSix/ poly-Si. Following the gate de®nition lithography, the gate is etched. Self-aligned source/drain regions are formed by ion-implantation of phosphorus/boron dopants. The source and drain are self-aligned to form because of the ion doping form over the gate electrode. Then the ®rst interlayer is deposited by CVD and contact
holes are made on the gate, source and drain. Al is deposited Ê to conduct wiring on the source, drain and circuit. A 7000 A sputtered Al±2%Si metal was used as the source/drain electrode material. SiNx:H is deposited as the second interlayer and pixel electrode (ITO) is formed. Further, the passivation layer is formed and openings are made in it. Then the blackmatrix (BM) is deposited as a light shield and patterned. We simulate their transfer and output characteristics at different voltages using SPICE with our TFT model. In this model, We adopted an ªequivalent componentº approach which treated the poly-Si TFT with large off-current, low subthreshold slope and kink effect as a c-Si MOSFET with parasitic components (diode, resistor, capacitor and MOSFET with different characteristics). Fig. 3 shows the I±V characteristics of the model and experimental data with a cross-section of the TFT. We have already designed a panel with fundamental pixel structure using this model and displayed the TFT-LCDs [4,5].
644
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
Fig. 3. Cross-section of the TFTs and I±V characteristics.
4. Reduction of DC level shift by Cgs coupling The DC level shift varies with data because the LC cell capacitance changes with data (Fig. 4). Differences in DC level shifts among data cause residual DC components in the LC cell voltage, even with an AC drive scheme. This leads to image sticking and ¯icker. The complementary 2TFTs structure has advantages over the conventional one in eliminating the DC level shift differences among data. The DC level shift, DVp, is expressed as DVp Cgs Von ±Voff = Clc 1 Cgs 1 Cstg ; where Clc, Cgs and Cstg represent LC capacitance, the gate-source capacitance of
TFT, and storage capacitance, respectively. In the conventional architecture, Cgs, in addition to Clc, varies with data because it depends upon the effective gate bias, i.e. the relative voltage difference between gate-source at the end of the addressing. DVp shows a complicated dependence on data because of the combination of Clc and Cgs. This makes it dif®cult to cancel the DC level shift differences among data. However, in our architecture, the DC level shift is minimized by additional DVp 0 2DVp : During the one-rowpixels selection time, all pixels along a row are charged up to the applied data voltages through n-channel TFT and pchannel TFT, respectively. For the proposed new pixel
Fig. 4. Capacitive coupling effect on typical dynamic waveforms.
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
645
Fig. 5. Equivalent circuit model and parameters for simulation.
structure, we performed the simulation. We checked the ®nal pixel voltage which was simulated by varying applied data voltage Vd. Simulation was performed for the equivalent one row circuit model (Fig. 5), the 1st pixel with minimum RC line delay (worst case of DC level shift) and the last pixel with maximum RC line delay. The simulated pixel voltage shift is shown in Fig. 6. Fig. 6 shows the level shift
of the pixel voltages by the capacitive coupling to the gate voltage drop. The pixel voltages were compared with the conventional structure which has only one-switching-TFT for switch. DVp is minimized in the new complementary 2TFT structure. The capacitive coupling voltage, DVp, of the new structure is lower than that of the conventional oneswitching-TFT type pixel. The smaller value of the capacitive coupling voltage is attributed to the compensated DC level shift by n-channel switching TFT and p-channel switching TFT. The most common defect in an active-matrix LCD is probably open lines or fault TFT circuits. In this matrix design, if there is an open line in one path, the other path ensures that the cells receive the correct data. If there are short circuits in the matrix, the laser cutting method change them to open circuit defects. Thus, almost all defects can be overcome with this complementary 2-TFTs structure. 5. Conclusion
Fig. 6. DC level shift voltage dependence on the data voltage for minimum gate pulse distortion conditions (min. RC line delay: worst case).
We proposed a TFT matrix structure and drive scheme that eliminates the DC level shift differences among data and reduces ¯icker in a complementary 2-TFTs structure. The DC level shift compensating characteristics in a complementary 2-TFTs matrix architecture was investigated considering the voltage-dependent characteristics of the gate capacitance when the TFT goes to the off-state from the on-state. Increasing the number of cell dots decreases the fabrication yield of TFT-LCD panels, creating a signi®cant problem. To overcome this, a new duplication redundancy technology called a complementary 2-TFTs structure, which has defect tolerant capability, was proposed. This redundancy technology with defect tolerant capability is a
646
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
very economical con®guration and very capable of compensating for open circuit defects in a large active matrix panel. In addition, the proposed structure can minimize the aperture ratio reduction by a `one contact hole±two TFTs' structure. Consequently, this structure drastically reduces DC level shift and dot/line defects, enabling fabrication of large, high resolution poly-Si TFT-LCD panels at a relatively low cost.
[2]
[3]
[4]
References [1] S. Higashi, Y. Matsueda, S. Takenaka, M. Miyasaka, I. Yudasaka,
[5]
H. Ohshima, A 1.8-in. poly-Si TFT-LCD for HDTV projectors with a 5-V fully integrated driver, SID '95 Digest, 1995, pp. 81±84. H. Sato, H. Nakamura, Y. Makazono, M. Kobayashi, K. Mori, N. Harada, A 1.9M-Pixel poly-Si TFT-LCD for HD and computer-data projectors, IEEE Trans. On Consumer Electronics, 41(4), November 1995, pp. 1181±1188. M. Itoh, Y. Yamamoto, T. Morita, H Yoneda, Y, Yamane, S. Tsuchimoto, F. Funada, K. Awane, High-resolusion low-temperature poly-Si TFT-LCDs using a novel structure with TFT capacitors, SID '96 Digest, 1996, pp. 17±20. B.D. Choi, S.T. Kim, O.K. Kwon, M.J. Soh, K.M. Lim, High-apertureratio 2.4-in-diagonal poly-Si TFT-LCD panel with high immunity to threshold-voltage variations, SID '97 Digest, 1997, pp. 1069±1072. K.M. Lim, M.Y. Sung, Low noise digital data driver circuit integrated poly-Si TFT-LCD, Microelectronics 30 (1999) 905±910.
www.elsevier.com/locate/mejo
A study on the poly-Si TFT and novel pixel structure for low ¯icker Kyoung Moon Lim*, Ho Cheol Kang, Man Young Sung Semiconductor & CAD Laboratory, Department of Electrical Engineering, Korea University, 1, 5-ka Anam-Dong, Sungbuk-ku, Seoul 136-701, South Korea Accepted 23 March 2000
Abstract We propose a new pixel structure based on complementary 2-TFTs switching structure. This structure is capable of reduction of DC level shift by Cgs coupling and improvement of defect tolerance, so making large, high image quality TFT-LCD panel fabrication both easy and economical. The compensating characteristics for reducing DC level shift in complementary 2-TFTs switching architecture were investigated using a TFT equivalent model. However, the number of gate lines and TFTs doubles as compared with a fundamental structure without redundancy. To minimize this problem (reduction of aperture ratio), a new pixel structure called a complementary 2-TFTs structure, which has one contact hole, was proposed. This technology has a low hardware overhead and is very capable of redundancy for open circuit defects in a TFT-LCD panel. q 2000 Elsevier Science Ltd. All rights reserved. Keywords: Poly-Si TFT; Pixel; DC level shift; Redundancy
1. Introduction The demand for high resolution AMLCDs resulted in a considerable increase in efforts to develop poly-Si TFTs which use polycrystalline silicon ®lm as a channel. PolySi TFT technologies have been progressed by integrating peripheral driver circuits on the same substrate of TFTLCDs because it has high carrier mobility and CMOS self-alignment structure [1,2]. Recently, high-resolution TFT-LCDs with more than one million pixels and largesize TFT-LCDs have been developed, and drive methods and pixel structure for high-resolution TFT-LCDs have been proposed [3,4]. The electrode-optical characteristics of LCDs depend not only on the design parameters of the pixels, but also the driving voltages and addressing pulse duration of the pixels. When the gate pulse goes to the off state, the pixel voltage, Vp, is shifted by DVp, which is a gate-to-pixel feedthrough voltage (DC level shift voltage, kick-back voltage) caused by the gate-to-source parasitic capacitance, Cgs, of TFT. The DC level shift varies with data because the LC cell capacitance changes with data. Differences in DC level shifts among data cause residual DC components in the LC cell voltage, even with an AC drive scheme. This leads to image sticking and ¯icker. Thus, reducing DC level shift is one of * Corresponding author. Tel.: 1 82-2-3290-3782; fax: 1 82-2-9211325. E-mail address: [email protected] (K.M. Lim).
the most important problems for a high resolution and a good image quality. We propose a new TFT matrix architecture and driving scheme, featuring a compensating TFT in addition to the conventional addressing TFT (nTFT and pTFT, respectively, in Fig. 1). DC level shift is cancelled by switching a compensating TFT. This technology drastically reduces dot and line defects, enabling fabrication of large, high image quality poly-Si TFT-LCD panels at a relatively low cost. 2. Pixel structure and drive wave form The ¯aw in TFT active-matrix driving is the decrease in fabrication yield caused by the complicated fabrication process. To solve this problem, several defect tolerant methods that drive one pixel by several TFTs have been proposed. The shared duplication redundancy method are collected and compared in Table 1. Structure 1 in Table 1 was the fundamental method. Redundancy structure 2 was conceived by paying attention to the fact that major defects in the fabrication process were crossover shorts between gate lines and data lines. The TFTs with crossover short defects detected in the inspection stage are removed by laser cutting either of the bus lines. The basic concept of this construction is that each pixel receives two different signals successively through two TFTs in one frame period during normal operation. If a defective TFT is found, it is eliminated by laser trimming and the pixel is driven by only the remaining TFT.
0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved. PII: S 0026-269 2(00)00046-X
642
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
Fig. 1. Con®guration of poly-Si TFT panel and applied waveforms.
Therefore, a remarkable feature of this redundancy method is that automatic defect tolerance is not feasible but only TFT duplication is necessary and no additional gate or data lines are needs. Redundancy structure 3 is a proposed method that consists of an active matrix circuit with two input routes. TFTs and gate lines are duplicated for each pixel provided. If
one gate line in the ®gure of structure 2 in Table 1 has an open defect and/or one TFT has an defect, then normal data will be input to the pixel through the other TFT. Moreover, this defect-tolerant technology provides automatic defect tolerant capability and so defect inspection and laser maintenance are not necessary. However, as shown in Table 1, the number of gate lines and TFTs doubles as compared with a fundamental structure without redundancy. To minimize this problem (reduction of aperture ratio), a new redundancy method called a complementary 2-TFTs structure, which has one contact hole, was proposed. Fig. 1 shows the circuit diagram and drive waveforms of the proposed TFT matrix. The pixel consists of two gate lines, a data-line, a common electrode, two switching TFTs (nTFT and pTFT), a storage capacitor, and a liquid crystal capacitor. The gate of a pixel TFT is connected to the adjacent vertical scanning line, the source to the adjacent data line, and the drain to both the storage capacitor and the pixel electrode which drives the liquid crystal, respectively. The video signal is written from the data line to the pixel electrode through the TFT when the scanning line is selected. To compensate for DC level shift by the capacitive coupling voltage, DVp, an extra TFT, complementary TFT, is added to each pixel. Vck, Vst, Vgi and Vgib represent external clock, starting pulse and addressing scan pulses, respectively. nTFT and pTFT are n-channel TFT (LDD, off-set or dual gate type) and p-channel TFT (LDD, off-set or dual gate type), respectively. Fig. 2 is the top view of the new pixel structure (layout). This structure can minimize the aperture ratio reduction by the proposed `one contact hole± two TFT' structure. Increasing the number of cell dots decreases the fabrication yield of TFT-LCD panels, creating a signi®cant problem. To overcome this, a new duplication redundancy technology called a complementary 2-TFTs structure, which has defect tolerant capability, was proposed.
Table 1 Comparison of duplication redundancy structure 1 (fundamental)
2
3
1 1 Very high No No No
2 (same type) 1 High Yes Yes No
2 (different type) 2 Low Yes Yes Yes
Structure
No. of TFTs per pixel No. of gate lines per pixel Aperture ratio Redundancy for TFT Redundancy for gate lines Compensation of DC level shift
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
643
Fig. 2. The proposed pixel structure.
3. TFT fabrication and model Fig. 3 shows the cross-section of the TFT developed in this work according to the production process. 5 inch quartz wafers were used as the substrate material. A base oxide layer is deposited on a quartz wafer, and then an a-Si Ê , 4858C) is deposited on it. layer (LPCVD, Si2H6, 1200 A The a-Si layer is crystallized by furnace annealing (6008C, 24 hr). After crystallization, the device islands are patterned and etched using a standard lithography process. Then an Ê oxide layer is grown by thermal oxidation to form a 850 A gate oxide layer. Next, a gate electrode is formed with WSix/ poly-Si. Following the gate de®nition lithography, the gate is etched. Self-aligned source/drain regions are formed by ion-implantation of phosphorus/boron dopants. The source and drain are self-aligned to form because of the ion doping form over the gate electrode. Then the ®rst interlayer is deposited by CVD and contact
holes are made on the gate, source and drain. Al is deposited Ê to conduct wiring on the source, drain and circuit. A 7000 A sputtered Al±2%Si metal was used as the source/drain electrode material. SiNx:H is deposited as the second interlayer and pixel electrode (ITO) is formed. Further, the passivation layer is formed and openings are made in it. Then the blackmatrix (BM) is deposited as a light shield and patterned. We simulate their transfer and output characteristics at different voltages using SPICE with our TFT model. In this model, We adopted an ªequivalent componentº approach which treated the poly-Si TFT with large off-current, low subthreshold slope and kink effect as a c-Si MOSFET with parasitic components (diode, resistor, capacitor and MOSFET with different characteristics). Fig. 3 shows the I±V characteristics of the model and experimental data with a cross-section of the TFT. We have already designed a panel with fundamental pixel structure using this model and displayed the TFT-LCDs [4,5].
644
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
Fig. 3. Cross-section of the TFTs and I±V characteristics.
4. Reduction of DC level shift by Cgs coupling The DC level shift varies with data because the LC cell capacitance changes with data (Fig. 4). Differences in DC level shifts among data cause residual DC components in the LC cell voltage, even with an AC drive scheme. This leads to image sticking and ¯icker. The complementary 2TFTs structure has advantages over the conventional one in eliminating the DC level shift differences among data. The DC level shift, DVp, is expressed as DVp Cgs Von ±Voff = Clc 1 Cgs 1 Cstg ; where Clc, Cgs and Cstg represent LC capacitance, the gate-source capacitance of
TFT, and storage capacitance, respectively. In the conventional architecture, Cgs, in addition to Clc, varies with data because it depends upon the effective gate bias, i.e. the relative voltage difference between gate-source at the end of the addressing. DVp shows a complicated dependence on data because of the combination of Clc and Cgs. This makes it dif®cult to cancel the DC level shift differences among data. However, in our architecture, the DC level shift is minimized by additional DVp 0 2DVp : During the one-rowpixels selection time, all pixels along a row are charged up to the applied data voltages through n-channel TFT and pchannel TFT, respectively. For the proposed new pixel
Fig. 4. Capacitive coupling effect on typical dynamic waveforms.
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
645
Fig. 5. Equivalent circuit model and parameters for simulation.
structure, we performed the simulation. We checked the ®nal pixel voltage which was simulated by varying applied data voltage Vd. Simulation was performed for the equivalent one row circuit model (Fig. 5), the 1st pixel with minimum RC line delay (worst case of DC level shift) and the last pixel with maximum RC line delay. The simulated pixel voltage shift is shown in Fig. 6. Fig. 6 shows the level shift
of the pixel voltages by the capacitive coupling to the gate voltage drop. The pixel voltages were compared with the conventional structure which has only one-switching-TFT for switch. DVp is minimized in the new complementary 2TFT structure. The capacitive coupling voltage, DVp, of the new structure is lower than that of the conventional oneswitching-TFT type pixel. The smaller value of the capacitive coupling voltage is attributed to the compensated DC level shift by n-channel switching TFT and p-channel switching TFT. The most common defect in an active-matrix LCD is probably open lines or fault TFT circuits. In this matrix design, if there is an open line in one path, the other path ensures that the cells receive the correct data. If there are short circuits in the matrix, the laser cutting method change them to open circuit defects. Thus, almost all defects can be overcome with this complementary 2-TFTs structure. 5. Conclusion
Fig. 6. DC level shift voltage dependence on the data voltage for minimum gate pulse distortion conditions (min. RC line delay: worst case).
We proposed a TFT matrix structure and drive scheme that eliminates the DC level shift differences among data and reduces ¯icker in a complementary 2-TFTs structure. The DC level shift compensating characteristics in a complementary 2-TFTs matrix architecture was investigated considering the voltage-dependent characteristics of the gate capacitance when the TFT goes to the off-state from the on-state. Increasing the number of cell dots decreases the fabrication yield of TFT-LCD panels, creating a signi®cant problem. To overcome this, a new duplication redundancy technology called a complementary 2-TFTs structure, which has defect tolerant capability, was proposed. This redundancy technology with defect tolerant capability is a
646
K.M. Lim et al. / Microelectronics Journal 31 (2000) 641±646
very economical con®guration and very capable of compensating for open circuit defects in a large active matrix panel. In addition, the proposed structure can minimize the aperture ratio reduction by a `one contact hole±two TFTs' structure. Consequently, this structure drastically reduces DC level shift and dot/line defects, enabling fabrication of large, high resolution poly-Si TFT-LCD panels at a relatively low cost.
[2]
[3]
[4]
References [1] S. Higashi, Y. Matsueda, S. Takenaka, M. Miyasaka, I. Yudasaka,
[5]
H. Ohshima, A 1.8-in. poly-Si TFT-LCD for HDTV projectors with a 5-V fully integrated driver, SID '95 Digest, 1995, pp. 81±84. H. Sato, H. Nakamura, Y. Makazono, M. Kobayashi, K. Mori, N. Harada, A 1.9M-Pixel poly-Si TFT-LCD for HD and computer-data projectors, IEEE Trans. On Consumer Electronics, 41(4), November 1995, pp. 1181±1188. M. Itoh, Y. Yamamoto, T. Morita, H Yoneda, Y, Yamane, S. Tsuchimoto, F. Funada, K. Awane, High-resolusion low-temperature poly-Si TFT-LCDs using a novel structure with TFT capacitors, SID '96 Digest, 1996, pp. 17±20. B.D. Choi, S.T. Kim, O.K. Kwon, M.J. Soh, K.M. Lim, High-apertureratio 2.4-in-diagonal poly-Si TFT-LCD panel with high immunity to threshold-voltage variations, SID '97 Digest, 1997, pp. 1069±1072. K.M. Lim, M.Y. Sung, Low noise digital data driver circuit integrated poly-Si TFT-LCD, Microelectronics 30 (1999) 905±910.