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A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load
Integration, the VLSI Journal xxx (xxxx) xxx
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A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load Pratosh Kumar Pal a, ∗ , R.K. Nagaria b a b
Electronics and Communication Engineering Department, Madan Mohan Malviya University of Technology, Gorakhpur, Gorakhpur, 273010, India Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, 211004, India
A R T I C L E
I N F O
Keywords: Sub-1 V Cascaded current mirror Subthreshold Current reference Voltage reference
A B S T R A C T
A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/◦ C for a temperature range of −20 to 108 ◦ C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2 . The obtained average reference current is 6 nA having a slope of 5.5pA/◦ C.
1. Introduction The current and voltage reference circuits are a must component of any analog and mixed-signal circuits which is used as a constant current or supply voltage independent of process, supply voltage, and temperature (PVT) variations. The developing modern electronics needs low voltage and low power reference circuits with high performance parameters like compact area. These compact devices require very low supply voltage and currents in nano-ampere resulting nano-watt power dissipation. Therefore, the use of resistors and BJTs are avoided in designing a bandgap reference as they have bulky size and higher bandgap voltage i.e. around 1.2 V [1]. Hence, MOSFETs operating in subthreshold region are considered as the replacement for designing current and voltage reference circuits for fulfilling the demands of low voltage and low power applications [2–5]. The design and analysis of subthreshold voltage reference is done after a thorough literature survey of different voltage references to have an overall better performance. In literature, there are different references proposed using BJTs, resistors and MOSFETs in different combinations. The voltage references in Refs. [6–13] use only resistors and in Refs. [14–18] use resistors and BJTs both. These voltage
references require high supply voltage up to 4 V and current in microamperes resulting high power dissipation and larger active area. Therefore, reference circuits without resistors and BJTs are reported in Refs. [19–31] operating in the subthreshold and saturation region. In Ref. [25], body biased resistorless reference is presented to reduce temperature effect. Due to very low supply variation option from 0.6 to 0.7 V, it has high line regulation which is improved by the proposed reference. [21] proposes a voltage reference without BJTs and resistors for compact area and ultralow power dissipation by employing leakage current of subthreshold transistor as PTAT source. In Ref. [22], reference voltage is generated by feeding supply independent current into the active load. Also uses trimming circuit for reducing process effects. The brief reported in Ref. [31] shows improved arrangement of triode-based widlar reference to reduce both circuit complexity and overall current consumption and [23] gives a survey on different methods of current reference generation. The reference [20], proposes a reference current near-zero power dissipation of 3.4 pW with average reference current ◦ of 1.2 pA at V DD = 0.4 V with TC = 469.3 ppm/ C. In Ref. [24], the difference of two PTAT currents for generation of current reference which is supplied to active load circuit for reference voltage generation is pro-
∗ Corresponding author. E-mail addresses: [email protected] (P.K. Pal), [email protected] (R.K. Nagaria). https://doi.org/10.1016/j.vlsi.2019.11.016 Received 14 May 2019; Received in revised form 24 August 2019; Accepted 26 November 2019 Available online XXX 0167-9260/© 2019 Elsevier B.V. All rights reserved.
Please cite this article as: P.K. Pal, R.K. Nagaria, A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load, Integration, the VLSI Journal, https://doi.org/10.1016/j.vlsi.2019.11.016
P.K. Pal, R.K. Nagaria
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ature variations which is supplied to ALC. The ALC consists of cascode connection of Self-cascode MOSFET (SCM) circuits and an NMOS transistor for temperature compensation of the output voltage reference. The SCM circuit is having two NMOS transistors connected in cascode mode which gives a PTAT voltage source. The proposed circuit has all the transistors of the output ALC operating in subthreshold region. The mathematical expression for the current of a subthreshold operating MOS [21] having V DS ≥ 4V T is given by ( ) ( ) VGS − VTH W exp Isub = Io (1) L 𝜂 VT where Io = 𝜇 Cox (𝜂 − 1) VT2 and 𝜇 , Cox , 𝜂 , V T , W/L = K, and V TH are mobility of electrons or holes, gate-oxide capacitance per unit area, subthreshold slope parameter, thermal voltage, aspect ratio of the MOS transistor and threshold voltage respectively. The typical value of 𝜂 is 1.5 [25]. The Wand L are channel width and length of the MOS transistor respectively. The expression of output reference voltage is the sum of three PTAT voltages from SCM circuit and one CTAT from NMOS as in Fig. 1, given as
Fig. 1. Basic operating principle of proposed CCMVRC.
VREF = VDS8 + VDS10 + VDS12 + VGS13
(2)
In expression (2), the starting three voltage terms represent a PTAT voltage and the fourth term represents a CTAT voltage. The sum of these PTAT and CTAT voltages in appropriate proportion give rise to an output reference voltage independent of supply and temperature variations. This is done by providing proper optimization to the transistor sizes representing these PTAT and CTAT voltages which are explained in following sections.
posed. But it uses Standard-V TH (SVT) and High-V TH (HVT) transistors as active load resulting complex fabrication process. The work presented in this brief is a sub-1 V, high PSRR subthreshold voltage reference employing cascaded current mirror based supply and temperature compensation circuit. Hence, this Cascaded Current Mirror based Voltage Reference Circuit (CCMVRC) has high PSRR. A Cascode connection of MOS transistors used as active load circuit for output reference voltage. The operating supply voltage is 0.95 V which ◦ results in output reference voltage of 609 mV with TC of 44.5 ppm/ C. The remaining contents of this brief are presented in following sections: Section 2 presents the basic working concept of proposed CCMVRC with description of the proposed circuit given in Section 3. The Section 4 explains the different design related considerations taken while analyzing the proposed CCMVRC and the simulation results and results explanation is provided in Sections 5. Finally the conclusion of the presented work is included in the Section 6.
3. Proposed voltage reference circuit description The core of the presented CCMVRC is shown in Fig. 2 consists of following circuit blocks: start-up circuit, beta-multiplier based current generator, cascaded current mirror circuit, and cascoded transistors as active load. The start-up circuit is used to avoid the unwanted zero current mode operation of the proposed voltage reference. The current generator circuit utilizes the concept of beta-multiplier to generate a supply independent current followed by cascaded current mirrors to further compensate the temperature effect on the generated supply independent current by CGC. This results in a reference current independent of supply and temperature. This reference current is then fed to active load circuit to give a supply and temperature independent output voltage reference. The body effect is utilized to reduce the effect of temperature on threshold voltages of the ALC transistors. The rest of circuit description is explained in the following subsections in detail.
2. Principle of operation The basic principle of operation of the proposed voltage reference circuit is shown in Fig. 1. Here, a supply independent current is further compensated for temperature independence before going to the ALC. This gives a reference current independent of supply and temper-
Fig. 2. The core schematic of the proposed CCMVRC. 2
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Fig. 3. The core of the proposed current reference.
Fig. 5. Variation of I 7 with respect of temperature for different supply variations.
Fig. 4. Variation of I 7 with respect of V DD for different temperature variations. Fig. 6. Plot of I error , I out and I out1 of node A vs temperature for V DD = 0.95.
3.1. Supply independent current generator circuit The supply independent current generator circuit consists of transistors numbered from M1-M7 as shown in Fig. 3. The transistors M1-M3 is used as a current mirror to have currents in I 1 , I 2 , and I 3 branches. Here, all the transistors of CGC are working in subthreshold region except M7 which is operating in deep-triode region as an active resistor to avoid larger power dissipation instead of using passive resistor. From Fig. 3, it is observed that VGS4 = VGS5 + VDS7 .
From (4), (5) and (6), the I 7 is given as ( ) ( ) K5 ∗ 𝜂 VT ln . I7 = 𝜇n Cox K7 VGS7 − VTH7 K4
(7)
The threshold voltage of MOS transistors with body biasing is given as
(3)
The transistors M4 and M5 are operating in subthreshold region and it have equal threshold voltages as it has zero source to body voltage. Then from (2) and (3), the expression of V DS7 is given as VDS7 = 𝜂 VT ln(
K5 ). K4
(4)
The transistor M7 is operating in strong inversion, deep-triode region as an active resistor and the expression for its resistance with ∗ body biased threshold voltage VTH7 is given as R7 =
1 ∗ ) 𝜇n Cox K7 (VGS7 − VTH7
.
(5)
The output current of the CGC is expressed as the drain current of M7, given by I7 =
VDS7 . R7
(6)
Fig. 7. Plot of I ′ error , I out2 and I REF of node B vs temperature for V DD = 0.95. 3
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Table 1 The channel length and width of different transistors used in the proposed CCMVRC. Transistor
W (𝜇 m) × m∗ /L [𝜇 m]
Transistor
W [𝜇 m] × m∗ /L [𝜇 m]
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13
5 × 5/10 5 × 4/10 5 × 4/10 2 × 4/10 4 × 4/10 0.4 × 1/10 0.4 × 1/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 1/10
M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25
5× 5× 5× 5× 5× 5× 5× 5× 5× 5× 5× 5×
10/10 2/10 2/10 2/10 2/10 11/10 1/10 11/10 1/10 11/10 1/10 2/10
Fig. 8. Plot of I REF with respect to supply voltage for different temperature variations.
Fig. 10. The layout 75 𝜇m × 109 𝜇m.
(√
2ΦF + VSB −
√
) 2ΦF .
the
proposed
CCMVRC
with
dimensions
The expression (11) gives a current independent of supply voltage variation as it has no supply voltage term. This current is fed to the next block of current subtraction based temperature compensation for reference current generation. The plot showing variation of current I 7 with respect to supply and temperature variations is shown in Figs. 4 and 5.
Fig. 9. Plot of I REF with respect to temperature for different supply variations.
VTH = VTH0 + 𝛾
of
(8)
where ΦF , V TH0 , 𝛾 , and V SB are fermi potential, threshold voltage with no body bias, body effect coefficient and source to body voltage of the MOSFET respectively. The threshold voltage expression is further simplified by using body effect approximation [26] represented as VTH ≈ VTH0 + (𝜂 − 1) VSB
(9)
The body biasing voltage of M7 is generated by SCM circuit having transistors M19 and M20 operating in subthreshold region in ALC of Fig. 2. As V TH of M19 and M20 are same, the V bias by (1) is given as Vbias = VDS20 = 𝜂 VT ln
3K19 . K20
(10)
As V bias is directly proportional to V T , it is a PTAT voltage for the condition when K 19 > K 20 . This PTAT voltage reduces the effect of temperature on V TH7 resulting in process variation reduction. From Fig. 3, it is observed that V GS7 = V GS6 and assuming equal V TH0 of M6 and M7, the expression of output current I 7 from (1), (7), (9), and (10) is given as ( [ ( ) )] ( ) 3K19 I6 K5 I7 = 𝜇n Cox K7 (𝜂 VT )2 ln + (𝜂 − 1) ln . (11) ln K 6 I0 K20 K4
Fig. 11. Variation of threshold voltage of body biased transistors with respect to temperature. 4
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3.3. Cascode transistors as active load circuit The core schematic of the proposed voltage reference is shown in Fig. 2. It is having cascoded transistors working in subthreshold region as ALC. The ALC consists of transistors numbered from M15-M25. It has all the transistors operating in subthreshold region. The transistors M15-M18 are the part of current mirror circuit that copies the reference current I REF to the ALC. The load stage is used to compensate the effect of temperature on the output reference voltage, V REF . The selfcascode MOSFET pairs M19-M20, M21-M22, and M23-M24 generate three PTAT voltages as the drain to source voltages of M20, M22 and M24 respectively. The CTAT voltage is generated by the gate to source voltage of M25. Here, the output voltage reference voltage from (2) and (10) is given as Fig. 12. The plot of threshold voltage variation of body biased transistors of CCMVRC with respect to supply voltage.
VREF = Vbias + VDS22 + VDS24 + VGS25 .
From (1) and (9), the gate to source voltage of M25 is given as ( ) IREF VGS25 = VTH0 + (𝜂 − 1) (Vbias + VDS22 ) + 𝜂 VT ln . (17) I0 K25
3.2. Cascaded current mirror based reference current
Similarly, the drain to source voltages V DS22 is given as ) ( 2K21 . VDS22 = (𝜂 − 1) Vbias + 𝜂 VT ln K22
The cascaded current mirror is used to reduce the effect of temperature and supply voltage on the current generated by the CGC. Here, the concept of error current is used to reduce the temperature effect on current by subtracting the error from the current generated by CGC. The cascaded current mirror circuit configuration consists of transistors numbered from M8-M12 is shown in Fig. 3. All the transistors are working in subthreshold region of MOS operations. The transistor pairs M3-M8, M3-M9, M10-M11, M13-M14, and M10-M12 are used as a current mirror to produce scaled currents to their respective branches. The currents I out and I out1 are scaled version currents of PMOS and NMOS current mirrors respectively. By KCL at node A, we have Ierror = Iout1 − Iout .
K14 I . K13 error
(12)
The expression (19) has summation of CTAT and PTAT voltage terms. The first term is a CTAT and the last three terms are a PTAT. Therefore, by varying the aspect ratio terms of different transistors present in these voltage terms, a better TC of output reference voltage is obtained from expression (19). This will give a reference voltage as independent as possible to supply voltage and temperature variations. The variation of I REF with respect to supply and temperature variations is shown in Figs. 8 and 9.
(13)
4. Design considerations
The expression of I REF in terms of current I 7 using different current mirrors is given as IREF
K8 = (K K + K10 K14 − K11 K14 )I7 . K3 K10 K13 12 13
4.1. Transistor biasing
(14)
Transistor biasing is implemented such that all the transistors are working in their respective region of operation to ensure correct output at each stage of the proposed CCMVRC. In any branch of the proposed
Finally, the expression of I REF in terms of different device dimensions and temperature dependent terms using 13 and 14 is given as
IREF =
(18)
The transistors M25 and M22 are body biased using PTAT voltages V DS22 + V bias and V bias respectively. These PTAT voltages are able to reduce the CTAT effect of threshold voltages of M25 and M22 limiting temperature effect on the output reference voltage. This will reduce the process effect on V TH22 and V TH25 , hence to the output reference voltage. From (10), (16), (17) and (18), the expression of output reference voltage is given as ( ( ) ) K23 IREF 2K21 VREF = VTH0 + 𝜂 VT ln + 𝜂 2 VT ln K24 K25 I0 K22 ) ( 3K19 (19) + 𝜂 3 VT ln K20
The variation of these currents of node A is shown in Fig. 6. These currents I out and I out1 are PTAT in nature. When subtracted from each other it gives an error current I error which is also a PTAT but has very low slope variation. The value of I error is in pA having a slope of around ◦ ◦ 0.002 nA/ C. Similarly, the slope of I out2 is around 0.02 nA/ C. Therefore, to nullify the effect of temperature on I REF at node B, the current I error is scaled by 10X to have same slope. Then, this error current I ′ error is subtracted from the current I out2 to reduce the PTAT effect of temperature at higher temperature values resulting a reference current as shown in Fig. 7. After applying KCL at node B, the I REF is given as IREF = Iout2 −
(16)
( [ ( ) )] ( ) K8 (K12 K13 + K10 K14 − K11 K14 ) 3K19 I6 K5 𝜇n Cox K7 (𝜂 VT )2 ln + (𝜂 − 1) ln . ln K3 K10 K13 K 6 I0 K20 K4
(15)
circuit, the voltage drop across diode-connected transistors are fixed. If there is any change in supply voltage, the extra supply variation drops to those transistors in the branch other than diode connected transistors. It is assumed that the transistor M7 is operating in deep-triode region. As threshold voltage of M6 and M7 transistors are 355.6 mV and 331.5 mV respectively, the gate to source voltage of M6 and M7 are made equal to 340 mV such that M6 is operating in subthreshold
This will reduce the effect of temperature on the current at higher temperature components resulting in current with less temperature variation. It also reduces the effect of supply voltage on the current generated by CGC because of the current mirror concept as the output current of current mirror is only in terms of aspect ratio of the transistors of the current mirror. This concept helps in improving the PSRR as well as line regulation of the proposed CCMVRC. 5
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Fig. 13. V REF vs Supply Voltage for different temperature at typical process corner.
Fig. 14. V REF vs Supply Voltage for different process corner at room temperature.
region and M7 is operating in deep-triode region. The V DS7 is equal to 21.4 mV and V sat7 is equal to 62 mV satisfying V DS7 << 2V sat7 , condition for deep-triode region operation. Also, for reduction of channel length modulation effect, the length of all the transistors are made large enough.
4.4. Body biased transistors The proposed CCMVRC is having M7, M22, and M25 as the body biased transistors. The threshold voltage of these transistors are tested for variation of temperature and supply voltage variations which is shown in Figure 11 and 12 respectively. It is further observed that the bulk current through these transistors M7, M22, and M25 are 6.18 fA, 1.94 fA, and 3.97 fA respectively. Also, the ibd and ibs of transistors M7, M22, and M25 are 2.16 fA, 0.99 pA, 1.98 fA and 4.01 fA, 0.955 pA, 1.98 fA respectively. Therefore, it is concluded that these transistors are not having any bulk leakage problem.
4.2. Minimum supply voltage The minimum supply voltage is selected based on biasing requirement of different transistors of the proposed circuit. The biasing should be such that it allow all the transistors of each branch to operate in their respective region of operation. As most of the transistors are working in subthreshold region, the condition V DS ≥ 4V T should be satisfied by respective transistors. Based on each branch requirement for supply voltage under said condition, the minimum supply voltage can be given as
VDD min
⎛VGS6 + 4VT , VGS4 + 4VT , |VGS3 | + 4VT + VDS7 , VGS10 + 4VT , |VGS13 | + 4VT ,⎞ ⎟ ⎜ = max ⎜ |VGS15 | + 4VT , VGS20 + 4VT , VDS20 + VGS22 + 4VT , ⎟. ⎟ ⎜ 4VT + VGS24 + VGS25 + VDS22 + VDS20 , ⎠ ⎝
(20)
The expression (20) represents minimum supply requirement of each branch of the proposed CCMVRC. The last term represents the maximum voltage requirement branch. Considering V DS = 4V T ≈ 100 mV, the maximum value of last term in expression (20) is observed around 826 mV as V GS24 = 248 mV and V GS25 = 279 mV. Considering a proper margin for supply voltage, the minimum value for the proposed CCMVRC is taken as 950 mV.
4.3. Minimum supply current The minimum supply current is the requirement for low power applications of the proposed reference voltage. For this, the transistors of CGC should have minimum possible device dimensions specially for transistor M7 operating in deep-triode region to minimize the output current, I 7 . Keeping minimum current requirement and channel length modulation effect, M7 has aspect ratio of 0.4/10. However, the current is further decided by dimensions of M1, M3, M4, M5 and M6 transistors. Therefore, from expression (11) the ratio KKK1 and KK5 should be 3 6
4
minimum for lower output current. The dimensions of core transistors of the proposed CCMVRC is provided in Table 1 where m represents multiplier of transistor width and the layout is shown in Fig. 10.
Fig. 15. V REF vs Temperature for different supply voltages at typical process corner. 6
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Fig. 16. V REF vs Temperature for different process corners at supply voltages of 0.95 V without trimming.
Fig. 18. V REF vs Temperature for different process corners after trimming.
Table 2 The switch positions of trimming circuit for different corners. Corners
S0
S1
S2
FF FS SF SS TT
ON OFF ON OFF OFF
OFF ON ON OFF ON
OFF OFF OFF ON OFF
put V REF obtained is 609.7 mV at room temperature. Fig. 14 shows the variation of V REF vs V DD for different process corners. The worst case minimum and maximum value of V REF is 591 mV and 633 mV at FF and SS corners for 0.95 V and 1.8 V supply voltages respectively. In Fig. 15, the V REF vs temperature is plotted for different supply voltages variations. At 0.95 V supply, the variation of V REF is from 608.7 mV to 612.2 mV for temperature variation from −20 to 108 ◦ C ◦ resulting temperature coefficient (TC) of around 44.5 ppm/ C. The variation of V REF w.r.t. temperature for different process corners is shown
Fig. 17. Trimming circuit.
5. Simulation results 5.1. Simulation framework The proposed sub-1 V, MOS-only subthreshold current and voltage references are designed and implemented using Cadence EDA tool with Spectre as simulator for simulations in 180 nm CMOS technology. Simulations are performed for supply voltage varied from 0.95 to 1.8 V and temperature varied from −20 to 108 ◦ C. The variability of different corners are analyzed by performing Monte-Carlo simulations at constant supply and constant temperature. The calculation of line regulation and TC is performed by expressions ΔV REF /ΔV DD in mV/V and ΔV REF × 106 /(ΔT × Average V REF ) in ppm/◦ C respectively. 5.2. Result discussion The output reference voltage, V REF vs supply voltage, V DD plot for different temperatures is shown in Fig. 13. This shows V REF varies from 609 mV to 610.4 mV at room temperature for supply varying from 0.95 to 1.8 V resulting the line regulation (LR) of around 1.99 mV/V. Also, the LR at 0.8 V, 0.85 V and 0.9 V of supply voltage is given as 13.8 mV/V, 4.58 mV/V, and 2.57 mV/V respectively. The average out-
Fig. 19. Plot of supply current vs supply voltage for different process corners at room temperature. 7
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Fig. 22. Plot of PSRR vs frequency for different process corners at V DD = 0.95 V and T = 27 ◦ C.
Fig. 20. Plot of supply current vs temperature for different process corners at V DD = 0.95 V.
Fig. 23. Histogram of V REF after performing monte-carlo simulation at V DD = 0.95 V and T = 27 ◦ C.
temperature for different process corners. It is observed that the minimum and maximum value is 58.2 nA and 77.6 nA respectively for all corners. This small variation is due to extra cascaded current mirrors used for temperature compensation. In Fig. 21, the power supply rejection ratio (PSRR) plot for different frequencies is shown. At 0.95 mV supply, the PSRR value is −42dB. The increase in supply voltage causes rise in values of transconductance and output resistance of transistors contributing the PSRR. Hence, it is observed that the PSRR increases by increasing the supply voltage. In addition, the PSRR values for different corners shown in Fig. 22 have very small variation from −36.5 dB to −44dB. The Monte-Carlo simulations are performed for 1000 point considering process and mismatch variations in all transistors. The histogram
Fig. 21. Plot of PSRR vs frequency for different supply voltage at room temperature.
in Fig. 16. At FF and SS corners, worst case variation of the V REF is observed for complete temperature swing with value of 580 mV and 638 mV at 108 ◦ C respectively. This is because of the threshold voltage component in (19) contributing to slightly more CTAT voltage at high temperatures in case of FF corner and opposite for SS corner. The variation at remaining corners is around 3.5 mV which is acceptable to proposed TC value. A trimming circuit is adopted to further compensate the effect of process variations at different process corners. The trimming circuit configuration is shown in Fig. 17. The transistor M25 is trimmed using for better corner results of the output reference voltage. The trimmed results are shown in Fig. 18. The combination of switch positions is given in Table 2. After trimming, the worst case maximum and minimum variation of V REF 617.5 mV at 80 ◦ C and 598 mV at 108 ◦ C for FF and FS corners respectively. In Fig. 19, the variation of supply current w.r.t. V DD is shown at different process corners. At 0.95 V supply, the supply current varies from 60.4 nA to 61.4 nA for all corners. The minimum and maximum value of supply current is 60.4 nA and 66.3 nA for SS and FF corners respectively. Similarly, Fig. 20 shows the supply current variation w.r.t.
Fig. 24. Histogram plot of TC by sweeping temperature from −20 to 108 ◦ C at constant V DD = 0.95 V. 8
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are having TC greater than 300 ppm/ C. This can further be reduced by using proposed trimming circuit in Fig. 17. The upper limit of TC ◦ will be 3𝜎 value i.e. around 1092 ppm/ C. Similarly, Fig. 25 shows the histogram of Line Regulation (LR) values. It has 𝜇 and 𝜎 values of 3.2 mV/V and 2.44 mV/V respectively. The proposed CCMVRC is analyzed for input noise effect on output reference voltage. Noise analysis is performed by AC analysis in frequency range from 0.1 Hz to 10 MHz. The Fig. 26 shows the values of output noise for different frequencies. The output√RMS value of √ noise obtained is 56.8𝜇 V ∕ Hz at 10 Hz and 27.9𝜇 V ∕ Hz at 1 kHz having dominating transistors M3, M10, M11, and M3, M5, M11 respectively. The flat band integrated noise for the frequency range of 0.1 Hz to 10 kHz is 1.9 mV. The flicker noise is dominated by transistors M3, M6, and M64 up to 2 Hz frequency range. Beyond 2 Hz, the thermal noise is the dominated by transistors M10, M12, and M18. Finally, a comparison table is shown in Table 3 of the proposed CCMVRC with the recent literature based on subthreshold operating voltage references. To summarize different performance parameters of voltage references, a single parameter i.e. Figure of Merit (FOM) as presented in Ref. [8] is included as
Fig. 25. Histogram plot of LR by sweeping supply voltage from 0.95 to 1.8 V at constant temperature of T = 27 ◦ C.
FOM =
|PSRR@100Hz| TC × LR × Area × Supply Current
(21)
The conclusive advantages of proposed CCMVRC with other reported works is presented here in terms of performance parameters. It has lower line regulation than [8,15,25,29] and comparable line regulation than [10]. The proposed CCMVRC has less supply requirement than [10,18,21,28] which are using either resistor or BJT and has supply current in larger nano-ampere regime. Therefore, they require higher power dissipation than proposed reference. It has TC comparable to Refs. [10,15,24] and better than [12,22]. It has comparable PSRR than most of the literature except [13,18]. Finally, all the parameters are compared using a single parameter termed as FOM, which is best for the proposed CCMVRC among all reported recent works than [22], which has high FOM because of very low line regulation.
Fig. 26. Plot of output noise of proposed reference voltage at V DD = 0.95 V and T = 27 ◦ C.
of variability analysis using Monte-Carlo (MC) simulation is shown in Figs. 23–25. The Monte-Carlo simulation of output reference voltage is performed with V DD = 0.95 V at room temperature shown in Fig. 23. It gives a mean (𝜇 ) and standard deviation (𝜎 ) value of V REF as 607.9 mV and 20.4 mV respectively. This variation can further be reduced by using proposed trimming circuit. The histogram in Fig. 24 shows the variation pattern of the TC. Here, it can be observed that 𝜇 and 𝜎 val◦ ◦ ues are 133.5 ppm/ C and 364 ppm/ C respectively. This is because of three mean values in the range of 6 K–7 K causing such a large variation in the 𝜇 and 𝜎 values. From the Fig. 24, it is evident that 65% of the ◦ TC values fall in the range below 100 ppm/ C. The minimum TC values ◦ reported is 32.8 ppm/ C. The MC of TC gives 90% yield for TC val◦ ues less than 200 ppm/ C. Out of total 1000 point MC, only 47 points
6. Conclusion A low supply and low power subthreshold voltage reference is presented using current subtraction based temperature compensation. Standard beta-multiplier current generator followed by cascaded current mirror to improve current from supply and temperature variations resulting high PSRR and better LR. The output load consists of cascoded transistors generating PTAT and CTAT for output reference voltage. The circuit operates at 0.95 V supply with 60.7 nA current resulting a power requirement of 58 nW at room temperature. The average output voltage reference obtained at room temperature is 609.7 mV with a line ◦ regulation of 1.99 mV/V. The obtained TC is 44.5 ppm/ C for temper-
Table 3 Performance comparison of proposed and recent literatures on low power subthreshold voltage references. Parameters
Proposeda
[8]a
[25]a
[29]a
[10]b
[14]b
[15]b
[22]b
Technology Temperature (◦ C) Supply Voltage (V) VREF (mV) TC (ppm/◦ C) PSRR (dB)@100 Hz Line Regulation (mV/V) Supply Current (𝜇 A) Die Area (mm2 ) FOM
180 nm −20 to 108 0.95 to 1.8 609.7 44.5 −42 1.99 [email protected] V 0.0082 964
180 nm −40 to 120 1.4 to 2 650 82 −70 3.33c [email protected] Vc 0.035 159
180 nm −20 to 80 0.6 441 25 −44 30c [email protected] Vc 0.00715 158
28 nm −15 to 80 0.85 to 4.1 252 218.8 −34c 6.46c [email protected] Vc NA NA
130 nm −40 to 85 1 to 3.3 598 47 −44 1.3c 1@1 V 0.02 36
180 nm −20 to 80 1.35 to 1.8 630 14.1 −75.7@dc 0.298 [email protected] V 0.015 1365
180 nm −40 to 60 0.8 to 2 467.2 38.7 NA 7.4 [email protected] Vc 0.0033 NA
180 nm −40 to 140 0.4 210 82 −45c 0.056c [email protected] V 0.021 46665
a b c
Simulated Values. Measured Values. Calculated from given data and graph of existing literature. 9
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ature ranging from −20 to 108 ◦ C. The proposed CCMVRC exhibits a PSRR of −42 dB at 100 Hz. It has an active area of 0.0082 mm2 .
[13] J. Jiang, W. Shu, J.S. Chang, A 5.6 ppm/C temperature coefficient, 87-db psrr, sub-1-v voltage reference in 65-nm cmos exploiting the zero-temperature-coefficient point, IEEE J. Solid State Circuits 52 (3) (2017) 623–633. [14] Z.-k. Zhou, Y. Shi, C. Gou, X. Wang, G. Wu, J.-f. Feng, Z. Wang, B. Zhang, A resistorless low-power voltage reference, IEEE Trans. Circuits Syst. II: Express Briefs 63 (7) (2016) 613–617. [15] Q. Yang, P. Han, N. Mei, Z. Zhang, A 16.4 nw, sub-1 v, resistor-less voltage reference with bjt voltage divider, J. Circuits Syst. Comput. 27 (13) (2018) 1850206. [16] C. Yu, L. Siek, An area-efficient current-mode bandgap reference with intrinsic robust start-up behavior, IEEE Trans. Circuits Syst. II: Express Briefs 62 (10) (2015) 937–941. [17] A.K. Singh, P.K. Pal, M. Pattanaik, A wide temperature range voltage bandgap reference generator in 32nm cmos technology, in: 2015 Global Conference on Communication Technologies (GCCT), IEEE, 2015, pp. 696–699. [18] Q.L. Li, W. Deng, X.Y. Ma, J. Huang, A novel low line regulation voltage reference with no amplifier, J. Circuits Syst. Comput. 27 (10) (2018) 1850152. [19] K. Ueno, T. Hirose, T. Asai, Y. Amemiya, A 300 nw, 15 ppm/C, 20 ppm/v cmos voltage reference circuit consisting of subthreshold mosfets, IEEE J. Solid State Circuits 44 (7) (2009) 2047–2054. [20] H. Wang, P.P. Mercier, A 3.4-pw 0.4-v 469.3 ppm/C five-transistor current reference generator, IEEE Solid-State Circuits Lett. 1 (5) (2018) 122–125. [21] Y. Liu, C. Zhan, L. Wang, An ultralow power subthreshold cmos voltage reference without requiring resistors or bjts, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26 (1) (2018) 201–205. [22] Y. Liu, C. Zhan, L. Wang, J. Tang, G. Wang, A 0.4-v wide temperature range all-mosfet subthreshold voltage reference with 0.027/v line sensitivity, IEEE Trans. Circuits Syst. II: Express Briefs 65 (8) (2018) 969–973. [23] B. Aggarwal, M. Gupta, A.K. Gupta, A comparative study of various current mirror configurations: topologies and characteristics, Microelectron. J. 53 (2016) 134–155. [24] J. Duan, Z. Zhu, J. Deng, W. Xu, B. Wei, A novel 0.8-v 79-nw cmos-only voltage reference with- 55-db psrr@ 100 hz, IEEE Trans. Circuits Syst. II: Express Briefs 65 (7) (2018) 849–853. [25] Z. Zhu, et al., A 0.6 v 31 nw 25 ppm/C mosfet-only sub-threshold voltage reference, Microelectron. J. 66 (2017) 25–30. [26] Y. Zeng, Y. Huang, Y. Luo, H.-Z. Tan, An ultra-low-power cmos voltage reference generator based on body bias technique, Microelectron. J. 44 (12) (2013) 1145–1153. [27] Y. Wang, Z. Zhu, J. Yao, Y. Yang, A 0.45-v, 14.6-nw cmos subthreshold voltage reference with no resistors and no bjts, IEEE Trans. Circuits Syst. II: Express Briefs 62 (7) (2015) 621–625. [28] I. Lee, D. Sylvester, D. Blaauw, A subthreshold voltage reference with scalable output voltage for low-power iot systems, IEEE J. Solid State Circuits 52 (5) (2017) 1443–1449. [29] M. Mohammed, K. Abugharbieh, M. Abdelfattah, S. Kawar, Design methodology for mosfet-based voltage reference circuits implemented in 28 nm cmos technology, AEU-Int. J. Electron. Commun. 70 (5) (2016) 568–577. [30] Z. Zhu, J. Hu, Y. Wang, A 0.45 v, nano-watt 0.033 line sensitivity mosfet-only sub-threshold voltage reference with no amplifiers, IEEE Trans. Circuits Syst. I: Reg. Pap. 63 (9) (2016) 1370–1380. [31] S.S. Bethi, K.S. Lee, R. Veillette, J. Carletta, M. Willett, A temperature and process insensitive CMOS reference current generator, in: Midwest Symposium on Circuits and Systems, 2013, pp. 301–304.
Acknowledgement The authors are thankful to the ministry Of Electronics And Information Technology (Meity), Govt. of India, for grants and supports provide as special manpower development program. The Department of Electronic and Communication Engineering, MMMUT, Gorakhpur, India is acknowledged for providing the necessary infrastructure. The Department of Electronic and Communication Engineering, MN National Institute of Technology Allahabad, India is also highly acknowledged for providing the necessary tools for calculations and simulations. References [1] B. Razavi, Design of Analog CMOS Integrated Circuits, first ed., McGraw-Hill, Inc., New York, NY, USA, 2001. [2] A.K. Dubey, R.K. Nagaria, Enhanced gain low-power cmos amplifiers: a novel design approach using bulk-driven load and introduction to gacoba technique, J. Circuits Syst. Comput. 27 (13) (2018) 1850204. [3] P.K. Pal, A.K. Dubey, S.R. Kassa, R.K. Nagaria, Voltage comparison based high speed & low power domino circuit for wide fan-in gates, in: 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), IEEE, 2016, pp. 96–99. [4] A. Kumar, R. Nagaria, A new leakage-tolerant high speed comparator based domino gate for wide fan-in or logic for low power vlsi circuits, Integration 63 (2018) 174–184. [5] P.K. Pal, A.K. Singh, M. Pattanaik, Energy efficient design of direct coupled pass transistor based pulse triggered flip-flop, in: 2015 International Conference on Technological Advancements in Power and Energy (TAP Energy), IEEE, 2015, pp. 161–164. [6] X.L. Tan, P.K. Chan, U. Dasgupta, A sub-1-v 65-nm mos threshold monitoring-based voltage reference, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (10) (2015) 2317–2321. [7] C. Yongda, Z. Zhige, W. Zhen, L. Jianming, Threshold-voltage-difference-based cmos voltage reference derived from basic current bias generator with 4.3 ppm/C temperature coefficient, Electron. Lett. 50 (7) (2014) 505–507. [8] S. Yousefi, M. Jalali, A high-psrr low-power cmos voltage reference based on weighted vgs difference, AEU-Int. J. Electron. Commun. 70 (1) (2016) 50–57. [9] L. Liu, Y. Song, J. Mu, W. Guo, Z. Zhu, Y. Yang, A high accuracy cmos subthreshold voltage reference with offset cancellation and thermal compensation, Microelectron. J. 60 (2017) 102–108. [10] A. Parisi, A. Finocchiaro, G. Palmisano, An accurate 1-v threshold voltage reference for ultra-low power applications, Microelectron. J. 63 (2017) 155–159. [11] Z. Qianneng, Y. Kai, L. Jinzhao, P. Yu, L. Guoquan, L. Wei, Novel high-psrr high-order curvature-compensated bandgap voltage reference, J. China Univ. Posts Telecommun. 23 (2) (2016) 66–96. [12] P.B. Basyurt, E. Bonizzoni, D.Y. Aksin, F. Maloberti, A 0.4-v supply curvature-corrected reference generator with 84.5-ppm/C average temperature coefficient within- 40C to 130C, IEEE Trans. Circuits Syst. II: Express Briefs 64 (4) (2017) 362–366.
10
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Integration, the VLSI Journal journal homepage: www.elsevier.com/locate/vlsi
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load Pratosh Kumar Pal a, ∗ , R.K. Nagaria b a b
Electronics and Communication Engineering Department, Madan Mohan Malviya University of Technology, Gorakhpur, Gorakhpur, 273010, India Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, 211004, India
A R T I C L E
I N F O
Keywords: Sub-1 V Cascaded current mirror Subthreshold Current reference Voltage reference
A B S T R A C T
A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/◦ C for a temperature range of −20 to 108 ◦ C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2 . The obtained average reference current is 6 nA having a slope of 5.5pA/◦ C.
1. Introduction The current and voltage reference circuits are a must component of any analog and mixed-signal circuits which is used as a constant current or supply voltage independent of process, supply voltage, and temperature (PVT) variations. The developing modern electronics needs low voltage and low power reference circuits with high performance parameters like compact area. These compact devices require very low supply voltage and currents in nano-ampere resulting nano-watt power dissipation. Therefore, the use of resistors and BJTs are avoided in designing a bandgap reference as they have bulky size and higher bandgap voltage i.e. around 1.2 V [1]. Hence, MOSFETs operating in subthreshold region are considered as the replacement for designing current and voltage reference circuits for fulfilling the demands of low voltage and low power applications [2–5]. The design and analysis of subthreshold voltage reference is done after a thorough literature survey of different voltage references to have an overall better performance. In literature, there are different references proposed using BJTs, resistors and MOSFETs in different combinations. The voltage references in Refs. [6–13] use only resistors and in Refs. [14–18] use resistors and BJTs both. These voltage
references require high supply voltage up to 4 V and current in microamperes resulting high power dissipation and larger active area. Therefore, reference circuits without resistors and BJTs are reported in Refs. [19–31] operating in the subthreshold and saturation region. In Ref. [25], body biased resistorless reference is presented to reduce temperature effect. Due to very low supply variation option from 0.6 to 0.7 V, it has high line regulation which is improved by the proposed reference. [21] proposes a voltage reference without BJTs and resistors for compact area and ultralow power dissipation by employing leakage current of subthreshold transistor as PTAT source. In Ref. [22], reference voltage is generated by feeding supply independent current into the active load. Also uses trimming circuit for reducing process effects. The brief reported in Ref. [31] shows improved arrangement of triode-based widlar reference to reduce both circuit complexity and overall current consumption and [23] gives a survey on different methods of current reference generation. The reference [20], proposes a reference current near-zero power dissipation of 3.4 pW with average reference current ◦ of 1.2 pA at V DD = 0.4 V with TC = 469.3 ppm/ C. In Ref. [24], the difference of two PTAT currents for generation of current reference which is supplied to active load circuit for reference voltage generation is pro-
∗ Corresponding author. E-mail addresses: [email protected] (P.K. Pal), [email protected] (R.K. Nagaria). https://doi.org/10.1016/j.vlsi.2019.11.016 Received 14 May 2019; Received in revised form 24 August 2019; Accepted 26 November 2019 Available online XXX 0167-9260/© 2019 Elsevier B.V. All rights reserved.
Please cite this article as: P.K. Pal, R.K. Nagaria, A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load, Integration, the VLSI Journal, https://doi.org/10.1016/j.vlsi.2019.11.016
P.K. Pal, R.K. Nagaria
Integration, the VLSI Journal xxx (xxxx) xxx
ature variations which is supplied to ALC. The ALC consists of cascode connection of Self-cascode MOSFET (SCM) circuits and an NMOS transistor for temperature compensation of the output voltage reference. The SCM circuit is having two NMOS transistors connected in cascode mode which gives a PTAT voltage source. The proposed circuit has all the transistors of the output ALC operating in subthreshold region. The mathematical expression for the current of a subthreshold operating MOS [21] having V DS ≥ 4V T is given by ( ) ( ) VGS − VTH W exp Isub = Io (1) L 𝜂 VT where Io = 𝜇 Cox (𝜂 − 1) VT2 and 𝜇 , Cox , 𝜂 , V T , W/L = K, and V TH are mobility of electrons or holes, gate-oxide capacitance per unit area, subthreshold slope parameter, thermal voltage, aspect ratio of the MOS transistor and threshold voltage respectively. The typical value of 𝜂 is 1.5 [25]. The Wand L are channel width and length of the MOS transistor respectively. The expression of output reference voltage is the sum of three PTAT voltages from SCM circuit and one CTAT from NMOS as in Fig. 1, given as
Fig. 1. Basic operating principle of proposed CCMVRC.
VREF = VDS8 + VDS10 + VDS12 + VGS13
(2)
In expression (2), the starting three voltage terms represent a PTAT voltage and the fourth term represents a CTAT voltage. The sum of these PTAT and CTAT voltages in appropriate proportion give rise to an output reference voltage independent of supply and temperature variations. This is done by providing proper optimization to the transistor sizes representing these PTAT and CTAT voltages which are explained in following sections.
posed. But it uses Standard-V TH (SVT) and High-V TH (HVT) transistors as active load resulting complex fabrication process. The work presented in this brief is a sub-1 V, high PSRR subthreshold voltage reference employing cascaded current mirror based supply and temperature compensation circuit. Hence, this Cascaded Current Mirror based Voltage Reference Circuit (CCMVRC) has high PSRR. A Cascode connection of MOS transistors used as active load circuit for output reference voltage. The operating supply voltage is 0.95 V which ◦ results in output reference voltage of 609 mV with TC of 44.5 ppm/ C. The remaining contents of this brief are presented in following sections: Section 2 presents the basic working concept of proposed CCMVRC with description of the proposed circuit given in Section 3. The Section 4 explains the different design related considerations taken while analyzing the proposed CCMVRC and the simulation results and results explanation is provided in Sections 5. Finally the conclusion of the presented work is included in the Section 6.
3. Proposed voltage reference circuit description The core of the presented CCMVRC is shown in Fig. 2 consists of following circuit blocks: start-up circuit, beta-multiplier based current generator, cascaded current mirror circuit, and cascoded transistors as active load. The start-up circuit is used to avoid the unwanted zero current mode operation of the proposed voltage reference. The current generator circuit utilizes the concept of beta-multiplier to generate a supply independent current followed by cascaded current mirrors to further compensate the temperature effect on the generated supply independent current by CGC. This results in a reference current independent of supply and temperature. This reference current is then fed to active load circuit to give a supply and temperature independent output voltage reference. The body effect is utilized to reduce the effect of temperature on threshold voltages of the ALC transistors. The rest of circuit description is explained in the following subsections in detail.
2. Principle of operation The basic principle of operation of the proposed voltage reference circuit is shown in Fig. 1. Here, a supply independent current is further compensated for temperature independence before going to the ALC. This gives a reference current independent of supply and temper-
Fig. 2. The core schematic of the proposed CCMVRC. 2
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Fig. 3. The core of the proposed current reference.
Fig. 5. Variation of I 7 with respect of temperature for different supply variations.
Fig. 4. Variation of I 7 with respect of V DD for different temperature variations. Fig. 6. Plot of I error , I out and I out1 of node A vs temperature for V DD = 0.95.
3.1. Supply independent current generator circuit The supply independent current generator circuit consists of transistors numbered from M1-M7 as shown in Fig. 3. The transistors M1-M3 is used as a current mirror to have currents in I 1 , I 2 , and I 3 branches. Here, all the transistors of CGC are working in subthreshold region except M7 which is operating in deep-triode region as an active resistor to avoid larger power dissipation instead of using passive resistor. From Fig. 3, it is observed that VGS4 = VGS5 + VDS7 .
From (4), (5) and (6), the I 7 is given as ( ) ( ) K5 ∗ 𝜂 VT ln . I7 = 𝜇n Cox K7 VGS7 − VTH7 K4
(7)
The threshold voltage of MOS transistors with body biasing is given as
(3)
The transistors M4 and M5 are operating in subthreshold region and it have equal threshold voltages as it has zero source to body voltage. Then from (2) and (3), the expression of V DS7 is given as VDS7 = 𝜂 VT ln(
K5 ). K4
(4)
The transistor M7 is operating in strong inversion, deep-triode region as an active resistor and the expression for its resistance with ∗ body biased threshold voltage VTH7 is given as R7 =
1 ∗ ) 𝜇n Cox K7 (VGS7 − VTH7
.
(5)
The output current of the CGC is expressed as the drain current of M7, given by I7 =
VDS7 . R7
(6)
Fig. 7. Plot of I ′ error , I out2 and I REF of node B vs temperature for V DD = 0.95. 3
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Table 1 The channel length and width of different transistors used in the proposed CCMVRC. Transistor
W (𝜇 m) × m∗ /L [𝜇 m]
Transistor
W [𝜇 m] × m∗ /L [𝜇 m]
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13
5 × 5/10 5 × 4/10 5 × 4/10 2 × 4/10 4 × 4/10 0.4 × 1/10 0.4 × 1/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 4/10 5 × 1/10
M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25
5× 5× 5× 5× 5× 5× 5× 5× 5× 5× 5× 5×
10/10 2/10 2/10 2/10 2/10 11/10 1/10 11/10 1/10 11/10 1/10 2/10
Fig. 8. Plot of I REF with respect to supply voltage for different temperature variations.
Fig. 10. The layout 75 𝜇m × 109 𝜇m.
(√
2ΦF + VSB −
√
) 2ΦF .
the
proposed
CCMVRC
with
dimensions
The expression (11) gives a current independent of supply voltage variation as it has no supply voltage term. This current is fed to the next block of current subtraction based temperature compensation for reference current generation. The plot showing variation of current I 7 with respect to supply and temperature variations is shown in Figs. 4 and 5.
Fig. 9. Plot of I REF with respect to temperature for different supply variations.
VTH = VTH0 + 𝛾
of
(8)
where ΦF , V TH0 , 𝛾 , and V SB are fermi potential, threshold voltage with no body bias, body effect coefficient and source to body voltage of the MOSFET respectively. The threshold voltage expression is further simplified by using body effect approximation [26] represented as VTH ≈ VTH0 + (𝜂 − 1) VSB
(9)
The body biasing voltage of M7 is generated by SCM circuit having transistors M19 and M20 operating in subthreshold region in ALC of Fig. 2. As V TH of M19 and M20 are same, the V bias by (1) is given as Vbias = VDS20 = 𝜂 VT ln
3K19 . K20
(10)
As V bias is directly proportional to V T , it is a PTAT voltage for the condition when K 19 > K 20 . This PTAT voltage reduces the effect of temperature on V TH7 resulting in process variation reduction. From Fig. 3, it is observed that V GS7 = V GS6 and assuming equal V TH0 of M6 and M7, the expression of output current I 7 from (1), (7), (9), and (10) is given as ( [ ( ) )] ( ) 3K19 I6 K5 I7 = 𝜇n Cox K7 (𝜂 VT )2 ln + (𝜂 − 1) ln . (11) ln K 6 I0 K20 K4
Fig. 11. Variation of threshold voltage of body biased transistors with respect to temperature. 4
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3.3. Cascode transistors as active load circuit The core schematic of the proposed voltage reference is shown in Fig. 2. It is having cascoded transistors working in subthreshold region as ALC. The ALC consists of transistors numbered from M15-M25. It has all the transistors operating in subthreshold region. The transistors M15-M18 are the part of current mirror circuit that copies the reference current I REF to the ALC. The load stage is used to compensate the effect of temperature on the output reference voltage, V REF . The selfcascode MOSFET pairs M19-M20, M21-M22, and M23-M24 generate three PTAT voltages as the drain to source voltages of M20, M22 and M24 respectively. The CTAT voltage is generated by the gate to source voltage of M25. Here, the output voltage reference voltage from (2) and (10) is given as Fig. 12. The plot of threshold voltage variation of body biased transistors of CCMVRC with respect to supply voltage.
VREF = Vbias + VDS22 + VDS24 + VGS25 .
From (1) and (9), the gate to source voltage of M25 is given as ( ) IREF VGS25 = VTH0 + (𝜂 − 1) (Vbias + VDS22 ) + 𝜂 VT ln . (17) I0 K25
3.2. Cascaded current mirror based reference current
Similarly, the drain to source voltages V DS22 is given as ) ( 2K21 . VDS22 = (𝜂 − 1) Vbias + 𝜂 VT ln K22
The cascaded current mirror is used to reduce the effect of temperature and supply voltage on the current generated by the CGC. Here, the concept of error current is used to reduce the temperature effect on current by subtracting the error from the current generated by CGC. The cascaded current mirror circuit configuration consists of transistors numbered from M8-M12 is shown in Fig. 3. All the transistors are working in subthreshold region of MOS operations. The transistor pairs M3-M8, M3-M9, M10-M11, M13-M14, and M10-M12 are used as a current mirror to produce scaled currents to their respective branches. The currents I out and I out1 are scaled version currents of PMOS and NMOS current mirrors respectively. By KCL at node A, we have Ierror = Iout1 − Iout .
K14 I . K13 error
(12)
The expression (19) has summation of CTAT and PTAT voltage terms. The first term is a CTAT and the last three terms are a PTAT. Therefore, by varying the aspect ratio terms of different transistors present in these voltage terms, a better TC of output reference voltage is obtained from expression (19). This will give a reference voltage as independent as possible to supply voltage and temperature variations. The variation of I REF with respect to supply and temperature variations is shown in Figs. 8 and 9.
(13)
4. Design considerations
The expression of I REF in terms of current I 7 using different current mirrors is given as IREF
K8 = (K K + K10 K14 − K11 K14 )I7 . K3 K10 K13 12 13
4.1. Transistor biasing
(14)
Transistor biasing is implemented such that all the transistors are working in their respective region of operation to ensure correct output at each stage of the proposed CCMVRC. In any branch of the proposed
Finally, the expression of I REF in terms of different device dimensions and temperature dependent terms using 13 and 14 is given as
IREF =
(18)
The transistors M25 and M22 are body biased using PTAT voltages V DS22 + V bias and V bias respectively. These PTAT voltages are able to reduce the CTAT effect of threshold voltages of M25 and M22 limiting temperature effect on the output reference voltage. This will reduce the process effect on V TH22 and V TH25 , hence to the output reference voltage. From (10), (16), (17) and (18), the expression of output reference voltage is given as ( ( ) ) K23 IREF 2K21 VREF = VTH0 + 𝜂 VT ln + 𝜂 2 VT ln K24 K25 I0 K22 ) ( 3K19 (19) + 𝜂 3 VT ln K20
The variation of these currents of node A is shown in Fig. 6. These currents I out and I out1 are PTAT in nature. When subtracted from each other it gives an error current I error which is also a PTAT but has very low slope variation. The value of I error is in pA having a slope of around ◦ ◦ 0.002 nA/ C. Similarly, the slope of I out2 is around 0.02 nA/ C. Therefore, to nullify the effect of temperature on I REF at node B, the current I error is scaled by 10X to have same slope. Then, this error current I ′ error is subtracted from the current I out2 to reduce the PTAT effect of temperature at higher temperature values resulting a reference current as shown in Fig. 7. After applying KCL at node B, the I REF is given as IREF = Iout2 −
(16)
( [ ( ) )] ( ) K8 (K12 K13 + K10 K14 − K11 K14 ) 3K19 I6 K5 𝜇n Cox K7 (𝜂 VT )2 ln + (𝜂 − 1) ln . ln K3 K10 K13 K 6 I0 K20 K4
(15)
circuit, the voltage drop across diode-connected transistors are fixed. If there is any change in supply voltage, the extra supply variation drops to those transistors in the branch other than diode connected transistors. It is assumed that the transistor M7 is operating in deep-triode region. As threshold voltage of M6 and M7 transistors are 355.6 mV and 331.5 mV respectively, the gate to source voltage of M6 and M7 are made equal to 340 mV such that M6 is operating in subthreshold
This will reduce the effect of temperature on the current at higher temperature components resulting in current with less temperature variation. It also reduces the effect of supply voltage on the current generated by CGC because of the current mirror concept as the output current of current mirror is only in terms of aspect ratio of the transistors of the current mirror. This concept helps in improving the PSRR as well as line regulation of the proposed CCMVRC. 5
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Fig. 13. V REF vs Supply Voltage for different temperature at typical process corner.
Fig. 14. V REF vs Supply Voltage for different process corner at room temperature.
region and M7 is operating in deep-triode region. The V DS7 is equal to 21.4 mV and V sat7 is equal to 62 mV satisfying V DS7 << 2V sat7 , condition for deep-triode region operation. Also, for reduction of channel length modulation effect, the length of all the transistors are made large enough.
4.4. Body biased transistors The proposed CCMVRC is having M7, M22, and M25 as the body biased transistors. The threshold voltage of these transistors are tested for variation of temperature and supply voltage variations which is shown in Figure 11 and 12 respectively. It is further observed that the bulk current through these transistors M7, M22, and M25 are 6.18 fA, 1.94 fA, and 3.97 fA respectively. Also, the ibd and ibs of transistors M7, M22, and M25 are 2.16 fA, 0.99 pA, 1.98 fA and 4.01 fA, 0.955 pA, 1.98 fA respectively. Therefore, it is concluded that these transistors are not having any bulk leakage problem.
4.2. Minimum supply voltage The minimum supply voltage is selected based on biasing requirement of different transistors of the proposed circuit. The biasing should be such that it allow all the transistors of each branch to operate in their respective region of operation. As most of the transistors are working in subthreshold region, the condition V DS ≥ 4V T should be satisfied by respective transistors. Based on each branch requirement for supply voltage under said condition, the minimum supply voltage can be given as
VDD min
⎛VGS6 + 4VT , VGS4 + 4VT , |VGS3 | + 4VT + VDS7 , VGS10 + 4VT , |VGS13 | + 4VT ,⎞ ⎟ ⎜ = max ⎜ |VGS15 | + 4VT , VGS20 + 4VT , VDS20 + VGS22 + 4VT , ⎟. ⎟ ⎜ 4VT + VGS24 + VGS25 + VDS22 + VDS20 , ⎠ ⎝
(20)
The expression (20) represents minimum supply requirement of each branch of the proposed CCMVRC. The last term represents the maximum voltage requirement branch. Considering V DS = 4V T ≈ 100 mV, the maximum value of last term in expression (20) is observed around 826 mV as V GS24 = 248 mV and V GS25 = 279 mV. Considering a proper margin for supply voltage, the minimum value for the proposed CCMVRC is taken as 950 mV.
4.3. Minimum supply current The minimum supply current is the requirement for low power applications of the proposed reference voltage. For this, the transistors of CGC should have minimum possible device dimensions specially for transistor M7 operating in deep-triode region to minimize the output current, I 7 . Keeping minimum current requirement and channel length modulation effect, M7 has aspect ratio of 0.4/10. However, the current is further decided by dimensions of M1, M3, M4, M5 and M6 transistors. Therefore, from expression (11) the ratio KKK1 and KK5 should be 3 6
4
minimum for lower output current. The dimensions of core transistors of the proposed CCMVRC is provided in Table 1 where m represents multiplier of transistor width and the layout is shown in Fig. 10.
Fig. 15. V REF vs Temperature for different supply voltages at typical process corner. 6
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Fig. 16. V REF vs Temperature for different process corners at supply voltages of 0.95 V without trimming.
Fig. 18. V REF vs Temperature for different process corners after trimming.
Table 2 The switch positions of trimming circuit for different corners. Corners
S0
S1
S2
FF FS SF SS TT
ON OFF ON OFF OFF
OFF ON ON OFF ON
OFF OFF OFF ON OFF
put V REF obtained is 609.7 mV at room temperature. Fig. 14 shows the variation of V REF vs V DD for different process corners. The worst case minimum and maximum value of V REF is 591 mV and 633 mV at FF and SS corners for 0.95 V and 1.8 V supply voltages respectively. In Fig. 15, the V REF vs temperature is plotted for different supply voltages variations. At 0.95 V supply, the variation of V REF is from 608.7 mV to 612.2 mV for temperature variation from −20 to 108 ◦ C ◦ resulting temperature coefficient (TC) of around 44.5 ppm/ C. The variation of V REF w.r.t. temperature for different process corners is shown
Fig. 17. Trimming circuit.
5. Simulation results 5.1. Simulation framework The proposed sub-1 V, MOS-only subthreshold current and voltage references are designed and implemented using Cadence EDA tool with Spectre as simulator for simulations in 180 nm CMOS technology. Simulations are performed for supply voltage varied from 0.95 to 1.8 V and temperature varied from −20 to 108 ◦ C. The variability of different corners are analyzed by performing Monte-Carlo simulations at constant supply and constant temperature. The calculation of line regulation and TC is performed by expressions ΔV REF /ΔV DD in mV/V and ΔV REF × 106 /(ΔT × Average V REF ) in ppm/◦ C respectively. 5.2. Result discussion The output reference voltage, V REF vs supply voltage, V DD plot for different temperatures is shown in Fig. 13. This shows V REF varies from 609 mV to 610.4 mV at room temperature for supply varying from 0.95 to 1.8 V resulting the line regulation (LR) of around 1.99 mV/V. Also, the LR at 0.8 V, 0.85 V and 0.9 V of supply voltage is given as 13.8 mV/V, 4.58 mV/V, and 2.57 mV/V respectively. The average out-
Fig. 19. Plot of supply current vs supply voltage for different process corners at room temperature. 7
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Fig. 22. Plot of PSRR vs frequency for different process corners at V DD = 0.95 V and T = 27 ◦ C.
Fig. 20. Plot of supply current vs temperature for different process corners at V DD = 0.95 V.
Fig. 23. Histogram of V REF after performing monte-carlo simulation at V DD = 0.95 V and T = 27 ◦ C.
temperature for different process corners. It is observed that the minimum and maximum value is 58.2 nA and 77.6 nA respectively for all corners. This small variation is due to extra cascaded current mirrors used for temperature compensation. In Fig. 21, the power supply rejection ratio (PSRR) plot for different frequencies is shown. At 0.95 mV supply, the PSRR value is −42dB. The increase in supply voltage causes rise in values of transconductance and output resistance of transistors contributing the PSRR. Hence, it is observed that the PSRR increases by increasing the supply voltage. In addition, the PSRR values for different corners shown in Fig. 22 have very small variation from −36.5 dB to −44dB. The Monte-Carlo simulations are performed for 1000 point considering process and mismatch variations in all transistors. The histogram
Fig. 21. Plot of PSRR vs frequency for different supply voltage at room temperature.
in Fig. 16. At FF and SS corners, worst case variation of the V REF is observed for complete temperature swing with value of 580 mV and 638 mV at 108 ◦ C respectively. This is because of the threshold voltage component in (19) contributing to slightly more CTAT voltage at high temperatures in case of FF corner and opposite for SS corner. The variation at remaining corners is around 3.5 mV which is acceptable to proposed TC value. A trimming circuit is adopted to further compensate the effect of process variations at different process corners. The trimming circuit configuration is shown in Fig. 17. The transistor M25 is trimmed using for better corner results of the output reference voltage. The trimmed results are shown in Fig. 18. The combination of switch positions is given in Table 2. After trimming, the worst case maximum and minimum variation of V REF 617.5 mV at 80 ◦ C and 598 mV at 108 ◦ C for FF and FS corners respectively. In Fig. 19, the variation of supply current w.r.t. V DD is shown at different process corners. At 0.95 V supply, the supply current varies from 60.4 nA to 61.4 nA for all corners. The minimum and maximum value of supply current is 60.4 nA and 66.3 nA for SS and FF corners respectively. Similarly, Fig. 20 shows the supply current variation w.r.t.
Fig. 24. Histogram plot of TC by sweeping temperature from −20 to 108 ◦ C at constant V DD = 0.95 V. 8
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are having TC greater than 300 ppm/ C. This can further be reduced by using proposed trimming circuit in Fig. 17. The upper limit of TC ◦ will be 3𝜎 value i.e. around 1092 ppm/ C. Similarly, Fig. 25 shows the histogram of Line Regulation (LR) values. It has 𝜇 and 𝜎 values of 3.2 mV/V and 2.44 mV/V respectively. The proposed CCMVRC is analyzed for input noise effect on output reference voltage. Noise analysis is performed by AC analysis in frequency range from 0.1 Hz to 10 MHz. The Fig. 26 shows the values of output noise for different frequencies. The output√RMS value of √ noise obtained is 56.8𝜇 V ∕ Hz at 10 Hz and 27.9𝜇 V ∕ Hz at 1 kHz having dominating transistors M3, M10, M11, and M3, M5, M11 respectively. The flat band integrated noise for the frequency range of 0.1 Hz to 10 kHz is 1.9 mV. The flicker noise is dominated by transistors M3, M6, and M64 up to 2 Hz frequency range. Beyond 2 Hz, the thermal noise is the dominated by transistors M10, M12, and M18. Finally, a comparison table is shown in Table 3 of the proposed CCMVRC with the recent literature based on subthreshold operating voltage references. To summarize different performance parameters of voltage references, a single parameter i.e. Figure of Merit (FOM) as presented in Ref. [8] is included as
Fig. 25. Histogram plot of LR by sweeping supply voltage from 0.95 to 1.8 V at constant temperature of T = 27 ◦ C.
FOM =
|PSRR@100Hz| TC × LR × Area × Supply Current
(21)
The conclusive advantages of proposed CCMVRC with other reported works is presented here in terms of performance parameters. It has lower line regulation than [8,15,25,29] and comparable line regulation than [10]. The proposed CCMVRC has less supply requirement than [10,18,21,28] which are using either resistor or BJT and has supply current in larger nano-ampere regime. Therefore, they require higher power dissipation than proposed reference. It has TC comparable to Refs. [10,15,24] and better than [12,22]. It has comparable PSRR than most of the literature except [13,18]. Finally, all the parameters are compared using a single parameter termed as FOM, which is best for the proposed CCMVRC among all reported recent works than [22], which has high FOM because of very low line regulation.
Fig. 26. Plot of output noise of proposed reference voltage at V DD = 0.95 V and T = 27 ◦ C.
of variability analysis using Monte-Carlo (MC) simulation is shown in Figs. 23–25. The Monte-Carlo simulation of output reference voltage is performed with V DD = 0.95 V at room temperature shown in Fig. 23. It gives a mean (𝜇 ) and standard deviation (𝜎 ) value of V REF as 607.9 mV and 20.4 mV respectively. This variation can further be reduced by using proposed trimming circuit. The histogram in Fig. 24 shows the variation pattern of the TC. Here, it can be observed that 𝜇 and 𝜎 val◦ ◦ ues are 133.5 ppm/ C and 364 ppm/ C respectively. This is because of three mean values in the range of 6 K–7 K causing such a large variation in the 𝜇 and 𝜎 values. From the Fig. 24, it is evident that 65% of the ◦ TC values fall in the range below 100 ppm/ C. The minimum TC values ◦ reported is 32.8 ppm/ C. The MC of TC gives 90% yield for TC val◦ ues less than 200 ppm/ C. Out of total 1000 point MC, only 47 points
6. Conclusion A low supply and low power subthreshold voltage reference is presented using current subtraction based temperature compensation. Standard beta-multiplier current generator followed by cascaded current mirror to improve current from supply and temperature variations resulting high PSRR and better LR. The output load consists of cascoded transistors generating PTAT and CTAT for output reference voltage. The circuit operates at 0.95 V supply with 60.7 nA current resulting a power requirement of 58 nW at room temperature. The average output voltage reference obtained at room temperature is 609.7 mV with a line ◦ regulation of 1.99 mV/V. The obtained TC is 44.5 ppm/ C for temper-
Table 3 Performance comparison of proposed and recent literatures on low power subthreshold voltage references. Parameters
Proposeda
[8]a
[25]a
[29]a
[10]b
[14]b
[15]b
[22]b
Technology Temperature (◦ C) Supply Voltage (V) VREF (mV) TC (ppm/◦ C) PSRR (dB)@100 Hz Line Regulation (mV/V) Supply Current (𝜇 A) Die Area (mm2 ) FOM
180 nm −20 to 108 0.95 to 1.8 609.7 44.5 −42 1.99 [email protected] V 0.0082 964
180 nm −40 to 120 1.4 to 2 650 82 −70 3.33c [email protected] Vc 0.035 159
180 nm −20 to 80 0.6 441 25 −44 30c [email protected] Vc 0.00715 158
28 nm −15 to 80 0.85 to 4.1 252 218.8 −34c 6.46c [email protected] Vc NA NA
130 nm −40 to 85 1 to 3.3 598 47 −44 1.3c 1@1 V 0.02 36
180 nm −20 to 80 1.35 to 1.8 630 14.1 −75.7@dc 0.298 [email protected] V 0.015 1365
180 nm −40 to 60 0.8 to 2 467.2 38.7 NA 7.4 [email protected] Vc 0.0033 NA
180 nm −40 to 140 0.4 210 82 −45c 0.056c [email protected] V 0.021 46665
a b c
Simulated Values. Measured Values. Calculated from given data and graph of existing literature. 9
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ature ranging from −20 to 108 ◦ C. The proposed CCMVRC exhibits a PSRR of −42 dB at 100 Hz. It has an active area of 0.0082 mm2 .
[13] J. Jiang, W. Shu, J.S. Chang, A 5.6 ppm/C temperature coefficient, 87-db psrr, sub-1-v voltage reference in 65-nm cmos exploiting the zero-temperature-coefficient point, IEEE J. Solid State Circuits 52 (3) (2017) 623–633. [14] Z.-k. Zhou, Y. Shi, C. Gou, X. Wang, G. Wu, J.-f. Feng, Z. Wang, B. Zhang, A resistorless low-power voltage reference, IEEE Trans. Circuits Syst. II: Express Briefs 63 (7) (2016) 613–617. [15] Q. Yang, P. Han, N. Mei, Z. Zhang, A 16.4 nw, sub-1 v, resistor-less voltage reference with bjt voltage divider, J. Circuits Syst. Comput. 27 (13) (2018) 1850206. [16] C. Yu, L. Siek, An area-efficient current-mode bandgap reference with intrinsic robust start-up behavior, IEEE Trans. Circuits Syst. II: Express Briefs 62 (10) (2015) 937–941. [17] A.K. Singh, P.K. Pal, M. Pattanaik, A wide temperature range voltage bandgap reference generator in 32nm cmos technology, in: 2015 Global Conference on Communication Technologies (GCCT), IEEE, 2015, pp. 696–699. [18] Q.L. Li, W. Deng, X.Y. Ma, J. Huang, A novel low line regulation voltage reference with no amplifier, J. Circuits Syst. Comput. 27 (10) (2018) 1850152. [19] K. Ueno, T. Hirose, T. Asai, Y. Amemiya, A 300 nw, 15 ppm/C, 20 ppm/v cmos voltage reference circuit consisting of subthreshold mosfets, IEEE J. Solid State Circuits 44 (7) (2009) 2047–2054. [20] H. Wang, P.P. Mercier, A 3.4-pw 0.4-v 469.3 ppm/C five-transistor current reference generator, IEEE Solid-State Circuits Lett. 1 (5) (2018) 122–125. [21] Y. Liu, C. Zhan, L. Wang, An ultralow power subthreshold cmos voltage reference without requiring resistors or bjts, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26 (1) (2018) 201–205. [22] Y. Liu, C. Zhan, L. Wang, J. Tang, G. Wang, A 0.4-v wide temperature range all-mosfet subthreshold voltage reference with 0.027/v line sensitivity, IEEE Trans. Circuits Syst. II: Express Briefs 65 (8) (2018) 969–973. [23] B. Aggarwal, M. Gupta, A.K. Gupta, A comparative study of various current mirror configurations: topologies and characteristics, Microelectron. J. 53 (2016) 134–155. [24] J. Duan, Z. Zhu, J. Deng, W. Xu, B. Wei, A novel 0.8-v 79-nw cmos-only voltage reference with- 55-db psrr@ 100 hz, IEEE Trans. Circuits Syst. II: Express Briefs 65 (7) (2018) 849–853. [25] Z. Zhu, et al., A 0.6 v 31 nw 25 ppm/C mosfet-only sub-threshold voltage reference, Microelectron. J. 66 (2017) 25–30. [26] Y. Zeng, Y. Huang, Y. Luo, H.-Z. Tan, An ultra-low-power cmos voltage reference generator based on body bias technique, Microelectron. J. 44 (12) (2013) 1145–1153. [27] Y. Wang, Z. Zhu, J. Yao, Y. Yang, A 0.45-v, 14.6-nw cmos subthreshold voltage reference with no resistors and no bjts, IEEE Trans. Circuits Syst. II: Express Briefs 62 (7) (2015) 621–625. [28] I. Lee, D. Sylvester, D. Blaauw, A subthreshold voltage reference with scalable output voltage for low-power iot systems, IEEE J. Solid State Circuits 52 (5) (2017) 1443–1449. [29] M. Mohammed, K. Abugharbieh, M. Abdelfattah, S. Kawar, Design methodology for mosfet-based voltage reference circuits implemented in 28 nm cmos technology, AEU-Int. J. Electron. Commun. 70 (5) (2016) 568–577. [30] Z. Zhu, J. Hu, Y. Wang, A 0.45 v, nano-watt 0.033 line sensitivity mosfet-only sub-threshold voltage reference with no amplifiers, IEEE Trans. Circuits Syst. I: Reg. Pap. 63 (9) (2016) 1370–1380. [31] S.S. Bethi, K.S. Lee, R. Veillette, J. Carletta, M. Willett, A temperature and process insensitive CMOS reference current generator, in: Midwest Symposium on Circuits and Systems, 2013, pp. 301–304.
Acknowledgement The authors are thankful to the ministry Of Electronics And Information Technology (Meity), Govt. of India, for grants and supports provide as special manpower development program. The Department of Electronic and Communication Engineering, MMMUT, Gorakhpur, India is acknowledged for providing the necessary infrastructure. The Department of Electronic and Communication Engineering, MN National Institute of Technology Allahabad, India is also highly acknowledged for providing the necessary tools for calculations and simulations. References [1] B. Razavi, Design of Analog CMOS Integrated Circuits, first ed., McGraw-Hill, Inc., New York, NY, USA, 2001. [2] A.K. Dubey, R.K. Nagaria, Enhanced gain low-power cmos amplifiers: a novel design approach using bulk-driven load and introduction to gacoba technique, J. Circuits Syst. Comput. 27 (13) (2018) 1850204. [3] P.K. Pal, A.K. Dubey, S.R. Kassa, R.K. Nagaria, Voltage comparison based high speed & low power domino circuit for wide fan-in gates, in: 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), IEEE, 2016, pp. 96–99. [4] A. Kumar, R. Nagaria, A new leakage-tolerant high speed comparator based domino gate for wide fan-in or logic for low power vlsi circuits, Integration 63 (2018) 174–184. [5] P.K. Pal, A.K. Singh, M. Pattanaik, Energy efficient design of direct coupled pass transistor based pulse triggered flip-flop, in: 2015 International Conference on Technological Advancements in Power and Energy (TAP Energy), IEEE, 2015, pp. 161–164. [6] X.L. Tan, P.K. Chan, U. Dasgupta, A sub-1-v 65-nm mos threshold monitoring-based voltage reference, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (10) (2015) 2317–2321. [7] C. Yongda, Z. Zhige, W. Zhen, L. Jianming, Threshold-voltage-difference-based cmos voltage reference derived from basic current bias generator with 4.3 ppm/C temperature coefficient, Electron. Lett. 50 (7) (2014) 505–507. [8] S. Yousefi, M. Jalali, A high-psrr low-power cmos voltage reference based on weighted vgs difference, AEU-Int. J. Electron. Commun. 70 (1) (2016) 50–57. [9] L. Liu, Y. Song, J. Mu, W. Guo, Z. Zhu, Y. Yang, A high accuracy cmos subthreshold voltage reference with offset cancellation and thermal compensation, Microelectron. J. 60 (2017) 102–108. [10] A. Parisi, A. Finocchiaro, G. Palmisano, An accurate 1-v threshold voltage reference for ultra-low power applications, Microelectron. J. 63 (2017) 155–159. [11] Z. Qianneng, Y. Kai, L. Jinzhao, P. Yu, L. Guoquan, L. Wei, Novel high-psrr high-order curvature-compensated bandgap voltage reference, J. China Univ. Posts Telecommun. 23 (2) (2016) 66–96. [12] P.B. Basyurt, E. Bonizzoni, D.Y. Aksin, F. Maloberti, A 0.4-v supply curvature-corrected reference generator with 84.5-ppm/C average temperature coefficient within- 40C to 130C, IEEE Trans. Circuits Syst. II: Express Briefs 64 (4) (2017) 362–366.
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