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A wafer level reliability method for short-loop processing
Microelectron. Reliab., Vol. 36, No. 11/12, pp. 1859-1862, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/96 $15.00 + .00
Pergamon Plh
S0026-2714(96)00215-6
A WAFER LEVEL RELIABILITY METHOD FOR SHORT-LOOP PROCESSING J.B. DULUC, T. ZIMMER, N. MILET, J.P. DOM IXL, URA 846-CNRS - University BORDEAUX I 351, Cours de la Liberation, F 33405 TALENCE
Abstract: This paper presents a new method to isolate process steps causing
performance spread of analogue or digital circuits. It is based on the analysis of process control (PC) parameters and can be directly applied to parametric on-wafer test. The suitability of this technology inside an automated environment is emphasised, as an aid tool in control processes stability and quality. The analysis includes a physical approach of the PC parameter combined with a correlation ratio study. This methodology which links PC parameters to process quantities, results in short-loop processing as well as enhanced yield improvement. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Spread in performance of analogue or digital circuits is largely due to inherent fluctuation in the manufacturing process. A today's standard technology consists of about twenty different process steps. For each step, process tolerances (mask alignment, temperature variations, implant dose and every changes) affect the performance fluctuation of the final device or circuit. The question arises, is there a process step, whose fluctuation causes a large performance distribution of the final device and how can it be identified. Different methods have been proposed with link model parameter variability to process fluctuation. They are based on the principal component analysis (PCA) [1,2] or factor analysis [3]. The parameters used are device model parameters. But these parameters are not directly accessible at the manufacturing level and often the models are semi-empirical, so the interpretation of the results is difficult. The proposed approach uses PC parameters expressed in physical formula and can be directly applied to parametric on-wafer test. METHODOLOGY Parameters as a function of technological data
The control of different process steps during manufacturing is realised by parametric on-wafer tests using special test structures. In a bipolar technology typical PC parameters are the transistor gain (BETA), the base-emitter voltage (VBE0) for a given bias current IE, the collector current (ICE0) for a given bias voltage VCE, the breakdown voltage of the different bipolar junctions (BVCE0, BVBE0, BVCB0, BVCS0), and the leakage substrate current (ICS0). In addition, the square resistances of the different doping layers are determined using 1859
1860
J.B. Duluc et al.
Van der Pauw structures. The PC parameters and supplementary abbreviations used in this paper are summarised in table 1. Table 1 PC parameters and technological data BETA VBE0 ICE0 BVCE0 BVBE0 BVCB0 BVCS0 ICS0 VBPIN RBPIN VEPI
transistor gain REPI VCE base-emitter voltage (IE) collector current (VCE) RCE collector-emitter breakdown voltage Nab, Wb base-emitter breakdown voltage Nde, We Nepi, Wepi collector-base breakdown voltage collector-substrate breakdown voltage Nce, Wce Hb, He leakage substrate current L base square resistance dbe base layer resistance QNA 1, QN 1 epitaxial square resistance
epitaxial layer resistance buried layer square resistance buried layer resistance base: doping density & vertical width emitter: doping density & vertical width epitaxial: doping density & vertical width buried layer: doping density & vertical width base contact opening width, emitter width emitter, base and collector length distance between base and emitter contact index concerning two different transistors
The PC parameters can be expressed as a function of technological data. For example the transistor gain BETA is given by the following formula [4]. (1)
B E T A = W~N'I~D"h W j,N ,,I,D t,~
Where D,b is the diffusion coefficient for electron in the base, Wb the base width, N,b the base doping density, Dp~ is the diffusion coefficient for holes in the emitter, We the emitter width, Nde the emitter doping density. In (1) simplifications as uniform doping profiles are assumed. The parameter BETA depends also on the emitter and base width and on the emitter and base doping density. This dependence is indicated in table 2, first row. A similar analysis can be done to relate all the other PC parameters to the technological data. The resulting expressions are achieved using the formula of semiconductor physics. The results are summarised in table 2, where the sign "x" indicates a dependence of the PC parameter (row) to the technological data (column). Table 2 PC parameter related to technological data.
BETA BVCE0 BVEB0 BVCB0 VBPIN RBPIN VEPI REPI VCE RCE VBE I CE0
Nab X X X X X X
Wb X X
Nde X X X
We X X X
X X X
Nepi Wepi
Nce
X X
X X
X X
X X
X X
X
L
He
Hb
X X X
X X X
X
X X
X X
dbe
X
X X X X
X X
Wce
X
X X
X
X
Short-loop processing
1861
Correlation study of the PC parameters With the parametric on-wafer test data, a correlation ratio study [5] is performed. The correlation ratio measures the degree of dependence of two variables regardless of the law which relates these variables. This is necessary, because the expressions relating the PC to technological parameters are not linear; they show exponential or logarithimic behaviours. The results are presented in table 3 (column 2). The strongest correlation has be obtained between the collector current ICEOQNAI and the collector current ICEOQN1 and between the breakdown voltage of the emitter-base junction BVEBOQNI and the collector current ICEOQN1. ANALYSIS Combining the theoretical process dependence of the PC parameter (table 2) with the correlation results (table 3 -column 2) permits to identify the key process variable fluctuation. The starting point is the fact that process parameter fluctuation implies PC parameter fluctuation. Let us consider the two PC parameters ICEOQNI and BVEBOQN1. The variation of BVEBOQN1 is due to a fluctuation of one or more of the process parameters Nab, Nde, We, L, He (table 2). The same consideration is valid for ICEOQNI: ICEOQN1 depends on Nab, Wb, Nde, We, Nepi, L, He, Hc and dbe. But BVEBOQN1 and ICEOQNI are strongly correlated. So the fluctuation of the two parameters has the same origin. Both, BVEBOQNI and ICEOQN1 depend on Nab, Nde, We, L, He. Which means that the variation of one or more of these process parameters will cause the final fluctuation of BVEBOQNI and ICEOQNI. The parameter ICEOQN1 depends also on Nepi, Wb, Hb and dbe. But the fluctuation of these process parameters cannot be at the origin of the variation of BVCEOQN1, because then correlation of ICEOQN1 and BVEBOQNI would be omitted. In fact, BVEBOQN1 is not related to Nepi, Wb, Hb an dbe. The second row of table 3 indicates this statement. This procedure was applied to all couples of parameters with a correlation coefficient greater than 0.95. The results are summarised in table 3. In the last row, the total number of events for each technological parameter is reported. The most influential process step is defined by the parameter which occurs most frequently.
Table 3 Results of the correlation ratio study combined with the technological dependence of the PC parameters. Regression ICEOQNAI-ICEOQNI BVEBOQNI - ICEOQN1 BETAQNI-ICEOQNI BVCEOQNI-ICEOQNI VEPI - ICEOQN1
BVEBOQNA I - BVCEOQN 1 Number of events
Ratio NePi Nab 0.997 X X 0.996 X 0.996 X 0.966 X X 0.995 X
0.955 13
X 11
Wb Nde We Wepi He L X X X X X X X X X X X X X X X X
9
X 8
X 8
5
3
3
1862
J.B. Duluc et al.
RESULTS
The procedure has been applied to forty wafers issued from one fabrication line. On the wafer were four identical sites with different test structures. On each site forty-two parameters were measured. From table 3 it can be found that for the given process the most important technological parameters is Nepi (the epitaxial layer doping density). This result is not surprising because different epitaxial doping density have been used for the wafers. This proves the validity of the presented method. The next important parameters are Nab (base doping density) and Wb (base width). So the base implantation is the critical key process step for this given technology. A better control during the base implantation will not only result in a more homogeneous distribution of the PC parameters, but also in a higher quality of the whole process. CONCLUSION A method has been presented, which allows determination of the critical process step causing the fluctuation of the circuit performance over one wafer or one lot. It is based on parametric on-wafer test data. This technique can be included in an automated environment, so that results are directly available during manufacturing. A computer program has been developed, which can easily be adapted to different technologies. This permits to control immediately the fluctuations of the process parameters. The benefits are enhanced yield improvement and shortloop processing. References: 1 A. Power, An approach for relating model parameter variabilities to process fluctuations, Proc. IEEE Int Conference on Microelectroni¢ Test Structures, Vol 6, March, 63-68 (1993) 2 T. Gueiting, H. Khalzar, The use of parametric test data for the prediction of circuit performance, Proceeding of the 2nd European liP IC-CAP users Meeting, Colmar, France, 716 (1994) 3 F.K. Iravani, M. Habu, E. Khalily, Statistical Modeling tools, Methods and application for Integrated Circuit Manufacturability, Proc. of the IEEE International Conference on Microelectronics Test Structures, Nava, Japan, 203-207 (1995) 4 D.J. Roulston, Bipolar Semiconductor Devices, McGraw Hill, New York, (1990) 5 P. Dagnelie, Thdorie et mdthodes statistiques vol.l, Les Presses Agronomiques de Gembloux, ASBL (1973)
Pergamon Plh
S0026-2714(96)00215-6
A WAFER LEVEL RELIABILITY METHOD FOR SHORT-LOOP PROCESSING J.B. DULUC, T. ZIMMER, N. MILET, J.P. DOM IXL, URA 846-CNRS - University BORDEAUX I 351, Cours de la Liberation, F 33405 TALENCE
Abstract: This paper presents a new method to isolate process steps causing
performance spread of analogue or digital circuits. It is based on the analysis of process control (PC) parameters and can be directly applied to parametric on-wafer test. The suitability of this technology inside an automated environment is emphasised, as an aid tool in control processes stability and quality. The analysis includes a physical approach of the PC parameter combined with a correlation ratio study. This methodology which links PC parameters to process quantities, results in short-loop processing as well as enhanced yield improvement. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Spread in performance of analogue or digital circuits is largely due to inherent fluctuation in the manufacturing process. A today's standard technology consists of about twenty different process steps. For each step, process tolerances (mask alignment, temperature variations, implant dose and every changes) affect the performance fluctuation of the final device or circuit. The question arises, is there a process step, whose fluctuation causes a large performance distribution of the final device and how can it be identified. Different methods have been proposed with link model parameter variability to process fluctuation. They are based on the principal component analysis (PCA) [1,2] or factor analysis [3]. The parameters used are device model parameters. But these parameters are not directly accessible at the manufacturing level and often the models are semi-empirical, so the interpretation of the results is difficult. The proposed approach uses PC parameters expressed in physical formula and can be directly applied to parametric on-wafer test. METHODOLOGY Parameters as a function of technological data
The control of different process steps during manufacturing is realised by parametric on-wafer tests using special test structures. In a bipolar technology typical PC parameters are the transistor gain (BETA), the base-emitter voltage (VBE0) for a given bias current IE, the collector current (ICE0) for a given bias voltage VCE, the breakdown voltage of the different bipolar junctions (BVCE0, BVBE0, BVCB0, BVCS0), and the leakage substrate current (ICS0). In addition, the square resistances of the different doping layers are determined using 1859
1860
J.B. Duluc et al.
Van der Pauw structures. The PC parameters and supplementary abbreviations used in this paper are summarised in table 1. Table 1 PC parameters and technological data BETA VBE0 ICE0 BVCE0 BVBE0 BVCB0 BVCS0 ICS0 VBPIN RBPIN VEPI
transistor gain REPI VCE base-emitter voltage (IE) collector current (VCE) RCE collector-emitter breakdown voltage Nab, Wb base-emitter breakdown voltage Nde, We Nepi, Wepi collector-base breakdown voltage collector-substrate breakdown voltage Nce, Wce Hb, He leakage substrate current L base square resistance dbe base layer resistance QNA 1, QN 1 epitaxial square resistance
epitaxial layer resistance buried layer square resistance buried layer resistance base: doping density & vertical width emitter: doping density & vertical width epitaxial: doping density & vertical width buried layer: doping density & vertical width base contact opening width, emitter width emitter, base and collector length distance between base and emitter contact index concerning two different transistors
The PC parameters can be expressed as a function of technological data. For example the transistor gain BETA is given by the following formula [4]. (1)
B E T A = W~N'I~D"h W j,N ,,I,D t,~
Where D,b is the diffusion coefficient for electron in the base, Wb the base width, N,b the base doping density, Dp~ is the diffusion coefficient for holes in the emitter, We the emitter width, Nde the emitter doping density. In (1) simplifications as uniform doping profiles are assumed. The parameter BETA depends also on the emitter and base width and on the emitter and base doping density. This dependence is indicated in table 2, first row. A similar analysis can be done to relate all the other PC parameters to the technological data. The resulting expressions are achieved using the formula of semiconductor physics. The results are summarised in table 2, where the sign "x" indicates a dependence of the PC parameter (row) to the technological data (column). Table 2 PC parameter related to technological data.
BETA BVCE0 BVEB0 BVCB0 VBPIN RBPIN VEPI REPI VCE RCE VBE I CE0
Nab X X X X X X
Wb X X
Nde X X X
We X X X
X X X
Nepi Wepi
Nce
X X
X X
X X
X X
X X
X
L
He
Hb
X X X
X X X
X
X X
X X
dbe
X
X X X X
X X
Wce
X
X X
X
X
Short-loop processing
1861
Correlation study of the PC parameters With the parametric on-wafer test data, a correlation ratio study [5] is performed. The correlation ratio measures the degree of dependence of two variables regardless of the law which relates these variables. This is necessary, because the expressions relating the PC to technological parameters are not linear; they show exponential or logarithimic behaviours. The results are presented in table 3 (column 2). The strongest correlation has be obtained between the collector current ICEOQNAI and the collector current ICEOQN1 and between the breakdown voltage of the emitter-base junction BVEBOQNI and the collector current ICEOQN1. ANALYSIS Combining the theoretical process dependence of the PC parameter (table 2) with the correlation results (table 3 -column 2) permits to identify the key process variable fluctuation. The starting point is the fact that process parameter fluctuation implies PC parameter fluctuation. Let us consider the two PC parameters ICEOQNI and BVEBOQN1. The variation of BVEBOQN1 is due to a fluctuation of one or more of the process parameters Nab, Nde, We, L, He (table 2). The same consideration is valid for ICEOQNI: ICEOQN1 depends on Nab, Wb, Nde, We, Nepi, L, He, Hc and dbe. But BVEBOQN1 and ICEOQNI are strongly correlated. So the fluctuation of the two parameters has the same origin. Both, BVEBOQNI and ICEOQN1 depend on Nab, Nde, We, L, He. Which means that the variation of one or more of these process parameters will cause the final fluctuation of BVEBOQNI and ICEOQNI. The parameter ICEOQN1 depends also on Nepi, Wb, Hb and dbe. But the fluctuation of these process parameters cannot be at the origin of the variation of BVCEOQN1, because then correlation of ICEOQN1 and BVEBOQNI would be omitted. In fact, BVEBOQN1 is not related to Nepi, Wb, Hb an dbe. The second row of table 3 indicates this statement. This procedure was applied to all couples of parameters with a correlation coefficient greater than 0.95. The results are summarised in table 3. In the last row, the total number of events for each technological parameter is reported. The most influential process step is defined by the parameter which occurs most frequently.
Table 3 Results of the correlation ratio study combined with the technological dependence of the PC parameters. Regression ICEOQNAI-ICEOQNI BVEBOQNI - ICEOQN1 BETAQNI-ICEOQNI BVCEOQNI-ICEOQNI VEPI - ICEOQN1
BVEBOQNA I - BVCEOQN 1 Number of events
Ratio NePi Nab 0.997 X X 0.996 X 0.996 X 0.966 X X 0.995 X
0.955 13
X 11
Wb Nde We Wepi He L X X X X X X X X X X X X X X X X
9
X 8
X 8
5
3
3
1862
J.B. Duluc et al.
RESULTS
The procedure has been applied to forty wafers issued from one fabrication line. On the wafer were four identical sites with different test structures. On each site forty-two parameters were measured. From table 3 it can be found that for the given process the most important technological parameters is Nepi (the epitaxial layer doping density). This result is not surprising because different epitaxial doping density have been used for the wafers. This proves the validity of the presented method. The next important parameters are Nab (base doping density) and Wb (base width). So the base implantation is the critical key process step for this given technology. A better control during the base implantation will not only result in a more homogeneous distribution of the PC parameters, but also in a higher quality of the whole process. CONCLUSION A method has been presented, which allows determination of the critical process step causing the fluctuation of the circuit performance over one wafer or one lot. It is based on parametric on-wafer test data. This technique can be included in an automated environment, so that results are directly available during manufacturing. A computer program has been developed, which can easily be adapted to different technologies. This permits to control immediately the fluctuations of the process parameters. The benefits are enhanced yield improvement and shortloop processing. References: 1 A. Power, An approach for relating model parameter variabilities to process fluctuations, Proc. IEEE Int Conference on Microelectroni¢ Test Structures, Vol 6, March, 63-68 (1993) 2 T. Gueiting, H. Khalzar, The use of parametric test data for the prediction of circuit performance, Proceeding of the 2nd European liP IC-CAP users Meeting, Colmar, France, 716 (1994) 3 F.K. Iravani, M. Habu, E. Khalily, Statistical Modeling tools, Methods and application for Integrated Circuit Manufacturability, Proc. of the IEEE International Conference on Microelectronics Test Structures, Nava, Japan, 203-207 (1995) 4 D.J. Roulston, Bipolar Semiconductor Devices, McGraw Hill, New York, (1990) 5 P. Dagnelie, Thdorie et mdthodes statistiques vol.l, Les Presses Agronomiques de Gembloux, ASBL (1973)