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An evaluation of fast wafer level test methods for interconnect reliability control
Microelectronics Reliability 39 (1999) 1707±1714
www.elsevier.com/locate/microrel
An evaluation of fast wafer level test methods for interconnect reliability control S. Foley a,*, J. Molyneaux b, A. Mathewson a a
NMRC, University College Cork, Lee Maltings, Prospect Row, Cork, Ireland b Analog Devices, Raheen Industrial Estate, Limerick, Ireland Received 30 November 1998
Abstract A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four dierent test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction IC manufacturers are constantly searching for fast Wafer Level Reliability (WLR) and Statistical Process/ Reliability Control (SP/RC) techniques for the characterization of electromigration and other failure phenomena in their eorts to build in reliability [1,2]. The advantages of fast WLR test techniques over traditional Median Time to Failure (MTF) testing are obvious: faster time-to-market, reduced test expense, reduced product costs and increased quality control. A number of these techniques have been developed but none have gained acceptance as complete replacements for MTF testing [3]. These techniques have been developed with speed in mind. Most often, this has resulted in ``overstressing'' of the metallization where highly accelerated stress conditions are used and the failure mechanisms are changed from those present in real life
* Corresponding author. Tel.: +353 21 904382; fax: +353 21 270271. E-mail address: [email protected] (S. Foley).
applications. Lifetime predictions based on results from these techniques are thus meaningless. This does not, however, mean that these techniques are entirely without merit Ð they are commonly used by IC manufacturers to predict and control the quality and reliability of the metallization process over very short test times. The aim of this work has been to evaluate the absolute and relative abilities of three popular fast WLR test techniques used in conjunction with associated test structure designs to detect changes in metallization quality and reliability over very short test times. In this way the wisdom of using these techniques for this purpose can be established. 2. Experimental 2.1. Test methods/test structures The three techniques which were evaluated were: Standard Wafer Level Electromigration Accelerated Test (SWEAT) [4], Breakdown Energy of Metal (BEM) [5] and Isothermal [6]. These techniques were
0026-2714/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 9 ) 0 0 1 7 1 - 7
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S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
Fig. 1. SWEAT and NIST type electromigration test structures.
evaluated on wafers taken from three production lots. Four dierent test structure types were also evaluated in conjunction with the three test types. These were: . M1 FLAT Ð an 800 mm long, 2 mm wide, ¯at, NIST-like [7] structure Ð see Fig. 1 . M1 TOPOGRAPHY Ð an 800 mm long, 2 mm wide, NIST-like structure over topography . SWEAT FLAT Ð a 1600 mm long, 2 mm wide (narrow regions) and 20 mm wide (wide regions) JEDEC-like [8] structure Ð see Fig. 1 . SWEAT TOPOGRAPHY Ð a 1600 mm long, 2 mm wide (narrow regions) and 20 mm wide (wide regions) JEDEC-like structure with topography under the narrow regions. The test structures were at the Metal 1 level which consisted of a 0.45 mm thick layer of Al±Si±Cu with a 0.14 mm thick Ti/TiN barrier layer and a 25 nm thick TiN anti-re¯ective coating. These layers were sputtered and patterned by dry-etching. Prior to the wafer level testing, Temperature Coecient of Resistance (TCR) and Temperature vs Power (TVP) measurements were performed on each of the test structure types at a number of sites across each of the wafers. Initial tests were performed on setup wafers to derive a matrix of stress conditions for the SWEAT, BEM and Isothermal test methods that yielded approximate test duration's of 30 s and 2 min for each of the test structure types. The results of the TCR and TVP measurements along with the appropriate stress conditions were used as inputs to the various
test algorithms for the wafer level testing on production lots A, B and C. The purpose of this work was to evaluate the relative abilities of the dierent test method/test structure combinations to detect changes in the electromigration performance of the metallization over very short test times. To achieve this, intentional changes had to be made to the standard samples Ð changes that are known to in¯uence the electromigration performance of the metallization. The two intentional changes which were used in this evaluation are as follows: 2.2. Microstructure change Ð precipitates One wafer from each of production lots A and B was baked at 2208C for 200 h. Temperature ageing of this nature is known to cause the growth of large Cu precipitates within the test lines [9]. These precipitates lead to electromigration ¯ux divergences and reduced metallization reliability. The purpose of the bake was thus to alter the reliability of the metallization and to see if wafer level test methods could successfully detect the change in reliability over very short test times. As described below, package level samples from the same lots were also subjected to the same bake for comparison purposes. 2.3. Process change Ð omission of passivation In production lot C the deposition of the ®nal passivation layer was intentionally omitted from the processing sequence. It is reasonable to expect the omission
S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
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Fig. 2. Lognormal failure distributions from package level MTF tests on baked and unbaked M1 FLAT structures from Lot A.
of the relatively thick passivation layer to have an impact on both the microstructure and stress of the Metal 1 ®lm and thus to alter the reliability of the metallization. The purpose of the omission was thus to evaluate the abilities of the various techniques to detect signi®cant process changes or errors that alter the metallization reliability. 2.4. Long-term tests for comparison For comparison purposes, traditional MTF tests were also performed on baked and unbaked packaged M1 FLAT and M1 TOPOGRAPHY structures taken from production lots A and B. These MTF tests were at much less severe stress conditions than the wafer level tests and had durations of the order of 100 h.
Table 1 Summary of package level MTF results
3. Results 3.1. Package level (MTF) results The lognormal failure distributions for packaged M1 FLAT structures (baked and unbaked) are illustrated in Fig. 2. As can be seen the MTF of the metallization decreases if baked. All of the MTF results are summarized in Table 1. As expected, in all cases the bake caused a reduction in the reliability of the metallization. The reduction in t50 values is observed for both production lots and for each of the four test structure types. Given this knowledge, the capabilities of the various wafer level test methods in conjunction with the dierent test structure designs to detect this reduction in reliability, were then assessed over very short test times. 3.2. Wafer level results
Pre-baked (@2208C for 200 h)
Lot
Structure
t50 (h)
No Yes No Yes No Yes No Yes
A A A A B B B B
M1 M1 M1 M1 M1 M1 M1 M1
144.65 103.74 96.22 84.19 159.65 115.23 113.03 89.19
Flat Flat Topog Topog Flat Flat Topog Topog
On each wafer (baked and unbaked) of each of the two lots, ®ve randomly selected test structures of each type were stressed using each of the three test methods and for each of two sets of stress conditions. The lifetimes obtained were grouped and plotted in lognormal distributions. Least squares line®ts were used to obtain estimates of the times to 50% cumulative failure (t50) and standard deviation. For example, the results obtained from Isothermal tests on SWEAT FLAT structures are illustrated in Fig. 3.
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S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
Fig. 3. Lognormal failure distributions with Least Squares estimates of distribution parameters from results of Isothermal testing on SWEAT FLAT test structures.
The wafer level results for production lots A and B are summarized in Table 2. This table gives values for the ratios of the baked and unbaked t50s for all test methods. Values for the ratios of t50s obtained using
the Isothermal test method on two unbaked wafers from the same production lots are also given. The least squares, standard deviation values varied randomly from test to test and it can be emphasised
Table 2 Summary of wafer level test results Lot B
Sweat testing of M1 Flat structures Sweat testing of M1 Topo structures Sweat testing of Sweat Flat structures Sweat testing of Sweat Topo structures BEM testing of M1 Flat structures BEM testing of M1 Topo structures BEM testing of Sweat Flat structures BEM testing of Sweat Topo structures Isothermal testing of M1 Flat structures Isothermal testing of M1 Topo structures Isothermal testing of Sweat Flat structures Isothermal testing of Sweat Topo structures a
NOTE: db
t50 baked t50 unbakedR EF
and du
t50 unbaked t50 unbakedR EF .
dba db db db db db db db db du db du db du db du
Lot A
30 s
2 min
30 s
2 min
1.57 2.29 1.58 1.35 1.07 1.31 1.04 1.06 0.59 0.70 2.03 1.75 0.66 0.96 0.62 1.03
1.25 1.12 1.40 0.98 0.90 1.27 0.83 1.26 0.96 0.82 1.45 1.37 0.86 1.01 0.89 0.99
0.98 1.80 1.51 1.22 1.19 0.93 1.05 1.08 1.19 1.03 2.40 1.96 0.64 0.94 0.55 1.10
1.14 1.02 1.18 0.95 1.09 0.75 0.72 1.03 0.73 0.77 1.10 0.91 0.88 1.01 0.88 0.95
S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
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Table 3 Reduction in t50 for unpassivated samples Lot A
Isothermal testing of Sweat Flat structures Isothermal testing of Sweat Topo structures
t50 t50
Lot B
Lot C (Unpassivated)
30 s
2 min
30 s
2 min
30 s
2 min
45.2 38.1
142.2 158.0
39.6 43.0
141.4 143.0
19.1 20.18
120.0 112.4
that data spread has no in¯uence on the results listed in Table 2. As can be seen from Table 2, the Isothermal test method when used in conjunction with the SWEAT based test structure designs is the only test method/test structure combination that gives correct and repeatable detection of the metallization reliability (db < 1). As well as successfully detecting the reduction in reliability for the baked wafer, a suitable test method/test structure combination should not detect any change in reliability between two unbaked wafers from the same lot. As can be seen from the ratios of unbaked t50s in Table 2, only the Isothermal/SWEAT-type test structure combination does this (du values close to 1). Wafer level tests identical to those used on production lots A and B were also performed on samples from production lot C (unpassivated). The t50 values from each of the three production lots (unbaked samples only), over both test durations and for the Isothermal test method combined with the SWEATbased test structures are summarized in Table 3.
Again, in this case, variations in the extracted standard deviations had no in¯uence on the lifetime ratio values listed in Table 3. As can be seen, the t50 values obtained from Isothermal tests on SWEAT-based structures for the unpassivated samples of lot C are signi®cantly lower than those of lots A and B which were fully processed. Isothermal/NIST, SWEAT and BEM all failed to detect these consistent reductions in t50 Ð and these results are omitted from the table for clarity. In this case, again, it is obvious that the Isothermal test method combined with SWEAT-type test structures is the only successful combination to use for the detection of changes in metallization reliability over such short test times.
4. Analysis The success of the Isothermal/SWEAT-type test structure combination compared to the Isothermal/ NIST combination and the SWEAT and BEM
Fig. 4. Calculated test structure temperatures at the beginning of CTTF control during SWEAT tests.
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S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
Fig. 5. Calculated test structure temperatures just prior to failure during SWEAT tests.
methods can be attributed to dierences in the magnitude and control of the test structure current and temperature during the various test methods. Temperature control is an important concern in the electromigration testing of aluminium copper alloy metallizations. The solubility of copper changes with temperature and a precipitation/dissolution process occurs with variations in metallization temperature. In theory it is important that this is taken into account when performing electromigration testing at temperatures that are much higher than those occurring at product use conditions. In practice, it is very dicult to achieve a valid compromise between suciently short test duration and realistic microstructure stabilization. For example, with the widely used Al±0.5wt%Cu alloy, the critical temperatures are as follows: (i) 2208C Ð the temperature limit, below which less than 20% of the copper concentration is in solution; (ii) 3168C Ð the temperature at which all of the copper goes into solution, (iii) 3508C Ð bulk diusion begins to dominate over grain boundary diusion and (iv) 6608C Ð the melting point of aluminium [10]. An examination of the control methodologies employed during the three test methods discussed above and the resulting variations in calculated test structure temperatures gives further clari®cation of this point. (Note: these are not measured temperatures but are calculated values, using the measured resistance of the structure and the TCR of the metallization Ð these calculated values are indicative of the levels of stress in the structure and the degree of damage that the structure has sustained.) The goal of the SWEAT test is to control the
applied current by keeping the calculated time-to-failure (CTTF ) constant. CTTF is related to the temperature, T, and applied current density, j, through Black's Eq. [11]: CTTF
A Ea : exp jn kT
1
The problem with SWEAT testing is that no attempt is made to control either of the independent variables, temperature or current. Only the dependent variable, time-to-failure, is controlled. A `target time-to-failure' is set at the beginning of the test and when this target time is short, as is required for reliability monitoring in a production line environment, the metallization temperature can easily rise close to the melting point of aluminium. This is illustrated in Figs. 4 and 5. Fig. 4 shows the test structure calculated temperatures during SWEAT testing at the beginning of the CTTF control. While the calculated temperatures for the NIST-type structures are high (exceeding the solubility limit of 3168C and in some cases the bulk diusion limit of 3508C), the calculated temperatures for the SWEAT-type structures are not extreme. However, in attempting to control the CTTF, the algorithm varies the currents applied to the test structure. The Joule heating and metallization temperature are thus variable during test and the actual structure temperatures just prior to failure can become very high. This is illustrated in Fig. 5 where all of the calculated temperatures exceed the solubility and diusion changeover limits and some approach the melting point of alu-
S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
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Fig. 6. Calculated test structure temperatures just prior to failure during BEM tests.
minium. With such poor temperature control and excessive metallization temperatures it is easy to understand why the SWEAT test was not successful in detecting either the microstructure or process changes over these short test times. The BEM algorithm that was used in this work was dierent to the classical BEM method [5]. In this work
the current was varied such that the temperature was ramped in constant temperature steps. Temperature is the dominant independent variable in Black's equation and this attempt to control it is an improvement over the original BEM method where current was ramped in constant steps. The calculated structure temperatures, observed just prior to failure during the BEM
Fig. 7. Calculated test structure temperatures during Isothermal tests.
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S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
tests, are illustrated in Fig. 6. The calculated temperatures observed during BEM tests on SWEAT-type structures are not extreme. However, despite controlling the dominant independent variable in Black's equation and the relatively low test temperatures observed just prior to failure, ramping the temperature until failure inadvertently causes the build-up of timevarying thermal gradients in the test structure. These gradients lead to locations of excessive temperatures where thermal runaway and fusing occurs and for this reason the actual fail times observed bear little relation to the real electromigration performance of the metallization. The goal of the Isothermal algorithm is to vary the current applied to the structure and the Joule heating in the structure in order to maintain a constant structure temperature throughout the test. The obvious advantage of this method over either SWEAT or BEM is that an attempt is made to directly control the temperature and for this reason the test is less likely to susceptible to thermal gradients and thermal runaway failures. The calculated structure temperatures that were necessary to achieve the short test times in this work are illustrated in Fig. 7. While the calculated temperatures for the NIST-type structures are high, those of the SWEAT-type structures are within a reasonable regime (especially for the 2 min test). These low temperatures coupled with the absence of harmful thermal gradients are good reasons why the Isothermal/SWEAT structure combination was better at detecting the imposed changes in microstructure and macrostructure than any of the other test method/test structure combinations evaluated in this study. 5. Conclusions It can be concluded that of the three test methods
and four test structure designs evaluated, the Isothermal test method used in conjunction with either of the SWEAT-based test structure designs is the only safe combination for detecting a change in the metallization reliability when one actually exists and not detecting a change when one does not. Its success can be attributed to the relatively low temperatures necessary and the method of temperature control employed. This test method/test structure combination can thus be recommended for use as fast, in-line testing to detect and control the reliability of metallization.
References [1] Molyneaux J, Prendergast J, Finucane N, Houlihan S, Proc. IEEE Integrated Reliability Workshop, 1996. p. 16. [2] Prendergast J, Murphy E, Stephenson M. Intl Journal of Quality and Reliability Engineering Volume 1997;13(5). [3] Lloyd JR. Mat Res Soc Symp Proc 1992;260:735±44. [4] Root BJ, Turner T, Proc. 23rd Ann. Reliab. Phys. Symp. IEEE, 1985. p. 100. [5] Hong CC, Crook DL, Proc. 23rd Ann. Reliab. Phys. Symp. IEEE, 1985. p. 108. [6] Pierce DG, Brusius PG. IEEE Electron Device Letters 1993;14(6). [7] ASTM Standard F1259-89,.Standard guide for design of ¯at, straight-line test structures for detecting metallization open-circuit or resistance-increase failure due to electromigration. Annual Book of ASTM Standards, vol. 10.04, 1989. [8] JEDEC Solid State Products Engineering Council. A guide for the design of straight line SWEAT test structures. JC-14.2-93-116, 1993. [9] Foley S, Martin D, Mathewson A. Proc. IEEE Integrated Reliability Workshop 1996;110±5. [10] Mondolfo LF. Aluminium alloys: structure and properties. London: Butterworths, 1976. [11] Black JR. 5th Annual Proc. Reliability Physics Symp, 1967. p. 148±59.
www.elsevier.com/locate/microrel
An evaluation of fast wafer level test methods for interconnect reliability control S. Foley a,*, J. Molyneaux b, A. Mathewson a a
NMRC, University College Cork, Lee Maltings, Prospect Row, Cork, Ireland b Analog Devices, Raheen Industrial Estate, Limerick, Ireland Received 30 November 1998
Abstract A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four dierent test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times. # 1999 Elsevier Science Ltd. All rights reserved.
1. Introduction IC manufacturers are constantly searching for fast Wafer Level Reliability (WLR) and Statistical Process/ Reliability Control (SP/RC) techniques for the characterization of electromigration and other failure phenomena in their eorts to build in reliability [1,2]. The advantages of fast WLR test techniques over traditional Median Time to Failure (MTF) testing are obvious: faster time-to-market, reduced test expense, reduced product costs and increased quality control. A number of these techniques have been developed but none have gained acceptance as complete replacements for MTF testing [3]. These techniques have been developed with speed in mind. Most often, this has resulted in ``overstressing'' of the metallization where highly accelerated stress conditions are used and the failure mechanisms are changed from those present in real life
* Corresponding author. Tel.: +353 21 904382; fax: +353 21 270271. E-mail address: [email protected] (S. Foley).
applications. Lifetime predictions based on results from these techniques are thus meaningless. This does not, however, mean that these techniques are entirely without merit Ð they are commonly used by IC manufacturers to predict and control the quality and reliability of the metallization process over very short test times. The aim of this work has been to evaluate the absolute and relative abilities of three popular fast WLR test techniques used in conjunction with associated test structure designs to detect changes in metallization quality and reliability over very short test times. In this way the wisdom of using these techniques for this purpose can be established. 2. Experimental 2.1. Test methods/test structures The three techniques which were evaluated were: Standard Wafer Level Electromigration Accelerated Test (SWEAT) [4], Breakdown Energy of Metal (BEM) [5] and Isothermal [6]. These techniques were
0026-2714/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 9 ) 0 0 1 7 1 - 7
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S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
Fig. 1. SWEAT and NIST type electromigration test structures.
evaluated on wafers taken from three production lots. Four dierent test structure types were also evaluated in conjunction with the three test types. These were: . M1 FLAT Ð an 800 mm long, 2 mm wide, ¯at, NIST-like [7] structure Ð see Fig. 1 . M1 TOPOGRAPHY Ð an 800 mm long, 2 mm wide, NIST-like structure over topography . SWEAT FLAT Ð a 1600 mm long, 2 mm wide (narrow regions) and 20 mm wide (wide regions) JEDEC-like [8] structure Ð see Fig. 1 . SWEAT TOPOGRAPHY Ð a 1600 mm long, 2 mm wide (narrow regions) and 20 mm wide (wide regions) JEDEC-like structure with topography under the narrow regions. The test structures were at the Metal 1 level which consisted of a 0.45 mm thick layer of Al±Si±Cu with a 0.14 mm thick Ti/TiN barrier layer and a 25 nm thick TiN anti-re¯ective coating. These layers were sputtered and patterned by dry-etching. Prior to the wafer level testing, Temperature Coecient of Resistance (TCR) and Temperature vs Power (TVP) measurements were performed on each of the test structure types at a number of sites across each of the wafers. Initial tests were performed on setup wafers to derive a matrix of stress conditions for the SWEAT, BEM and Isothermal test methods that yielded approximate test duration's of 30 s and 2 min for each of the test structure types. The results of the TCR and TVP measurements along with the appropriate stress conditions were used as inputs to the various
test algorithms for the wafer level testing on production lots A, B and C. The purpose of this work was to evaluate the relative abilities of the dierent test method/test structure combinations to detect changes in the electromigration performance of the metallization over very short test times. To achieve this, intentional changes had to be made to the standard samples Ð changes that are known to in¯uence the electromigration performance of the metallization. The two intentional changes which were used in this evaluation are as follows: 2.2. Microstructure change Ð precipitates One wafer from each of production lots A and B was baked at 2208C for 200 h. Temperature ageing of this nature is known to cause the growth of large Cu precipitates within the test lines [9]. These precipitates lead to electromigration ¯ux divergences and reduced metallization reliability. The purpose of the bake was thus to alter the reliability of the metallization and to see if wafer level test methods could successfully detect the change in reliability over very short test times. As described below, package level samples from the same lots were also subjected to the same bake for comparison purposes. 2.3. Process change Ð omission of passivation In production lot C the deposition of the ®nal passivation layer was intentionally omitted from the processing sequence. It is reasonable to expect the omission
S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
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Fig. 2. Lognormal failure distributions from package level MTF tests on baked and unbaked M1 FLAT structures from Lot A.
of the relatively thick passivation layer to have an impact on both the microstructure and stress of the Metal 1 ®lm and thus to alter the reliability of the metallization. The purpose of the omission was thus to evaluate the abilities of the various techniques to detect signi®cant process changes or errors that alter the metallization reliability. 2.4. Long-term tests for comparison For comparison purposes, traditional MTF tests were also performed on baked and unbaked packaged M1 FLAT and M1 TOPOGRAPHY structures taken from production lots A and B. These MTF tests were at much less severe stress conditions than the wafer level tests and had durations of the order of 100 h.
Table 1 Summary of package level MTF results
3. Results 3.1. Package level (MTF) results The lognormal failure distributions for packaged M1 FLAT structures (baked and unbaked) are illustrated in Fig. 2. As can be seen the MTF of the metallization decreases if baked. All of the MTF results are summarized in Table 1. As expected, in all cases the bake caused a reduction in the reliability of the metallization. The reduction in t50 values is observed for both production lots and for each of the four test structure types. Given this knowledge, the capabilities of the various wafer level test methods in conjunction with the dierent test structure designs to detect this reduction in reliability, were then assessed over very short test times. 3.2. Wafer level results
Pre-baked (@2208C for 200 h)
Lot
Structure
t50 (h)
No Yes No Yes No Yes No Yes
A A A A B B B B
M1 M1 M1 M1 M1 M1 M1 M1
144.65 103.74 96.22 84.19 159.65 115.23 113.03 89.19
Flat Flat Topog Topog Flat Flat Topog Topog
On each wafer (baked and unbaked) of each of the two lots, ®ve randomly selected test structures of each type were stressed using each of the three test methods and for each of two sets of stress conditions. The lifetimes obtained were grouped and plotted in lognormal distributions. Least squares line®ts were used to obtain estimates of the times to 50% cumulative failure (t50) and standard deviation. For example, the results obtained from Isothermal tests on SWEAT FLAT structures are illustrated in Fig. 3.
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Fig. 3. Lognormal failure distributions with Least Squares estimates of distribution parameters from results of Isothermal testing on SWEAT FLAT test structures.
The wafer level results for production lots A and B are summarized in Table 2. This table gives values for the ratios of the baked and unbaked t50s for all test methods. Values for the ratios of t50s obtained using
the Isothermal test method on two unbaked wafers from the same production lots are also given. The least squares, standard deviation values varied randomly from test to test and it can be emphasised
Table 2 Summary of wafer level test results Lot B
Sweat testing of M1 Flat structures Sweat testing of M1 Topo structures Sweat testing of Sweat Flat structures Sweat testing of Sweat Topo structures BEM testing of M1 Flat structures BEM testing of M1 Topo structures BEM testing of Sweat Flat structures BEM testing of Sweat Topo structures Isothermal testing of M1 Flat structures Isothermal testing of M1 Topo structures Isothermal testing of Sweat Flat structures Isothermal testing of Sweat Topo structures a
NOTE: db
t50 baked t50 unbakedR EF
and du
t50 unbaked t50 unbakedR EF .
dba db db db db db db db db du db du db du db du
Lot A
30 s
2 min
30 s
2 min
1.57 2.29 1.58 1.35 1.07 1.31 1.04 1.06 0.59 0.70 2.03 1.75 0.66 0.96 0.62 1.03
1.25 1.12 1.40 0.98 0.90 1.27 0.83 1.26 0.96 0.82 1.45 1.37 0.86 1.01 0.89 0.99
0.98 1.80 1.51 1.22 1.19 0.93 1.05 1.08 1.19 1.03 2.40 1.96 0.64 0.94 0.55 1.10
1.14 1.02 1.18 0.95 1.09 0.75 0.72 1.03 0.73 0.77 1.10 0.91 0.88 1.01 0.88 0.95
S. Foley et al. / Microelectronics Reliability 39 (1999) 1707±1714
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Table 3 Reduction in t50 for unpassivated samples Lot A
Isothermal testing of Sweat Flat structures Isothermal testing of Sweat Topo structures
t50 t50
Lot B
Lot C (Unpassivated)
30 s
2 min
30 s
2 min
30 s
2 min
45.2 38.1
142.2 158.0
39.6 43.0
141.4 143.0
19.1 20.18
120.0 112.4
that data spread has no in¯uence on the results listed in Table 2. As can be seen from Table 2, the Isothermal test method when used in conjunction with the SWEAT based test structure designs is the only test method/test structure combination that gives correct and repeatable detection of the metallization reliability (db < 1). As well as successfully detecting the reduction in reliability for the baked wafer, a suitable test method/test structure combination should not detect any change in reliability between two unbaked wafers from the same lot. As can be seen from the ratios of unbaked t50s in Table 2, only the Isothermal/SWEAT-type test structure combination does this (du values close to 1). Wafer level tests identical to those used on production lots A and B were also performed on samples from production lot C (unpassivated). The t50 values from each of the three production lots (unbaked samples only), over both test durations and for the Isothermal test method combined with the SWEATbased test structures are summarized in Table 3.
Again, in this case, variations in the extracted standard deviations had no in¯uence on the lifetime ratio values listed in Table 3. As can be seen, the t50 values obtained from Isothermal tests on SWEAT-based structures for the unpassivated samples of lot C are signi®cantly lower than those of lots A and B which were fully processed. Isothermal/NIST, SWEAT and BEM all failed to detect these consistent reductions in t50 Ð and these results are omitted from the table for clarity. In this case, again, it is obvious that the Isothermal test method combined with SWEAT-type test structures is the only successful combination to use for the detection of changes in metallization reliability over such short test times.
4. Analysis The success of the Isothermal/SWEAT-type test structure combination compared to the Isothermal/ NIST combination and the SWEAT and BEM
Fig. 4. Calculated test structure temperatures at the beginning of CTTF control during SWEAT tests.
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Fig. 5. Calculated test structure temperatures just prior to failure during SWEAT tests.
methods can be attributed to dierences in the magnitude and control of the test structure current and temperature during the various test methods. Temperature control is an important concern in the electromigration testing of aluminium copper alloy metallizations. The solubility of copper changes with temperature and a precipitation/dissolution process occurs with variations in metallization temperature. In theory it is important that this is taken into account when performing electromigration testing at temperatures that are much higher than those occurring at product use conditions. In practice, it is very dicult to achieve a valid compromise between suciently short test duration and realistic microstructure stabilization. For example, with the widely used Al±0.5wt%Cu alloy, the critical temperatures are as follows: (i) 2208C Ð the temperature limit, below which less than 20% of the copper concentration is in solution; (ii) 3168C Ð the temperature at which all of the copper goes into solution, (iii) 3508C Ð bulk diusion begins to dominate over grain boundary diusion and (iv) 6608C Ð the melting point of aluminium [10]. An examination of the control methodologies employed during the three test methods discussed above and the resulting variations in calculated test structure temperatures gives further clari®cation of this point. (Note: these are not measured temperatures but are calculated values, using the measured resistance of the structure and the TCR of the metallization Ð these calculated values are indicative of the levels of stress in the structure and the degree of damage that the structure has sustained.) The goal of the SWEAT test is to control the
applied current by keeping the calculated time-to-failure (CTTF ) constant. CTTF is related to the temperature, T, and applied current density, j, through Black's Eq. [11]: CTTF
A Ea : exp jn kT
1
The problem with SWEAT testing is that no attempt is made to control either of the independent variables, temperature or current. Only the dependent variable, time-to-failure, is controlled. A `target time-to-failure' is set at the beginning of the test and when this target time is short, as is required for reliability monitoring in a production line environment, the metallization temperature can easily rise close to the melting point of aluminium. This is illustrated in Figs. 4 and 5. Fig. 4 shows the test structure calculated temperatures during SWEAT testing at the beginning of the CTTF control. While the calculated temperatures for the NIST-type structures are high (exceeding the solubility limit of 3168C and in some cases the bulk diusion limit of 3508C), the calculated temperatures for the SWEAT-type structures are not extreme. However, in attempting to control the CTTF, the algorithm varies the currents applied to the test structure. The Joule heating and metallization temperature are thus variable during test and the actual structure temperatures just prior to failure can become very high. This is illustrated in Fig. 5 where all of the calculated temperatures exceed the solubility and diusion changeover limits and some approach the melting point of alu-
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Fig. 6. Calculated test structure temperatures just prior to failure during BEM tests.
minium. With such poor temperature control and excessive metallization temperatures it is easy to understand why the SWEAT test was not successful in detecting either the microstructure or process changes over these short test times. The BEM algorithm that was used in this work was dierent to the classical BEM method [5]. In this work
the current was varied such that the temperature was ramped in constant temperature steps. Temperature is the dominant independent variable in Black's equation and this attempt to control it is an improvement over the original BEM method where current was ramped in constant steps. The calculated structure temperatures, observed just prior to failure during the BEM
Fig. 7. Calculated test structure temperatures during Isothermal tests.
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tests, are illustrated in Fig. 6. The calculated temperatures observed during BEM tests on SWEAT-type structures are not extreme. However, despite controlling the dominant independent variable in Black's equation and the relatively low test temperatures observed just prior to failure, ramping the temperature until failure inadvertently causes the build-up of timevarying thermal gradients in the test structure. These gradients lead to locations of excessive temperatures where thermal runaway and fusing occurs and for this reason the actual fail times observed bear little relation to the real electromigration performance of the metallization. The goal of the Isothermal algorithm is to vary the current applied to the structure and the Joule heating in the structure in order to maintain a constant structure temperature throughout the test. The obvious advantage of this method over either SWEAT or BEM is that an attempt is made to directly control the temperature and for this reason the test is less likely to susceptible to thermal gradients and thermal runaway failures. The calculated structure temperatures that were necessary to achieve the short test times in this work are illustrated in Fig. 7. While the calculated temperatures for the NIST-type structures are high, those of the SWEAT-type structures are within a reasonable regime (especially for the 2 min test). These low temperatures coupled with the absence of harmful thermal gradients are good reasons why the Isothermal/SWEAT structure combination was better at detecting the imposed changes in microstructure and macrostructure than any of the other test method/test structure combinations evaluated in this study. 5. Conclusions It can be concluded that of the three test methods
and four test structure designs evaluated, the Isothermal test method used in conjunction with either of the SWEAT-based test structure designs is the only safe combination for detecting a change in the metallization reliability when one actually exists and not detecting a change when one does not. Its success can be attributed to the relatively low temperatures necessary and the method of temperature control employed. This test method/test structure combination can thus be recommended for use as fast, in-line testing to detect and control the reliability of metallization.
References [1] Molyneaux J, Prendergast J, Finucane N, Houlihan S, Proc. IEEE Integrated Reliability Workshop, 1996. p. 16. [2] Prendergast J, Murphy E, Stephenson M. Intl Journal of Quality and Reliability Engineering Volume 1997;13(5). [3] Lloyd JR. Mat Res Soc Symp Proc 1992;260:735±44. [4] Root BJ, Turner T, Proc. 23rd Ann. Reliab. Phys. Symp. IEEE, 1985. p. 100. [5] Hong CC, Crook DL, Proc. 23rd Ann. Reliab. Phys. Symp. IEEE, 1985. p. 108. [6] Pierce DG, Brusius PG. IEEE Electron Device Letters 1993;14(6). [7] ASTM Standard F1259-89,.Standard guide for design of ¯at, straight-line test structures for detecting metallization open-circuit or resistance-increase failure due to electromigration. Annual Book of ASTM Standards, vol. 10.04, 1989. [8] JEDEC Solid State Products Engineering Council. A guide for the design of straight line SWEAT test structures. JC-14.2-93-116, 1993. [9] Foley S, Martin D, Mathewson A. Proc. IEEE Integrated Reliability Workshop 1996;110±5. [10] Mondolfo LF. Aluminium alloys: structure and properties. London: Butterworths, 1976. [11] Black JR. 5th Annual Proc. Reliability Physics Symp, 1967. p. 148±59.