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Abnormal behavior with hump characteristics in current stressed a-InGaZnO thin film transistors
Solid-State Electronics 137 (2017) 22–28
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Abnormal behavior with hump characteristics in current stressed a-InGaZnO thin film transistors Woo-Sic Kim a,⇑, Yong-Jung Cho a, Yeol-Hyeong Lee a, JeongKi Park b, GeonTae Kim b, Ohyun Kim a a b
Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Kyungbuk 37673, Republic of Korea IT Development Group, LG Display, Gumi, Kyungbuk 39394, Republic of Korea
a r t i c l e
i n f o
Article history: Received 22 May 2017 Received in revised form 12 July 2017 Accepted 4 August 2017 Available online 5 August 2017 The review of this paper was arranged by Prof. E. Calleja Keywords: IGZO Instability Current stress Joule heating Hump Turn Around
a b s t r a c t We investigated the degradation mechanism of a-InGaZnO TFTs under simultaneous gate and drain bias stress. Gate and drain bias of 20 V were applied simultaneously to induce current stress, and abnormal turn-around behavior in transfer characteristics with a hump phenomenon were identified. Hump characteristics were interpreted in terms of parasitic current path, and the degradation itself was found to be caused dominantly by the electrical field and to be accelerated with current by Joule heating. The mechanism of asymmetrical degradation after current stress was also investigated. By decomposing the curves into two curves and measuring the relaxation behavior of the stressed TFTs, we also found that abnormal turn-around behavior in the transfer characteristics was related to acceptor-like states. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction Thin film transistors (TFTs) based on metal oxide have been widely investigated due to their high carrier mobility, good transparency, and low process temperature [1]. Especially, amorphousInGaZnO (a-IGZO) TFTs have high on/off current ratio, excellent uniformity and applicability to large size displays, and are therefore considered to be among the most promising candidates as switching/driving TFTs in flat panel displays. However, several factors such as temperature, illumination, ambient gas/molecule and bias condition reduce the reliability of a-IGZO TFTs [2–8]. Degradation mechanism of a-IGZO TFTs under gate bias stress with and without combinations of other factors have been quite well explained [5–8]; positive bias stress (PBS) usually causes positive shift of threshold voltage Vth by electron trapping at the gate insulator, whereas negative bias illumination stress (NBIS) causes negative shift of Vth by hole trapping or ionization of oxygen vacancy. However, the degradation mechanism under current stress (CS), during which gate and drain bias are applied simultaneously, should also be clarified to assure stability in practical operation. ⇑ Corresponding author. E-mail address: [email protected] (W.-S. Kim). http://dx.doi.org/10.1016/j.sse.2017.08.001 0038-1101/Ó 2017 Elsevier Ltd. All rights reserved.
Instability of a-IGZO TFTs under CS have been studied [9–14]. Impact ionization [9,10], hot carrier injection [11,12] and Joule heating [13,14] are the most-commonly accepted concepts to explain the degradation under CS, but no clear mechanism has been suggested to explain the degradation. In this paper, we investigated degradation behavior of back channel etched a-IGZO TFTs under CS. After CS, a hump phenomenon in I-V characteristics and abnormal turn-around behavior were identified. CS was found to cause asymmetrical degradation as well as Joule heating. Moreover, mechanism of abnormal turn-around behavior was clarified by decomposing I-V characteristics into two parts and measuring relaxation behavior after stress. 2. Method and measurements a-InGaZnO TFTs were fabricated on glass substrate with inverted staggered and back-channel-etched structure. Mo-Ti was utilized as the electrodes in the fabrication process. Detailed structure of the fabricated device has been described elsewhere [6]. TFTs with channel width W = 180 lm and length L = 4.5 lm were used for the overall experiment, but TFT having W = 30 lm with same L was also used when we investigated W dependency. Transfer characteristics of the TFTs were analyzed using an Agilent 4156 A semiconductor parameter analyzer. To apply CS, gate
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voltage VGS and drain voltage VDS were set to 20 V simultaneously for 100,000 s at temperature of 90 °C. During the stress, I-V characteristics were measured by sweeping VGS from 20 V to +20 V with fixed VDS of 0.1 V at pre-determined times. In addition, saturationregion characteristics were measured with fixed VDS = 20 V to examine the asymmetrical degradation. Transfer characteristic with hump phenomenon was decomposed into two curves by fitting part of the original curve to the linear-region drain current equation.
3. Results and discussion Transfer characteristics of the TFTs after CS for 100,000 s with VGS = VDS = 20 V were measured in darkness (Fig. 1). Transfer curves showed distinct hump characteristics with bi-directional shift after only 100 s of stress time ts. During the early stage of the stress, the on-current region shifted in the positive direction, and the subthreshold region shifted in the negative direction. However, abnormal turn-around behavior of sub-threshold characteristics occurred after prolonged ts; until 2000 s of stress, the transfer curve shifted bi-directionally, but at ts > 2000 s the overall shift was positive. Plot (Fig. 1b) of changes in hump threshold voltage VtH (VGS when drain current reached 109 A) showed clear turnaround behavior whereas plot (Fig. 1c) of changes in on-current region voltage VtOn (VGS when drain current reached 0.5 lA) showed continued positive shift. Hump characteristics are usually interpreted as current flowing through a parasitic current path [8,15,16]. Some papers suggested
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that the hump originates due to creation of donor-like states in the front channel of the device [17,18]. However, band structure during current flow in our case is not a favorable condition for donor-like states to be generated at the front channel. Because the Fermi level is close to the conduction band under positive gate bias, trap states in the band-gap would be occupied by electrons for a long ts. As we reported earlier about hump phenomenon for positive gate bias stressed a-IGZO TFTs [8], hump characteristics in this work could also be interpreted in terms of migration of positively charged species [15,19] (Zn+, H+, V+Oand V2+ O ) to the back-channel interface. When positive gate bias drives migration of preexisting positively-charged species to the back channel during the stress, the conduction band in the back channel would be lowered, and a parasitic conduction path would be formed with low threshold voltage Vth (Fig. 2a, b) [8]. On the other hand, the front channel which is the main conduction path, has relatively high Vth and therefore turns on later than the parasitic path, because electrons become trapped at the gate insulator/a-IGZO interface during the stress (Fig. 2a, c). Consequently, transfer characteristics showed two-step rising behavior due to the different Vth of the two paths. To identify the influence of current on the degradation behavior, the same gate bias stress was applied while the drain terminal was floated (Fig. 3). The same turn-around behavior in the subthreshold region and a hump phenomenon as in CS occurred after drain-floated stress, although the degradation was slower than during CS and some differences in response were evident. During ts of 100 s, for example, positive shift of the on-current region
Fig. 1. (a) Changes in transfer characteristics during current stress with VGS = VDS = 20 V and (b) DVtH and (c) DVtOn as a function of stress time. Shift of the transfer curve was initially bidirectional (red arrow), but was positive afterwards (blue arrow). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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Fig. 2. (a) Transfer characteristics with hump phenomenon exhibiting two step rising behavior after current stress. Qualitative description of band diagram in (b) region 1 and (c) region 2.
Fig. 3. (a) Changes in transfer characteristics during drain-floated stress with VGS = 20 V and (b) DVtH and (c) DVtOn as a function of stress time. Same degradation but tardy response with current stressed case was shown.
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Fig. 6. (a) Schematic diagram of proposed mechanism of asymmetrical degradation. (b) Forward saturation mode and reverse saturation mode transfer characteristics of drain floating stressed device showing symmetrical degradation.
Fig. 4. Comparison of transfer characteristics after current stress for 100 s in a-IGZO TFTs (a) with different channel widths (30 lm, 180 lm) and (b) at different temperatures (30, 60, 90 °C).
Fig. 5. Forward saturation mode and reverse saturation mode transfer characteristics of current stressed device showing asymmetrical degradation.
was about 4.026 V for current stressed one whereas that of drainfloating stressed one was only about 0.298 V (Fig. 1c and Fig. 3c). In addition, turn-around behavior of sub-threshold region occurred 10 times slower in drain-floating stressed case than current stressed case (Fig. 1b and Fig. 3b). This result implies that the degradation is dominantly affected by electric field and is acceler-
ated with Joule heating [13,14,20] by current flowing through the channel. TFTs with narrower W tends to dissipate heat more efficiently [13,21,22]. TFT with large W = 180 lm and small W = 30 lm were measured and compared after the same stress for 100 s with VGS = VDS = 20 V (Fig. 4a). After 100 s, the curve clearly degraded in the device with W = 180 lm, but showed relatively tardy degradation in the device with W = 30 lm. Moreover, as temperature was increased (30, 60 and 90 °C), the degradation accelerated when the same stress was applied (Fig. 4b). The increase in degradation rate with increase in W and in temperature supports the hypothesis that the degradation was accelerated by Joule heating after CS. In general, asymmetrical degradation is expected when TFTs are exposed to CS [14,23,24]. Therefore, transfer characteristics in forward saturation (FWD_Sat) and reverse saturation (REV_Sat) mode were measured before and after stress with VGS = VDS = 20 V (Fig. 5). In REV_Sat measurement, source and drain terminal were interchanged. Forward and reverse saturation curves were almost same before CS; this similarity means that the TFTs had good symmetry. However, after CS, the forward-mode and reverse-mode I-V curves differed. The sub-threshold region turned on earlier during FWD_Sat than during REV_Sat; this difference means that local Vth is lower near the source of the parasitic path than near the drain. On the contrary, the on-current during FWD_Sat rose relatively later than during REV_Sat; this difference means that local Vth is higher near the source of the main path than near the drain. Degradation asymmetry can be explained by a combination of lateral and vertical electric fields (Fig. 6a). Formation of a lateral field due to drain bias during the stress will increase accumulation of positively-charged species near the source side of the back channel. In contrast, the large vertical field between gate and source electrode during the CS will increase the number of electrons trapped at the source side of the front channel interface. Therefore, the sub-threshold region characteristic caused by the back channel
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Fig. 7. (a) Transfer characteristics with hump phenomenon decomposed into parasitic and main transistor components. Transfer characteristics of (b) original, (c) fitted parasitic transistor and (d) fitted main transistor during current stress (insets: linear scale curves for transfer characteristics).
Fig. 8. (a) Relaxation behavior for 68 h after 100,000 s of current stress and (b) DVtH and (c) DVtOn as a function of relaxation time. Recovery hardly happened after shape of the curve was almost restored.
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had lower Vth while on-current region caused by the front channel had higher Vth during FWD_Sat than during REV_Sat. On the other hand, drain-floated stress did not cause any noticeable difference between FWD_Sat and REV_Sat (Fig. 6b), supporting the suggested mechanism. To clarify the abnormal turn-around behavior, I-V curves were decomposed into parasitic and main transistor components (Fig. 7). Because we applied VDS = 0.1 V in the measurements, turn-on characteristics of the parasitic transistor could be fitted and extracted using the linear-region drain current equation
IDS
W 1 ¼ lC i ðV GS V th ÞV DS V 2DS L 2
where l [cm2V1s1] is carrier mobility and Ci [F/cm2] is insulator capacitance. The extracted turn-on region characteristics of the parasitic transistor were subtracted from the original curve to reveal the turn-on characteristics of the main transistor. As a result, original I-V curves with hump behavior could be successfully decomposed into parasitic and main transistors (Fig. 7a). Parasitic and main transistor characteristics extracted from the original curve were plotted for all ts (Fig. 7b, c, d). At ts1000 s just before turn-around behavior in the parasitic transistor started to occur, the sub-threshold region in the main transistor started to degrade (Fig. 7d). Because positive shift was accompanied by degradation of the sub-threshold slope in the I-V curves, this change can be interpreted in terms of acceptor-like states creation [25]. When acceptor-like states induce positive shift of the main transistor and weaken the influence of gate bias to the back channel, higher VGS is necessary to form a parasitic current path. Therefore, it would result in an overall positive shift including the parasitic current path, which appears as turn-around behavior. Relaxation behavior of the stressed device occurred exactly in the opposite direction of the stress-induced degradation (Fig. 8). The negatively-shifted parasitic transistor recovered to the positive direction (Fig. 8b), and the positively-shifted main transistor recovered to the negative direction (Fig. 8c). These change can be interpreted as returning of positive species accumulated in the back channel and de-trapping of electrons from the front channel. More importantly, after the shape of the curve was almost restored, further recovery to the initial location almost ceased. This result implies that relatively unrecoverable positive shift happened during the stress and it matches well with our interpretation that overall positive shift after turn-around behavior occurred by acceptor-like states, because degradation induced by trap states is relatively difficult to recover [26–28]. 4. Conclusion We investigated the degradation mechanism of back-channeletched a-IGZO TFTs under CS. Turn-around behavior with hump characteristics in I-V curve was observed after CS. The hump phenomenon was due to formation of a parasitic current path in the back channel region. The degradation was found to be dominantly caused by electric field and accelerated by Joule heating. Asymmetrical degradation in the source and drain was observed under forward and reverse saturation measurements. Accumulation of positively-charged species in the back channel and more electron trapping in the front channel region near source side were suggested as the cause of asymmetry in the I-V curves. Transfer characteristics after stress were decomposed into parasitic and main transistors, and abnormal turn-around behavior was suggested to be due to acceptor-like states; this hypothesis was supported by the relaxation measurement result which exhibited bi-directional recovery to the opposite direction of the degradation and slow recovery afterwards.
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Acknowledgements This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, Under the ‘‘ICT Consilience Creative Program” (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion), and technically by the LG display. The authors thank LG Display for technical support. References [1] Nomura K, Ohta H, Takagi A, Kamiya T, Hirano M, Hosono H. Roomtemperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004;432:488. [2] Takechi K, Nakata M, Eguchi T, Yamaguchi H, Kaneko S. Temperaturedependent transfer characteristics of amorphous InGaZnO4 thin-film transistors. Jpn J Appl Phys 2009;48:011301. [3] Park J-S, Jeong JK, Chung H-J, Mo Y-G, Kim HD. Electronic transport properties of amorphous indium-gallium-zinc oxide semiconductor upon exposure to water. Appl Phys Lett 2008;92:072104. [4] Chen W-T, Lo S-Y, Kao S-C, Zan H-W, Tsai C-C, Lin J-H, et al. Oxygen-dependent instability and annealing/passivation effects in amorphous In-Ga-Zn-O thinfilm transistors. IEEE Electron Device Lett 2011;32:1552. [5] Oh H, Yoon S-M, Ryu MK, Hwang C-S, Yang S, Park S-HK. Transition of dominant instability mechanism depending on negative gate bias under illumination in amorphous In-Ga-Zn-O thin film transistor. Appl Phys Lett 2011;98:033504. [6] Kim W-S, Lee Y-H, Cho Y-J, Kim B-K, Park KT, Kim O. Effect of wavelength and intensity of light on a-InGaZnO TFTs under negative bias illumination stress. ECS J Solid State Sci Technol 2017;6:Q6. [7] Lee Y-H, Seok S, Lee T-K, Kim S-H, Kim B-K, Kim O. Effect of Rising Edge during Dynamic Stress With Duty Ratio in Amorphous InGaZnO Thin Film Transistors. J Disp Technol 2016;12:1078. [8] Cho Y-J, Lee Y-H, Kim W-S, Kim B-K, Park KT, Kim O. Effect of illumination on the hump phenomenon in I-V characteristics of amorphous InGaZnO TFTs under positive gate-bias stress. Phys Status Solidi A 2017;214:1600503. [9] Choi S-H, Han M-K. Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress. Appl Phys Lett 2012;100:043503. [10] Choi S, Kim H, Jo C, Kim H-S, Choi S-J, Kim DM, et al. The effect of gate and drain fields on the competition between donor-like state creation and local electron trapping in In-Ga-Zn-O thin film transistors under current stress. IEEE Electron Device Lett 2015;36:1336. [11] Tsai M-Y, Chang T-C, Chu A-K, Chen T-C, Hsieh T-Y, Chen Y-T, et al. Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures. Thin Solid Films 2013;528:57. [12] Tsai M-Y, Chang T-C, Chu A-K, Chen T-C, Hsieh T-Y, Lin K-Y, et al. Asymmetric structure-induced hot-electron injection under hot-carrier stress in a-InGaZnO thin film transistor. Appl Phys Lett 2013;103:143508. [13] Mativenga M, Hong S, Jang J. High current stress effects in amorphousInGaZnO4 thin-film transistors. Appl Phys Lett 2013;102:023503. [14] Hsieh T-Y, Chang T-C, Chen T-C, Tsai M-Y, Chen Y-T, Chung Y-C, et al. Origin of self-heating effect induced asymmetrical degradation behavior in InGaZnO thin-film transistors. Appl Phys Lett 2013;100:232101. [15] Kim Y-M, Jeong K-S, Yun H-J, Yang S-D, Lee S-Y, Kim Y-C, et al. Investigation of zinc interstitial ions as the origin of anomalous stress-induced hump in amorphous indium gallium zinc oxide thin film transistors. Appl Phys Lett 2013;102:173502. [16] Huang S-Y, Chang T-C, Chen M-C, Chen S-C, Tsai C-T, Hung M-C, et al. Effects of ambient atmosphere on electrical characteristics of Al2O3 passivated InGaZnO thin film transistors during positive-bias-temperature-stress operation. Electrochem Solid State Lett 2011;14:H177. [17] Im H, Song H, Jeong J, Hong Y, Hong Y. Effects of defect creation on bidirectional behavior with hump characteristics of InGaZnO TFTs under bias and thermal stress. Jpn J Appl Phys 2015;54:03CB03. [18] Furuta M, Kamada Y, Kimura M, Hiramatsu T, Matsuda T, Furuta H, et al. Analysis of hump characteristics in thin-film transistors with ZnO channels deposited by sputtering at various oxygen partial pressures. IEEE Electron Device Lett 2010;31:1257. [19] Oh H, Park S-HK, Hwang C-S, Yang S, Ryu MK. Enhanced bias illumination stability of oxide thin film transistors through insertion of ultrathin positive charge barrier into active material. Appl Phys Lett 2011;99:022105. [20] Urakawa S, Tomai S, Ueoka Y, Yamazaki H, Kasami M, Yano K, et al. Thermal analysis of amorphous oxide thin-film transistor degraded y combination of joule heating and hot carrier effect. Appl Phys Lett 2013;102:053506. [21] Liu K-H, Chang T-C, Wu M-S, Hung Y-S, Hung P-H, Hsieh T-Y, et al. Investigation of channel width-dependent threshold voltage variation in aInGaZnO thin-film transistors. Appl Phys Lett 2014;104:133503. [22] Hsieh T-Y, Chang T-C, Chen T-C, Chen Y-T, Tsai M-Y, Chu A-K, et al. Selfheating-effect-induced degradation behaviors in a-InGaZnO thin-film transistors. IEEE Electron Device Lett 2014;34:63.
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[23] Chen B-W, Chang T-C, Hung Y-J, Hsieh T-Y, Tsai M-Y, Liao P-Y, et al. Investigation of temperature-dependent asymmetric degradation behavior induced by hot carrier effect in oxygen ambiance in In-Ga-Zn-O thin film transistors. Thin Solid Films 2014;572:33. [24] Jeong C-Y, Lee D, Song S-H, Kim JI, Lee J-H, Kwon H-I. A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization. Semicond Sci Technol 2014;29:045023. [25] Um JG, Mativenga M, Migliorato P, Jang J. Defect generation in amorphousindium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature. J Appl Phys 2014;115:134502. [26] Lee SM, Cho W-J, Park JT. Device Instability Under High Gate and Drain Biases in InGaZnO Thin Film Transistors. IEEE Trans Device Mater Reliab 2014;14:471. [27] Lee SM, Yu CG, Cho WJ, Park JT. Hot carrier degradation of InGaZnO thin film transistors under light illumination at the elevated temperature. Solid-State Electron 2012;72:88. [28] Oh H, Yoon SM, Ryu MK, Hwang CS, Yang S, Park SHK. Photon-accelerated negative bias instability involving subgap states creation in amorphous In-GaZn-O thin film transistor. Appl Phys Lett 2010;97:183502.
Woo-Sic Kim received the B.S. degree in electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Kyungbuk, Korea, in 2014, and is currently pursuing the Ph.D. degree in the Department of Electrical Engineering in POSTECH. His research interest is amorphous oxide thin-film transistors for application in display devices.
Ohyun Kim received the B.S. degree in electrical engineering from Seoul national University, in 1977, and the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1983. From 1983 to 1986, he was with Samsung Electronics, Korea, where he was involved in DRAM development. From 1989 to 1990, he was with Bell Communications Research, NJ, USA; during the period his research was focused on high speed devices. Since 1986, he has been a Professor in the Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH). His research interests include EUV lithography, polymer memories, AMOLEDs, Oxide TFTs, Graphene FETs and ReRAMs, and strained high-voltage MOSFETs.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Abnormal behavior with hump characteristics in current stressed a-InGaZnO thin film transistors Woo-Sic Kim a,⇑, Yong-Jung Cho a, Yeol-Hyeong Lee a, JeongKi Park b, GeonTae Kim b, Ohyun Kim a a b
Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Kyungbuk 37673, Republic of Korea IT Development Group, LG Display, Gumi, Kyungbuk 39394, Republic of Korea
a r t i c l e
i n f o
Article history: Received 22 May 2017 Received in revised form 12 July 2017 Accepted 4 August 2017 Available online 5 August 2017 The review of this paper was arranged by Prof. E. Calleja Keywords: IGZO Instability Current stress Joule heating Hump Turn Around
a b s t r a c t We investigated the degradation mechanism of a-InGaZnO TFTs under simultaneous gate and drain bias stress. Gate and drain bias of 20 V were applied simultaneously to induce current stress, and abnormal turn-around behavior in transfer characteristics with a hump phenomenon were identified. Hump characteristics were interpreted in terms of parasitic current path, and the degradation itself was found to be caused dominantly by the electrical field and to be accelerated with current by Joule heating. The mechanism of asymmetrical degradation after current stress was also investigated. By decomposing the curves into two curves and measuring the relaxation behavior of the stressed TFTs, we also found that abnormal turn-around behavior in the transfer characteristics was related to acceptor-like states. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction Thin film transistors (TFTs) based on metal oxide have been widely investigated due to their high carrier mobility, good transparency, and low process temperature [1]. Especially, amorphousInGaZnO (a-IGZO) TFTs have high on/off current ratio, excellent uniformity and applicability to large size displays, and are therefore considered to be among the most promising candidates as switching/driving TFTs in flat panel displays. However, several factors such as temperature, illumination, ambient gas/molecule and bias condition reduce the reliability of a-IGZO TFTs [2–8]. Degradation mechanism of a-IGZO TFTs under gate bias stress with and without combinations of other factors have been quite well explained [5–8]; positive bias stress (PBS) usually causes positive shift of threshold voltage Vth by electron trapping at the gate insulator, whereas negative bias illumination stress (NBIS) causes negative shift of Vth by hole trapping or ionization of oxygen vacancy. However, the degradation mechanism under current stress (CS), during which gate and drain bias are applied simultaneously, should also be clarified to assure stability in practical operation. ⇑ Corresponding author. E-mail address: [email protected] (W.-S. Kim). http://dx.doi.org/10.1016/j.sse.2017.08.001 0038-1101/Ó 2017 Elsevier Ltd. All rights reserved.
Instability of a-IGZO TFTs under CS have been studied [9–14]. Impact ionization [9,10], hot carrier injection [11,12] and Joule heating [13,14] are the most-commonly accepted concepts to explain the degradation under CS, but no clear mechanism has been suggested to explain the degradation. In this paper, we investigated degradation behavior of back channel etched a-IGZO TFTs under CS. After CS, a hump phenomenon in I-V characteristics and abnormal turn-around behavior were identified. CS was found to cause asymmetrical degradation as well as Joule heating. Moreover, mechanism of abnormal turn-around behavior was clarified by decomposing I-V characteristics into two parts and measuring relaxation behavior after stress. 2. Method and measurements a-InGaZnO TFTs were fabricated on glass substrate with inverted staggered and back-channel-etched structure. Mo-Ti was utilized as the electrodes in the fabrication process. Detailed structure of the fabricated device has been described elsewhere [6]. TFTs with channel width W = 180 lm and length L = 4.5 lm were used for the overall experiment, but TFT having W = 30 lm with same L was also used when we investigated W dependency. Transfer characteristics of the TFTs were analyzed using an Agilent 4156 A semiconductor parameter analyzer. To apply CS, gate
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voltage VGS and drain voltage VDS were set to 20 V simultaneously for 100,000 s at temperature of 90 °C. During the stress, I-V characteristics were measured by sweeping VGS from 20 V to +20 V with fixed VDS of 0.1 V at pre-determined times. In addition, saturationregion characteristics were measured with fixed VDS = 20 V to examine the asymmetrical degradation. Transfer characteristic with hump phenomenon was decomposed into two curves by fitting part of the original curve to the linear-region drain current equation.
3. Results and discussion Transfer characteristics of the TFTs after CS for 100,000 s with VGS = VDS = 20 V were measured in darkness (Fig. 1). Transfer curves showed distinct hump characteristics with bi-directional shift after only 100 s of stress time ts. During the early stage of the stress, the on-current region shifted in the positive direction, and the subthreshold region shifted in the negative direction. However, abnormal turn-around behavior of sub-threshold characteristics occurred after prolonged ts; until 2000 s of stress, the transfer curve shifted bi-directionally, but at ts > 2000 s the overall shift was positive. Plot (Fig. 1b) of changes in hump threshold voltage VtH (VGS when drain current reached 109 A) showed clear turnaround behavior whereas plot (Fig. 1c) of changes in on-current region voltage VtOn (VGS when drain current reached 0.5 lA) showed continued positive shift. Hump characteristics are usually interpreted as current flowing through a parasitic current path [8,15,16]. Some papers suggested
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that the hump originates due to creation of donor-like states in the front channel of the device [17,18]. However, band structure during current flow in our case is not a favorable condition for donor-like states to be generated at the front channel. Because the Fermi level is close to the conduction band under positive gate bias, trap states in the band-gap would be occupied by electrons for a long ts. As we reported earlier about hump phenomenon for positive gate bias stressed a-IGZO TFTs [8], hump characteristics in this work could also be interpreted in terms of migration of positively charged species [15,19] (Zn+, H+, V+Oand V2+ O ) to the back-channel interface. When positive gate bias drives migration of preexisting positively-charged species to the back channel during the stress, the conduction band in the back channel would be lowered, and a parasitic conduction path would be formed with low threshold voltage Vth (Fig. 2a, b) [8]. On the other hand, the front channel which is the main conduction path, has relatively high Vth and therefore turns on later than the parasitic path, because electrons become trapped at the gate insulator/a-IGZO interface during the stress (Fig. 2a, c). Consequently, transfer characteristics showed two-step rising behavior due to the different Vth of the two paths. To identify the influence of current on the degradation behavior, the same gate bias stress was applied while the drain terminal was floated (Fig. 3). The same turn-around behavior in the subthreshold region and a hump phenomenon as in CS occurred after drain-floated stress, although the degradation was slower than during CS and some differences in response were evident. During ts of 100 s, for example, positive shift of the on-current region
Fig. 1. (a) Changes in transfer characteristics during current stress with VGS = VDS = 20 V and (b) DVtH and (c) DVtOn as a function of stress time. Shift of the transfer curve was initially bidirectional (red arrow), but was positive afterwards (blue arrow). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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Fig. 2. (a) Transfer characteristics with hump phenomenon exhibiting two step rising behavior after current stress. Qualitative description of band diagram in (b) region 1 and (c) region 2.
Fig. 3. (a) Changes in transfer characteristics during drain-floated stress with VGS = 20 V and (b) DVtH and (c) DVtOn as a function of stress time. Same degradation but tardy response with current stressed case was shown.
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Fig. 6. (a) Schematic diagram of proposed mechanism of asymmetrical degradation. (b) Forward saturation mode and reverse saturation mode transfer characteristics of drain floating stressed device showing symmetrical degradation.
Fig. 4. Comparison of transfer characteristics after current stress for 100 s in a-IGZO TFTs (a) with different channel widths (30 lm, 180 lm) and (b) at different temperatures (30, 60, 90 °C).
Fig. 5. Forward saturation mode and reverse saturation mode transfer characteristics of current stressed device showing asymmetrical degradation.
was about 4.026 V for current stressed one whereas that of drainfloating stressed one was only about 0.298 V (Fig. 1c and Fig. 3c). In addition, turn-around behavior of sub-threshold region occurred 10 times slower in drain-floating stressed case than current stressed case (Fig. 1b and Fig. 3b). This result implies that the degradation is dominantly affected by electric field and is acceler-
ated with Joule heating [13,14,20] by current flowing through the channel. TFTs with narrower W tends to dissipate heat more efficiently [13,21,22]. TFT with large W = 180 lm and small W = 30 lm were measured and compared after the same stress for 100 s with VGS = VDS = 20 V (Fig. 4a). After 100 s, the curve clearly degraded in the device with W = 180 lm, but showed relatively tardy degradation in the device with W = 30 lm. Moreover, as temperature was increased (30, 60 and 90 °C), the degradation accelerated when the same stress was applied (Fig. 4b). The increase in degradation rate with increase in W and in temperature supports the hypothesis that the degradation was accelerated by Joule heating after CS. In general, asymmetrical degradation is expected when TFTs are exposed to CS [14,23,24]. Therefore, transfer characteristics in forward saturation (FWD_Sat) and reverse saturation (REV_Sat) mode were measured before and after stress with VGS = VDS = 20 V (Fig. 5). In REV_Sat measurement, source and drain terminal were interchanged. Forward and reverse saturation curves were almost same before CS; this similarity means that the TFTs had good symmetry. However, after CS, the forward-mode and reverse-mode I-V curves differed. The sub-threshold region turned on earlier during FWD_Sat than during REV_Sat; this difference means that local Vth is lower near the source of the parasitic path than near the drain. On the contrary, the on-current during FWD_Sat rose relatively later than during REV_Sat; this difference means that local Vth is higher near the source of the main path than near the drain. Degradation asymmetry can be explained by a combination of lateral and vertical electric fields (Fig. 6a). Formation of a lateral field due to drain bias during the stress will increase accumulation of positively-charged species near the source side of the back channel. In contrast, the large vertical field between gate and source electrode during the CS will increase the number of electrons trapped at the source side of the front channel interface. Therefore, the sub-threshold region characteristic caused by the back channel
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Fig. 7. (a) Transfer characteristics with hump phenomenon decomposed into parasitic and main transistor components. Transfer characteristics of (b) original, (c) fitted parasitic transistor and (d) fitted main transistor during current stress (insets: linear scale curves for transfer characteristics).
Fig. 8. (a) Relaxation behavior for 68 h after 100,000 s of current stress and (b) DVtH and (c) DVtOn as a function of relaxation time. Recovery hardly happened after shape of the curve was almost restored.
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had lower Vth while on-current region caused by the front channel had higher Vth during FWD_Sat than during REV_Sat. On the other hand, drain-floated stress did not cause any noticeable difference between FWD_Sat and REV_Sat (Fig. 6b), supporting the suggested mechanism. To clarify the abnormal turn-around behavior, I-V curves were decomposed into parasitic and main transistor components (Fig. 7). Because we applied VDS = 0.1 V in the measurements, turn-on characteristics of the parasitic transistor could be fitted and extracted using the linear-region drain current equation
IDS
W 1 ¼ lC i ðV GS V th ÞV DS V 2DS L 2
where l [cm2V1s1] is carrier mobility and Ci [F/cm2] is insulator capacitance. The extracted turn-on region characteristics of the parasitic transistor were subtracted from the original curve to reveal the turn-on characteristics of the main transistor. As a result, original I-V curves with hump behavior could be successfully decomposed into parasitic and main transistors (Fig. 7a). Parasitic and main transistor characteristics extracted from the original curve were plotted for all ts (Fig. 7b, c, d). At ts1000 s just before turn-around behavior in the parasitic transistor started to occur, the sub-threshold region in the main transistor started to degrade (Fig. 7d). Because positive shift was accompanied by degradation of the sub-threshold slope in the I-V curves, this change can be interpreted in terms of acceptor-like states creation [25]. When acceptor-like states induce positive shift of the main transistor and weaken the influence of gate bias to the back channel, higher VGS is necessary to form a parasitic current path. Therefore, it would result in an overall positive shift including the parasitic current path, which appears as turn-around behavior. Relaxation behavior of the stressed device occurred exactly in the opposite direction of the stress-induced degradation (Fig. 8). The negatively-shifted parasitic transistor recovered to the positive direction (Fig. 8b), and the positively-shifted main transistor recovered to the negative direction (Fig. 8c). These change can be interpreted as returning of positive species accumulated in the back channel and de-trapping of electrons from the front channel. More importantly, after the shape of the curve was almost restored, further recovery to the initial location almost ceased. This result implies that relatively unrecoverable positive shift happened during the stress and it matches well with our interpretation that overall positive shift after turn-around behavior occurred by acceptor-like states, because degradation induced by trap states is relatively difficult to recover [26–28]. 4. Conclusion We investigated the degradation mechanism of back-channeletched a-IGZO TFTs under CS. Turn-around behavior with hump characteristics in I-V curve was observed after CS. The hump phenomenon was due to formation of a parasitic current path in the back channel region. The degradation was found to be dominantly caused by electric field and accelerated by Joule heating. Asymmetrical degradation in the source and drain was observed under forward and reverse saturation measurements. Accumulation of positively-charged species in the back channel and more electron trapping in the front channel region near source side were suggested as the cause of asymmetry in the I-V curves. Transfer characteristics after stress were decomposed into parasitic and main transistors, and abnormal turn-around behavior was suggested to be due to acceptor-like states; this hypothesis was supported by the relaxation measurement result which exhibited bi-directional recovery to the opposite direction of the degradation and slow recovery afterwards.
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Acknowledgements This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, Under the ‘‘ICT Consilience Creative Program” (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion), and technically by the LG display. The authors thank LG Display for technical support. References [1] Nomura K, Ohta H, Takagi A, Kamiya T, Hirano M, Hosono H. Roomtemperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004;432:488. [2] Takechi K, Nakata M, Eguchi T, Yamaguchi H, Kaneko S. Temperaturedependent transfer characteristics of amorphous InGaZnO4 thin-film transistors. Jpn J Appl Phys 2009;48:011301. [3] Park J-S, Jeong JK, Chung H-J, Mo Y-G, Kim HD. Electronic transport properties of amorphous indium-gallium-zinc oxide semiconductor upon exposure to water. Appl Phys Lett 2008;92:072104. [4] Chen W-T, Lo S-Y, Kao S-C, Zan H-W, Tsai C-C, Lin J-H, et al. Oxygen-dependent instability and annealing/passivation effects in amorphous In-Ga-Zn-O thinfilm transistors. IEEE Electron Device Lett 2011;32:1552. [5] Oh H, Yoon S-M, Ryu MK, Hwang C-S, Yang S, Park S-HK. Transition of dominant instability mechanism depending on negative gate bias under illumination in amorphous In-Ga-Zn-O thin film transistor. Appl Phys Lett 2011;98:033504. [6] Kim W-S, Lee Y-H, Cho Y-J, Kim B-K, Park KT, Kim O. Effect of wavelength and intensity of light on a-InGaZnO TFTs under negative bias illumination stress. ECS J Solid State Sci Technol 2017;6:Q6. [7] Lee Y-H, Seok S, Lee T-K, Kim S-H, Kim B-K, Kim O. Effect of Rising Edge during Dynamic Stress With Duty Ratio in Amorphous InGaZnO Thin Film Transistors. J Disp Technol 2016;12:1078. [8] Cho Y-J, Lee Y-H, Kim W-S, Kim B-K, Park KT, Kim O. Effect of illumination on the hump phenomenon in I-V characteristics of amorphous InGaZnO TFTs under positive gate-bias stress. Phys Status Solidi A 2017;214:1600503. [9] Choi S-H, Han M-K. Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress. Appl Phys Lett 2012;100:043503. [10] Choi S, Kim H, Jo C, Kim H-S, Choi S-J, Kim DM, et al. The effect of gate and drain fields on the competition between donor-like state creation and local electron trapping in In-Ga-Zn-O thin film transistors under current stress. IEEE Electron Device Lett 2015;36:1336. [11] Tsai M-Y, Chang T-C, Chu A-K, Chen T-C, Hsieh T-Y, Chen Y-T, et al. Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures. Thin Solid Films 2013;528:57. [12] Tsai M-Y, Chang T-C, Chu A-K, Chen T-C, Hsieh T-Y, Lin K-Y, et al. Asymmetric structure-induced hot-electron injection under hot-carrier stress in a-InGaZnO thin film transistor. Appl Phys Lett 2013;103:143508. [13] Mativenga M, Hong S, Jang J. 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[23] Chen B-W, Chang T-C, Hung Y-J, Hsieh T-Y, Tsai M-Y, Liao P-Y, et al. Investigation of temperature-dependent asymmetric degradation behavior induced by hot carrier effect in oxygen ambiance in In-Ga-Zn-O thin film transistors. Thin Solid Films 2014;572:33. [24] Jeong C-Y, Lee D, Song S-H, Kim JI, Lee J-H, Kwon H-I. A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization. Semicond Sci Technol 2014;29:045023. [25] Um JG, Mativenga M, Migliorato P, Jang J. Defect generation in amorphousindium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature. J Appl Phys 2014;115:134502. [26] Lee SM, Cho W-J, Park JT. Device Instability Under High Gate and Drain Biases in InGaZnO Thin Film Transistors. IEEE Trans Device Mater Reliab 2014;14:471. [27] Lee SM, Yu CG, Cho WJ, Park JT. Hot carrier degradation of InGaZnO thin film transistors under light illumination at the elevated temperature. Solid-State Electron 2012;72:88. [28] Oh H, Yoon SM, Ryu MK, Hwang CS, Yang S, Park SHK. Photon-accelerated negative bias instability involving subgap states creation in amorphous In-GaZn-O thin film transistor. Appl Phys Lett 2010;97:183502.
Woo-Sic Kim received the B.S. degree in electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Kyungbuk, Korea, in 2014, and is currently pursuing the Ph.D. degree in the Department of Electrical Engineering in POSTECH. His research interest is amorphous oxide thin-film transistors for application in display devices.
Ohyun Kim received the B.S. degree in electrical engineering from Seoul national University, in 1977, and the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1983. From 1983 to 1986, he was with Samsung Electronics, Korea, where he was involved in DRAM development. From 1989 to 1990, he was with Bell Communications Research, NJ, USA; during the period his research was focused on high speed devices. Since 1986, he has been a Professor in the Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH). His research interests include EUV lithography, polymer memories, AMOLEDs, Oxide TFTs, Graphene FETs and ReRAMs, and strained high-voltage MOSFETs.