Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance

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Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp

Advances on doping strategies for triple-gate finFETs and lateral gate-allaround nanowire FETs and their impact on device performance ⁎

A. Veloso , A. De Keersgieter, P. Matagne, N. Horiguchi, N. Collaert Imec, Kapeldreef 75, 3001 Leuven, Belgium

A R T I C L E I N F O

A BS T RAC T

Keywords: Triple-gate finFETs Gate-all-around nanowire FETs Doping Inversion-mode device Junctionless transistors

This paper reviews some of the key doping strategies pursued for scaled finFET devices fabrication, addressing several of the critical integration challenges faced by this device architecture with regard to junction engineering, parasitics and series resistance control and their impact on device performance, reliability and variability. We will therefore look into the extendibility possibilities of using conventional doping techniques such as ion implantation, explore the use of novel methods to enable conformal doping of the thin body of the devices, and also evaluate junctionless vs. inversion-mode type of transistors for gate-all-around nanowire FETs, which can essentially be considered as the ultimate scaling limit of triple-gate finFETs.

1. Introduction Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density [1]. Such extraordinary growth has however recently become in danger with the end of classical scaling, as it reached its limits in terms of electrostatics and short-channel effects control, thus requiring implementation of novel device concepts such as triple-gate finFETs into manufacturing [2,3] to allow continuance of Moore’s law. These devices had previously, and for a long time already, been considered an attractive scaling option thanks to their potential for improved electrostatics, with significantly reduced short-channel effects, and offer of enhanced performance at lower supply voltages [2– 24]. Following their introduction at the 22 nm technology node, they continue to be the subject of many technology innovations as part of the quest for increased performance and scalability. One of the critical integration challenges for these devices lies with their doping, on the several available options and opportunities for optimizing it, a wide topic which will be the focus of this paper. From a scalability perspective, we will also look at gate-all-around (GAA) nanowire (NW) FET devices (NWFETs) which, as illustrated in Fig. 1, represent the ultimate scaling limit of triple-gate finFETs and can be implemented in a lateral (with one or more lateral wires vertically stacked) or in a vertical configuration [24–36]. In this work, we will address only the first type as it is closer to finFETs in terms of processing and circuit layouts, whereas the move towards a vertical architecture will require more disruptive technological and design changes to be considered and implemented. Examples of scanning electron microscopy (SEM) and ⁎

transmission electron microscopy (TEM) images after full device fabrication of triple-gate finFETs and gate-all-around NWFETs (on silicon (Si)-on-insulator (SOI) and bulk Si substrates) are shown in Figs. 2 and 3, respectively. For clarity purposes, some critical device dimensions (CD) are also highlighted here, such as the fin height (Hfin), fin width (Wfin), gate length (Lgate), and the nanowire height (HNW), NW width (WNW) or NW diameter (dNW). 2. Doping schemes for inversion-mode (IM) devices 2.1. Conventional ion implantation (I/I): extension vs. extensionless Ion implantation (I/I) is a well-established and conventional technique used for introducing dopants into devices, being also one of the options for junctions formation in finFETs [4–17]. An important aspect to consider with regard to these devices is the impact of the I/I on the fin morphology, a widely studied and reported topic in the literature [4–12]. As an example of its implications, Fig. 4 shows a comparison of the source/drain (S/D) series resistance (RSD) of Si finFET devices built on SOI substrates using I/Is and Si epitaxial growth (SEG) in the S/D areas. A clear increase in RSD for narrower fin devices can be observed here, more strongly for NMOS than for PMOS which leads to drive current degradation and compromises high-speed operation. The origins of such behavior have been demonstrated to lie with the occurrence in the devices of a degradation of the fins crystalline integrity, reduced dopant activation and dopant retention. Indeed, by correlating the RSD data with the I/I conditions used and the fin morphology of the devices, this showed that there is a clear impact

Corresponding author. E-mail address: [email protected] (A. Veloso).

http://dx.doi.org/10.1016/j.mssp.2016.10.018 Received 19 July 2016; Received in revised form 7 October 2016; Accepted 11 October 2016 Available online xxxx 1369-8001/ © 2016 Elsevier Ltd. All rights reserved.

Please cite this article as: Veloso, A., Materials Science in Semiconductor Processing (2016), http://dx.doi.org/10.1016/j.mssp.2016.10.018

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fins, after undergoing a similar spike anneal, show a crystalline middle part similarly defective but also a top part consisting of polycrystalline silicon (poly-Si) grains. The implant conditions used to dope the fins can also impact the quality and the growth rate of the epi grown for raised S/D, a wellknown method to reduce RSD, and which will also have implications in terms of the devices contact resistance values [18,38,39,40]. This is shown, for example, by the HRTEM images in Fig. 6 where stacking faults are observed in the epi layer grown on previously doped Si fins, more so for the cases where strongly amorphizing I/I conditions had been used prior to junction anneal. By contrast, defect-free epi layers are grown when starting from Si fins with preserved crystal integrity as is the case in Fig. 6 for undoped Si fins. In addition, defective layers will also correspond to an additional source of variability for the devices electrical characteristics [7]. Device variability control is critical and it has become increasingly challenging for scaled devices. Although an improvement in VT mismatch performance has been obtained with the transition from planar bulk devices to finFETs [10], several sources of variability can and have been associated with the latter [7,10] which require attention and further improvements, namely: variations of the Lgate, Hfin, and Wfin dimensions, fluctuations in S/D resistance and S/D doping profiles, random dopants fluctuation in the channel, as well as some impact from variations in the gate stack. Fig. 7 shows an example of the effect of extensions optimization vs. Lgate on the σ(VTlin) of finFET devices built with a similar processing for the remaining flow. A reduction of the fin sidewalls roughness was also demonstrated in Ref. [7] to improve the mismatch in transistor gain β, σ(Δβ/β). Another important aspect to consider for ion implanted junctions is the tilt angle restrictions due to resist shadowing at tight pitches. For the transistors in a SRAM cell subject to double-sided tilted I/Is, this could mean, for instance, that the fins closer to the resist edge could be at risk of receiving only I/I from one direction, whereas other fins could get I/I from the two opposing directions, a situation prone to become even more problematic with shrinking design rules. To reduce nonuniformity of implanted dosage in neighboring fins, alternative approaches such as the single-sided I/I scheme illustrated in Fig. 8 have hence been proposed [14,16]. Kawasaki et al. reported in Ref. [14] improved σ(VT) for the finFET devices of a SRAM cell built with this scheme, thus enabling a more stable SRAM operation, although the cell transistors also corresponded to lower drive currents compared to the double-sided I/I case due to a higher extension resistance. An extensionless approach for device fabrication [23,24] is also an attractive option to consider, namely thanks to the better quality, defect-free SEG (hence also a smaller output resistance (Rout) varia-

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Fig. 1. Schematics of the two device architectures, on bulk or SOI substrates, evaluated in this paper: triple-gate finFETs (on top) and lateral GAA-NWFETs (at the bottom). The latter consist of one or more, vertically stacked, lateral nanowires and can be considered the ultimate scaling limit of finFETs.

of the amount of the fin that is amorphized by the implanted species, with poor or problematic recrystallization during junction anneal resulting in defect formation and poor dopant activation [4,5,10,37]. In Fig. 4, the stronger degradation seen for NMOS is thus explained by the fact that the arsenic (As)-implanted narrow fins were more affected than the boron difluoride (BF2) or boron (B)-implanted fins used in PMOS. A clear corroboration of these statements can be found for example in Fig. 5 which shows high-resolution TEM (HRTEM) images of sub-20 nm wide fins subject to different thermal treatments after having previously received shallow As implants or deep arsenic and phosphorous (As+P) co-implants. In both cases, after I/I, some amorphization of the Si fins takes place (stronger for the deeper I/I condition), with regrowth after anneal appearing to be faster in the middle of the fin and slower or suppressed at the fin sidewall surfaces. And although, after 1050 °C spike anneal, the fins are fully recrystallized for the shallow I/I condition, twin boundary defects originating from the sidewall surfaces are visible in the TEM images in the regrown region. The situation is aggravated for the deeper I/I case, where the

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Fig. 4. RSD vs. Wfin for n and p-type triple-gate finFETs. RSD was extracted by extrapolating to Lgate=0 the total resistance R measured at |VGS|=3 V and |VDS|=50 mV.

Fig. 6. HRTEM images taken across a fin after SEG growth: 1) on an undoped fin (top row); 2) after As extension I/I (done prior to SEG), (As and P) HDD co-I/I, and 1050 °C spike anneal (bottom row). A clear dependency of the SEG growth rate and quality on the implant conditions is seen here.

Fig. 5. HRTEM images of sub-20 nm wide fins which were subjected to different anneal treatments after receiving shallow (on the left) or deep (on the right) implants.

bility) that can be expected to be obtained since it starts from undoped fins [7,10,12]. A schematic comparison of this approach with the standard one that relies on extension and HDD I/Is for junction formation is shown in Fig. 9. Another key advantage of the extensionless scheme is the reduced cost and cycle time it enables, with two less critical I/I photos. It however requires a tighter spacer CD (width and shape) control, with Fig. 10 showing examples of TEM images of devices with and without SEG faceting, which were hence defined depending on the shape of the spacers after patterning and the diluted hydrogen fluoride (dHF) time used in the epi pre-clean step. The SEG shape is of course important not only as it impacts the final junction profile obtained on these extensionless devices, but also as it can be used as a knob to reduce RSD and minimize gate-to-S/D parasitic capacitance [7,38,39]. Fig. 11 shows a comparison of the intrinsic transistor performance (ITP) characteristics for PMOS devices built with or without extensions

Fig. 7. Measured (symbols) and calculated (solid lines) σ(VTlin) vs. Lgate for devices with different extensions, with the corresponding VTlin-Lgate curves shown in the inset. Interdie variability can be explained by the Lgate spread, with σ(Lgate)=2.2 nm for the example presented here.

according to the process flow schematically illustrated in Fig. 12 which has the added flexibility to allow fabrication of triple-gate finFETs or GAA-NWFETs [24,25,41]. The latter type of devices is obtained at

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facets as mentioned before) and tuned I/I conditions, comparable device characteristics can be obtained for the two doping schemes (with or without extensions). Furthermore, GAA-NWFETs clearly outperform triple-gate finFETs when normalizing ION-IOFF per footprint, with GAA-NWFET devices corresponding to a larger effective width (Weff) for similar layout dimensions. For the devices represented in Fig. 11, each consists of 5-(fin or wire) of 22–23 nm height (Hfin or HNW), ∼1– 2 nm≤width (Wfin or WNW) < 20 nm, and their effective width was calculated as 5×(2Hfin+Wfin) for triple-gate finFETs or 5×(2HNW+2WNW) for GAA-NWFETs. In our previous works [23,24], we have also demonstrated that extensionless devices can moreover exhibit lower IOFF values as compared to those of reference devices, as well as show attractive performances when incorporated into circuits such as ring oscillators (RO) and SRAMs. Another particularly attractive feature of this type of devices is their potential for improved reliability thanks to a lower oxide field (Eox) at operation conditions. This has indeed been confirmed experimentally with bias-temperature-instability (BTI) and low-frequency noise measurement results [24,41]. As an example, Fig. 13 shows the negative-bias-temperature-instability (NBTI) results obtained for PMOS devices at 125 ºC, where the post-stress ID was measured with minimized delay time (∼1 ms) to reduce recovery effects and converted into a VT shift [42,43]. The data in this figure show that extensionless devices could withstand a clearly higher stress voltage (VG, stress), for a given ΔVT, than the reference GAA-NWFETs. Also, using |ΔVT|=50 mV as criterion for BTI lifetime prediction, this points to a substantially larger maximum allowed overdrive voltage (Voper), at ten years lifetime, for extensionless devices. Furthermore, the extensionless approach can also be advantageous in terms of ensuring an improved process robustness in the context of the GAA-NWFET devices fabrication scheme as described in this paper, wherein control of the lateral BOX recess during the fins release process (at RMG module) for wires formation is also important for reliability purposes. Indeed, technology computer-aided design (TCAD) simulation results depicted in Fig. 14 show that, in case of excessive lateral BOX recess, this leads to: 1) a higher Eox at the NWFET bottomgate edges; and 2) a considerably smaller Eox increase occurs for extensionless devices than for reference GAA-NWFETs. As a result, extensionless GAA-NWFETs will be substantially less impacted, performance and reliability wise, by process variations at the GAA formation module. In addition, given the sensitivity of several etch processes with regard to the type and amount of dopants present in silicon, a smaller impact of the etch process used to release the wires on the edges of the uncovered wires is thus expected to occur when skipping extensions (for devices on SOI or bulk Si substrates). The potential of the extensionless scheme has also been explored in the context of alternative emerging memory architectures such as the one-transistor floating body RAM (1T-FBRAM) [23,44–47]. Fig. 15 shows the simulated lateral electric field for several Lgate∼70 nm transistors (planar devices on ultra-thin BOX (UTBB)) in the hold ‘0’ state, with a lower maximum field at gate edges being calculated for the extensionless type of devices, more so if assuming SEG has no facets. As a result, ∼5× retention time improvement for 1T-FBRAM extensionless devices with faceted SEG was measured in Ref. [23] (Fig. 16), with further improvement expected to occur with facet-less SEG due to its even lower maximum field. Retention is determined by the ‘0’ state degradation (holes generation occurring during ‘0’ state hold), with band-to-band tunneling and trap-assisted-tunneling mechanisms limiting the retention time [46] and responsible for the observed field dependence. The similar retention time distributions obtained for the various devices evaluated in Fig. 16 suggest thus the presence of similar traps and generation/recombination (GR) centers distributions. Overall, several attractive features have thus been demonstrated for the extensionless scheme in both a logic and memory context, with device optimization depending on the targeted application.

Fig. 8. Ion implantation strategies: a) low-tilt, double-sided I/I; and b) high-tilt, singlesided I/I. Implant angles α and θ are limited by the resist height, fin height, fin pitch, and overlay control.

Fig. 9. Schematics of two approaches for junction formation using conventional I/I: reference devices with extension and HDD I/Is (on top) vs. extensionless devices (at the bottom).

Fig. 10. TEM images highlight the epitaxial Si grown on the S/D regions of SOI based finFETs with (on the right) or without (on the left) facets, depending on the spacers shape and the epi pre-clean treatment used.

replacement metal gate (RMG) module by simply removing with dHF the buried oxide layer (BOX) under the fins in areas previously covered by the dummy-gates, while the rest of the wafer remains protected by the inter-layer-dielectric-level zero (ILD0) used at RMG module. Note that this is a process also suitable for dense pitches since there is no need for S/D landing pads to anchor the suspended wires [28]. A similar gate stack can and was used for the different type of devices hereby built with this integration flow: interlayer-dielectric (IL)-SiO2/ HfO2 followed by the effective work function (EWF)-metal (TiN or a TiAl-based stack) and tungsten (W) fill-metal depositions. An example of a TEM image taken across a wire for a p-type GAA-NWFET device with TiN as the EWF-metal was previously shown in Fig. 3a. The data in Fig. 11 show that with the use of optimized spacers, S/D epi (e.g., epi

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Fig. 11. Comparable ITP characteristics are obtained for inversion-mode PMOS devices built with or without extensions. GAA-NWFETs outperform triple-gate finFETs when ION-IOFF is normalized to footprint, with Weff(GAA-NWFET) > Weff(triple-gate finFET) for similar layout dimensions and HNW∼22 nm, Hfin∼23 nm.

(Hfin=40 nm), at the expense of some reduction in the ION/IOFF ratio and a small (eventually leveling off) DIBL increase. The use of in-situ doped S/D epi in finFETs is also widely covered in the literature for purposes of strain, S/D and contact resistivities [2,48–52]. Using Si:P S/D epi for NMOS instead of implanted Si epi can be advantageous in terms of having a higher P activation efficiency than that obtained via P I/I and also because of its potential for a better controlled box-shaped profile, while avoiding I/I induced damage [48,52]. Yu et al. [50] also showed that low contact resistivity (ρc) values for n-type Si, down to 1.5×10−9 Ω.cm2 could be achieved on a Si:P epitaxial layer. Such was obtained by combining heavily in-situ P doped (2×1021 at.cm−3) epi on S/D areas with a dynamic surface anneal (DSA) treatment and a Ge pre-amorphization I/I step followed by Ti silicidation (Ge PAI + TiSix) in the contacts. For PMOS, SiGe S/D have been employed to induce compressive stress in the channel and hence boost performance [2]. Furthermore, ultra-low contact resistivity values of ∼2×10−9 Ω.cm2 on in-situ B doped Si0.3Ge0.7 S/D have also been reported in Ref. [51] by using a similar Ti based pre-contact amorphization I/I (PCAI) and post-metal anneal (PMA) technique as that reported in Ref. [50] for Si:P epi. In those devices, the Ti/TiN layers (used as a liner before the W deposition in the contact vias) were deposited prior to the PMA and after the Ge PCAI.

Fig. 12. Schematics of the process flow used for fabrication of triple-gate finFET and lateral GAA-NWFET devices using conventional junctions or an extensionless approach.

2.2.2. Hot I/I Controlling the Si wafer temperature during I/I has also been the subject of attention and various studies [53–56] as a possible knob for crystallographic damage engineering, besides the basic and essential need to prevent photo resist burning or melting. Fig. 19 shows how, by increasing the Si wafer temperature during I/I (hot I/I) up to a certain target value, this can lead to a considerable reduction of the depth of the amorphous layer created on the Si substrate for both P and As implants, with less than 1 nm amorphization depth achievable on blanket wafers. This figure also shows that, as the mass and/or energy of the implant species is increased, a higher I/I temperature is required to minimize or avoid amorphization. Less fin damage during hot extension I/I (an increasingly more critical issue for shrinking fin dimensions) was demonstrated in Ref. [56] and is shown in Fig. 20 to enable finFET performance improvement, with better results obtained using P vs. As as the implanted species for NMOS extensions formation, as it allows a lower implant damage thanks to its smaller atomic mass.

Fig. 13. Extensionless GAA-NWFETs show improved NBTI performance compared to reference inversion-mode devices built with conventional junctions.

2.2. Novel techniques 2.2.1. Dopants diffusion from in-situ doped epi An alternative extensionless and I/I-free doping technique is illustrated in Fig. 17, where a rapid thermal anneal (RTA) process step is used to drive dopants from the in-situ doped SEG grown on the S/D areas (after fin recess) of a bulk Si finFET device. The RTA condition determines in this case the dopant (As in Fig. 17) diffusion profile and the resulting doping contours in the top and vertical channels. A simplified TCAD assessment of this scheme [23] shows in Fig. 18 that increasing the Si-recess depth (from 10 to 40 nm) prior to SEG growth would lead to higher drive currents due to a more effective fin doping

2.2.3. Conformal doping schemes As part of the quest for improving doping uniformity in narrower and taller fins and shrinking fin pitch, for which tilt restrictions of I/I have also become increasingly challenging, several other innovative doping schemes [57–71] have been proposed such as conformal plasma doping [62–64], molecular monolayer doping (MLD) [65– 5

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Fig. 14. TCAD simulations predict a lower oxide field (Eox) at the (SOI based) NWFET bottom-gate edges for extensionless (Extless-GAA) vs. conventional (Ext-GAA) inversion-mode devices in case of excessive lateral BOX recess during the fins release process at RMG module.

Fig. 15. Lateral electric field simulated in the hold ‘0’ state (VG=-2.5 V, VB=2.5 V, VS=VD=0 V) for Lgate∼70 nm UTBB FBRAM devices. The maximum field at gate edges is lower for extensionless devices built with SEG without facets.

Fig. 17. On top, schematics of an approach to fabricate devices using in-situ doped SEG for junctions formation. At the bottom, contours of net active doping for two diffusion profiles (corresponding to two different RTA conditions) in bulk Si finFET devices.

MLD applied to SOI based finFETs (with 20 nm wide fins and Lgate∼40 nm) was demonstrated in Ref. [67]. Secondary ion mass spectrometry (SIMS) analysis of dopant profiles showed here that a steeper junction abruptness could be obtained with MLD (0.6 nm/dec) as compared to the cases where I/I or in-situ doped S/D epi were used. As an example of these novel doping techniques, the schematics in Fig. 21 illustrate the key processing steps for NMOS extension formation by PSG doping, as reported in Ref. [71]: 1) a PSG and a SiO2 cap layers are deposited in the same process chamber without vacuum break in-between depositions, with SIMS analysis confirming the presence of a high P concentration (6×1021 at cm−3) in the PSG layer. The two layers thicknesses are uniform from the bottom to the top of the fins, and at all fin sidewalls, to ensure uniform doping; 2) a drive-in anneal, at 1035 °C for 1.5 s, is then used to uniformly diffuse P into the Si fins, without induced Si damage, as confirmed by the TEM images in Fig. 22. The SiO2 cap layer presence is important to prevent P from out diffusing and is removed after the drive-in anneal by using dHF. This is done with high selectivity towards the other layers present on the wafer. For the devices reported here and in Ref. [71], a second anneal (also 1.5 s at 1035 °C) was used after HDD S/D I/I. Electrically, the data in Fig. 23 show that a 20% ION boost for n-type bulk Si finFETs

Fig. 16. Extensionless UTBB FBRAM devices show improved retention times (data shown for Lgate∼70 nm), with further improvement expected with the use of SEG without facets.

69], doping deposition and knock-in process [70], and doping by a doped silicate glass (e.g., P doped silicate glass (PSG) for NMOS) [71]. Solid-source doping has also been reported as a key feature for the implementation into manufacturing of bulk finFETs at 14 nm technology node by enabling better optimization of the punch-through stopper dopants [3].

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consisting of 5 nm wide fins (with Lgate in the 24–34 nm range) was achieved when using PSG doping instead of P I/I for the extensions formation.

spacers width=10nm Lgate=20nm 10nm doped HFin=40nm SEG W Fin=15nm

3. Junctionless devices Junctionless (JL) transistors have been receiving increased attention as a potential attractive alternative to conventional inversionmode (IM) devices for several type of applications [24,25,41,49,68,69,72–81]. Their process simplicity, by alleviating junction formation challenges, makes them particularly attractive for use, e.g.: in vertical GAA-NWFETs and stacked vertical GAA-NWFETs [25,49], in sequential 3D integration as the top-level FETs [69,82], and overall in a 3D sequential stacking approach (vertical or horizontal channel) [69,81]. Junctionless transistors are also of importance in the context of 3D stacked NAND flash memories [74,75], with poly-Si channel based JL devices also being extensively reported in the literature [68,69,74–81]. With regard to the doping techniques used to build these devices, several options have been reported in the literature [24,25,41,49,68,69]. For example, Ref. [69] refers to the use of a damage-free conformal molecular monolayer doping (MLD) method to form a shell doping profile (SDP) on thin film transistors (finTFT), followed by a microwave annealing (MWA) step to drive in and partially activate the MLD dopants, and a CO2-laser spike annealing (COLSA) step to further enhance the dopant activation process while helping to recover surface defects originated at fin patterning. Poly-Si and bulk Si JL finTFT transistors thus obtained were demonstrated in Ref. [69] to yield reduced SS, higher ION (with 160% improvement compared to SDP-finTFTs without COLSA) and larger ION/IOFF ratios ( > 107). Conventional I/I and in-situ doped Si epi have also been reported as techniques used to build JL GAA-NWFET devices in lateral [24,25,41] or vertical configurations [25,49], respectively. The JL lateral devices here discussed essentially share the process flow previously described in section 2.1., in Fig. 12. The key difference with the baseline GAANWFET flow (highlighted in Fig. 24) is that, for JL, the channel doping was obtained via ion implantation (B I/I for PMOS, P I/I for NMOS) after fins formation and dummy-gate dielectric deposition. This was followed by a spike anneal, after which device processing continued according to the baseline flow sequence, with dummy-gate electrode (aSi) deposition, dummy-gate planarization (using a-Si chemical mechanical polishing (CMP)) and patterning being the next defined steps. A similar gate stack was used in JL and reference inversion-mode type of devices, as obtained by a RMG high-k last (RMG-HKL) process and consisting of: IL-SiO2 formed by O3-oxidation and a high-k dielectric (HfO2) grown by atomic layer deposition (ALD), followed by the EWFmetal TiN and the fill-metal W. The ID-VG characteristics in Fig. 25 illustrate a key trade-off for controlling and designing JL GAA-NWFET devices: NW doping vs. NW size, with higher doping requiring a smaller NW size to be able to fully turn off the device. The NW height (HNW) in the evaluated lateral NWFETs was kept constant at ∼22 nm, while the NW width (WNW) ranged from ∼2 to ∼25 nm. Besides process simplicity, JL devices also offer the potential of improved reliability thanks to the possibility of a lower oxide field (Eox), for optimized doping of the NWs, at operating conditions. This is indeed confirmed experimentally by the negative and positive biastemperature-instability (N/PBTI) results in Fig. 26 which were obtained for PMOS/NMOS devices at 125 ºC, and where the post-stress ID was measured with minimized delay time (∼1 ms) to reduce recovery effects and converted into a VT shift [42,43]. The data show that JL (and under some conditions also extensionless inversion-mode devices) could withstand a clearly higher stress voltage (VG,stress), for a given ΔVT, than reference (with extensions) inversion-mode GAANWFETs. Using |ΔVT|=50 mV as criterion for BTI lifetime prediction,

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Fig. 21. Schematics of the key process steps to form extensions in n-type bulk Si finFETs using doping by a P doped silicate glass (PSG), with cross-section cuts taken across the gates (a) and fins (b).

SOI substrate Si thinning + fin patterning Dummy-gate dielectric (SiO2) deposition Channels doping by I/Is + anneal (JL only) Dummy a-Si dep + CMP + gate patterning Extensions I/Is (only for some IM devices) Spacers + S/D SEG + HDDs I/Is + RTA CESL + ILD0 deposition/CMP Dummy-gate removal RMG-HKL module fins release Gate stack deposition + metal-CMP S/D silicidation through vias in CESL/ILD0 CESL + ILD1 + W-filled contacts BEOL

Fig. 22. TEM images taken across fins after: a) PSG and SiO2 cap layers deposition; b) drive-in anneal and removal by dHF. In both cases, the wafers were coated with a SOC layer prior to the TEM analysis.

Fig. 24. Schematics of the process flow used for fabrication of junctionless and inversion-mode (with or without extensions) lateral GAA-NWFET devices.

Fig. 23. A 20% ION improvement is obtained for n-type bulk Si finFET devices (Wfin∼5 nm and Lgate=24–34 nm) built using PSG doping instead of P I/I for the extensions formation (ION @ VG−VT=0.6 V, IOFF @ VG−VT=−0.3 V, with VDS=0.9 V).

this means that the maximum allowed overdrive voltage (Voper), at ten years lifetime, is predicted to be substantially larger for both NMOS and PMOS JL devices. These BTI results agree quite well with the lowfrequency (LF) noise results plotted in Fig. 27, which show lower normalized input-referred noise spectral density values for JL vs. IM GAA-NWFETs, for both NMOS and PMOS, indicating less traps/ defects present. Moreover, for p-type JL devices, a small noise reduction was also measured with decreasing NW doping, with the noise origin identified in Ref. [25] to be due to carrier number fluctuations or oxide trapping with correlated mobility fluctuations. In addition, also improved hot carrier (HC) reliability behavior was measured for JL devices [41,73], as shown by the examples of ID-VG

Fig. 25. ID-VG characteristics of p-type JL lateral GAA-NWFET devices with varying NW dimensions and NW doping.

curves plotted in Fig. 28 for JL and reference IM GAA-NWFETs, at room temperature (RT), before and after applying a HC stress, for 2000 s, at VG=VD=1.5 V (on state HC). Indeed, considerably less degradation was observed for the JL devices, which exhibit smaller VT shifts after HC stress and for various stress times (Fig. 29a). This indicates occurrence of reduced HC injection into the gate dielectric

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Fig. 27. a) Junctionless GAA-NWFETs exhibit lower noise than inversion-mode devices, with a small dependency on NW doping (reduced noise with decreased NW doping) seen for PMOS. Two versions of IM GAA-NWFETs with similar NW sizes were used for the comparison: #2 and #1, corresponding to devices built with or without extensions, respectively. Overall, in terms of noise behavior, they are both outperformed by JL GAA-NWFETs, for NMOS and PMOS. b) Example of the LF noise spectra measured for a p-type JL GAA-NWFET device.

Fig. 28. Examples of ID vs. VG curves, at RT, before and after applying a HC stress, at VG=VD=1.5 V, for: IM (left) vs. JL (right) n-type GAA-NWFETs. The data show that considerably less degradation is measured for JL devices.

From a DC performance point of view, some of the key trade-offs/ knobs for optimum JL operation are highlighted by the TCAD results in Fig. 30: 1) for uniformly doped wires, ION is expected to peak at a certain NW doping concentration which varies with the size of the NW (i.e., the NW diameter (dNW)) and is higher for smaller NWs; 2) even though JL devices do not require junction formation, it is still desirable to introduce highly doped S/D areas for RSD reduction (and hence

bulk defects as compared to the case of reference IM devices. At the same time, the reduced ΔSS after HC stress for JL GAA-NWFETs shown in Fig. 29b also suggests less interface defects generation takes place for this type of devices. As for the off state HC reliability behavior, Ref. [73] shows that the HC degradation for JL devices is more limited in the off state than in the on state, with significantly reduced gate dielectric defect charge generation taking place in off state.

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Fig. 29. a) N-type JL GAA-NWFETs show smaller VT shifts after being subjected to HC stress, and for various stress times, than n-type IM devices. This indicates reduced HC injection into the gate dielectric bulk defects in the JL case. b) In addition, n-type JL GAA-NWFETs also show reduced ΔSS after HC stress which suggests less interface defects generation for these devices.

Fig. 30. TCAD evaluation of: a) impact of the NW doping and NW size on the drive current (ION) of p-type junctionless devices at VT overdrive (VG−VT=−0.7 V, VDS=−1.0 V). The comparison is done at fixed IOFF=100 nA/μm, and Lgate=3×dNW; b) VT modulation of JL GAA-NWFETs by EWF engineering and by varying the NW doping vs. NW size.

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Fig. 32. ION, IOFF at VT overdrive for n-type IM vs. JL lateral GAA-NWFETs (WNW < 25 nm, Lgate∼48 nm). JL devices can exhibit lower IOFF values, and for the smaller NWs a higher NW doping can help to increase ION without impacting IOFF.

time, it is worthwhile to highlight again the fact that JL show excellent electrostatics (SS, DIBL) compared to IM NWFETs, provided the NW size is kept sufficiently small (WNW≤10 nm) when its doping is higher. Comparing the impact on ION and IOFF for JL vs. IM NWFET devices, Fig. 32 shows that JL can exhibit lower IOFF values for a given NW size, and that indeed higher NW doping can help to increase ION though it is only interesting for the smaller NWs to avoid impacting IOFF. The lower off state current values is another very attractive feature of these devices, opening up further possibilities with regard to their potential use for low power applications [24,25]. A last and important point to address here with regard to this topic

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improved ION) especially for the smaller and less doped nanowires; 3) VT modulation by varying the NW doping is more pronounced for larger NWs, with gate stack EWF engineering predicted to yield similar ΔVTs for NWs of different size and doping. These trends have been confirmed experimentally in Refs. [24,25]. As an example, Fig. 31 shows the impact on VT, DIBL and SS for p-type JL vs. two versions of IM lateral GAA-NWFETs with similar NW size dimensions (WNW and HNW). Here, in agreement with the TCAD predictions, ΔVT vs. ΔWNW has a less pronounced slope for lowly doped JL NWFETs, becoming steeper for increased NW doping. At the same

Low Mid High doping (JL-GAA)

Fig. 31. JL vs. IM lateral GAA-NWFETs can show comparable, excellent electrostatics (SS, DIBL). For JL devices, the VT, SS and DIBL dependence on the NW size is more pronounced for the higher doped wires.

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A. Veloso et al. [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82]

is variability, which is generally a concern when considering junctionless devices. In Ref. [25] we have indeed shown that the VT mismatch performance of n-type JL GAA-NWFETs degraded with increased NW doping and in comparison with IM GAA-NWFETs, but we have also demonstrated that the impact seemed less for smaller NWs (WNW≤10 nm), for which the JL concept is most suitable (allowing a higher NW doping while keeping excellent electrostatics), and also for PMOS. 4. Conclusions In this review, we covered several of the key doping strategies used for scaled triple-gate finFET devices fabrication, including also an assessment of their extendibility to GAA-NWFETs which can be considered their ultimate scaling limit. In parallel with addressing various critical integration challenges with regard to junction engineering, parasitics and series resistance control, we also pursued an evaluation of the impact on device performance, reliability and variability of using conventional I/I and novel conformal doping techniques to dope increasingly scaled thin-body devices. Lastly, we explored the junctionless concept as a simpler and attractive alternative option vs. inversion-mode FETs for obtaining improved reliability and low power devices, of increasingly high interest in the general context of the various 3D architectures and/or 3D sequential stacking approaches currently under consideration for future devices and technological nodes. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]

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