- Email: [email protected]
Development and characterisation of nanowire-based FETs
Microelectronics Reliability 51 (2011) 1162–1165
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Development and characterisation of nanowire-based FETs Michał Zaborowski ⇑, Daniel Tomaszewski, Piotr Dumania, Piotr Grabiec Institute of Electron Technology (ITE), al. Lotników 32/46, 02-668 Warsaw, Poland
a r t i c l e
i n f o
Article history: Received 10 December 2010 Received in revised form 18 February 2011 Accepted 21 February 2011 Available online 23 March 2011
a b s t r a c t Development of Si nanowire-based FETs, suitable for sensor applications is reported. Process sequences for SOI and bulk p-channel FinFETs are described. SEM observations of the fabricated devices (180 nm wide, 87 nm or 175 nm high) are presented and discussed. Electrical characteristics measurements and basic characterisation results obtained for these devices are described. A procedure for serial resistance extraction has been mentioned in more detail, due to its high value inherent in the process used. Several aspects of the device sensitivity to front- and back-gate control have been discussed from the point of view of its application in biochemical detectors. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction
2. Development of technology
Standard bulk and SOI CMOS technologies have been adopted in ITE for fabrication of integrated Ion-Sensitive Field-Effect Transistor (ISFET) sensors [1] and of discrete large gate area ISFETs [2]. On the other hand it can be noted that the multi-gate MOSFETs have been extensively investigated in the last several years, due to perspectives for application in the sub-100 nm integrated circuits (ICs). Because of their better gate control over channel conduction as compared to planar MOSFETs, they are predestined for low-voltage applications. Among them triple-gate and double-gate MOSFETs (e.g. FinFETs) conducting along walls of a narrow silicon wire seem to be the most promising. Due to an almost ideal gate control and due to a small surface area these devices are expected to have also better sensitivity toward electrically active molecules [3]. Lithography-based patterning methods in a nano-scale reveal mostly a strong dependence of apparatus expenses on a smallest attainable pattern. Also nanoimprint lithography needs a relatively expensive mould. In order to avoid high cost of patterning a number of techniques have been developed, where the pattern width is determined not by the lithography step but by other methods. A widely used spacer technique [4] is a good example. Other class of techniques has been also developed, where Au or Ag are used for nanowires fabrication. Therefore it has a limited range of application [5,6]. Development of easily manufacturable Si-nanowirebased FETs suitable for sensor applications use has been the aim of this work.
ISFET-like devices have been fabricated in ITE clean-room using a NMOS process, described earlier in detail [2]. The device size down-scaling is possible but limited at 2–3 lm level determined by capabilities of the local equipment. In order to overcome these very conservative limitations and acquire capability to fabricate silicon narrow lines (wires), a Pattern Definition by Edge Oxidation (PaDEOx) method has been developed [7]. Width of the wire is controlled by conditions of lateral oxidation under a nitride mask, which appears by the LOCal Oxidation of Silicon (LOCOS) process. The minimum width of the Si line available in PaDEOx is close to 20 nm, irrespectively of a lithography technique. In the frame of this work, two PMOSFET processes have been developed with use of the PaDEOx method for definition of transistor channels. Bulk FinFET-type devices and SOI FinFETs have been fabricated in a very similar way. Flow charts of both processes are presented schematically in Table 1. The manufactured FinFET structures are illustrated in Fig. 1. In the reported experiment the n-type (100) SOI wafers with a 340 nm thick device layer of 0.1 X cm resistivity and 400 nm thick buried oxide (BOX) have been used for fabrication of SOI FinFETs. As the result of the operation no. 6 of the SOI FinFET processing (see Table 1) the closed-loop narrow oxide line has been obtained. It originates from ‘‘bird’s beak’’ region formed around the Si3N4/SiO2 stack, because the oxide layer in this region is thicker than the one growing at the neighbouring plane silicon surface. The narrow oxide line mentioned above serves as a mask in the Bosch plasma etching of silicon. As a result of the etching step a pair of transistor narrow channels has been formed between S and D contact areas (step no. 8 in Table 1 for SOI FinFETs). The gate oxidation and poly-Si gate preparation have
⇑ Corresponding author. E-mail address: [email protected] (M. Zaborowski). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.02.017
M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
1163
Table 1 Fabrication sequence of the transistors. SOI devices 1
Oxidation I xOx ¼ 135 nm
2 3
Nitride deposition 65 nm Nitride and oxide photolithography and etching Oxidation II 144 nm Nitride etching Oxide partially etching – thin oxide stays still in bird’s beak region Lithography of S/D contact surroundings Plasma etching of Si device layer through oxide and resist masks Gate oxidation 26 nm Poly-Si gate deposition, doping and patterning B+ S/D implantation BPSG passivation Contact etching Metallization deposition and patterning
4 5 6
7 8
9 10 11 12 13 14
Bulk devices 1 2 3 4 5 6 7 8
9 10
Initial oxidation B+ S/D implantation Oxidation I xOx ¼ 165 nm Nitride deposition 65 nm Nitride and oxide photolithography and etching Oxidation II 175 nm Nitride etching Oxide partially etching – thin oxide stays still in bird’s beak region Lithography of S/D contact surroundings Plasma etching of bulk Si through oxide and resist masks
11 12
Gate oxidation 29 nm Poly-Si gate deposition, doping and patterning
13 14 15
BPSG passivation Contact etching Metallization deposition and patterning
been the next steps. These have been followed by boron implantation across the gate oxide to form source and drain areas in selfaligned process. BPSG passivation and Ti:W/Al metallization have completed the process sequence on the SOI wafers. The device structure has been thoroughly examined via SEM observations. In order to reveal details of the Si-wire morphology the devices under observation have been post-processed. Passivating dielectric layers have been removed in HF bath. As may be seen in Fig. 2a the resulting transistors consist of two separate fin-shaped Si wires, serving as MOSFET channels. Height of these wires is approximately equal to 175 nm (Fig. 2b). However in order to obtain wires with different heights a group of the devices has been additionally oxidized. Their final height is 87 nm (Fig. 2c). Width of all the fins is 180 nm. Similar fin-type FETs have been developed using the standard bulk Si wafers. Main differences between the SOI and bulk processes are mentioned in Table 1. The preparation of drain and source regions has been shifted to the early beginning of the process sequence. Therefore a special care has been required in further thermal processing in order to form source/drain junction shallow enough. Due to this the fabrication has been preceded by SILVACO/ATHENA 1-D simulation (Fig. 3). This has allowed to design a shallow distribution of the B+ dopant, and the p–n junctions are expected to remain in the thin fins only, not in the bulk substrate. However, due to the changed source/drain
Fig. 2. SEM micrographs of double-fin SOI FETs with 180 nm wide fins. Passivation oxides have been removed in diluted HF: (a) general view; (b) single fin of ca 175 nm height; (c) single fin of 87 nm height, lowered by additional oxidation step.
preparation sequence, the bulk FinFET process is not self-aligned. So special efforts should be made to align the gate to diffusion patterns. The bulk FinFET structure after removing dielectric passivation (in order to clarify the view) is shown in Fig. 4. 3. Electrical characterisation Drain current (ID) versus gate and drain voltage (VGS, VDS) characteristics have been measured for series of FinFETs using a standard Keithley System 93 I–V setup. A test structure layout allows for evaluation of parameters of double fin devices with different
Fig. 1. Schematic view of the fabricated devices: (a) double-fin SOI FinFET; (b) double-fin bulk FinFET. Source contact has been cut off to demonstrate a pair of the fin-shape Si channels.
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M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
Fig. 3. Final 1-D distribution of doping concentration (cm3) versus depth (lm) in the bulk-type p MOSFET calculated using SILVACO/ATHENA.
Fig. 5. Transfer |ID(VGS)|, and transconductance gM(VGS) characteristics of bulk-type double-fin MOSFETs (shown in Fig. 4, fin length = 3 lm, fin separation = 6 lm).
proportionally to the fin heights, 175 nm and 87 nm. It may be concluded, that the current density becomes invariant. The wide subthreshold slope range mentioned above originates probably from wide spread of device local sizes, which have been achieved by subtraction of a part of device layer of the SOI wafer. It should be pointed out that the spread of the thinner device characteristics is larger than of the thicker ones. The test structure has been used also for measurements of resistance of the same pair of nanowires, which serve as the transistor channels. The resistors of length of 60 lm, 120 lm and 180 lm have been examined in several locations in the wafer. The resistance R can be described by an equation:
R ¼ Rc þ Lq=2A
Fig. 4. Bulk FinFET: one of the bulk fins after etching of passivation layer.
fin length and different fin separation (distance between the fins). Fin width has been a process controlled parameter. Both bulk and SOI transistors have been fabricated using this layout. The bulk double-fin FETs exhibit a reasonable reproducibility – Fig. 5, however small distortions of the characteristics shape may be noticed. There is a kind of hump in the medium inversion range of transconductance curves, which is supposed to be related to subsequent turning-on of different conduction paths in the device areas. More than one threshold voltage can be found for these devices. Measurements of transistors of two different separations between their fins allow to state that the main path for electric current flow is situated inside the fins. The SOI double-fin FinFETs also reveal correct electrical characteristics. The calculated value of the threshold voltage is in the range –2.4 to –2.2 V, and the subthreshold slope is in the range 100–150 mV/dec. I–V curves of two devices of different fin heights are shown in Fig. 6. The drain current is scaled nearly twice –
ð1Þ
where Rc is a sum of resistance of the two contacts, L and A are the length and cross-section area of the fin, respectively, and q is the fin mean resistivity. Mean resistance of the two contacts can be determined graphically – Fig. 7. Mean value and standard deviation of Rc parameter for 175 nmthick resistors have been estimated as 3.5 kX, and 0.8 kX, respectively. For the 87 nm-thick resistors these parameter are 7.4 kX and 1.3 kX. Next, after subtraction of the contact resistance fin resistance per unit length has been calculated. It has a mean value of 1.56 kX/lm for the individual thicker fin, whereas for the thinner fin – 2.72 kX/lm. A ratio of these values varies between 1.64 and 2.11. It corresponds to the ratio between fin mean heights (175 nm/87 nm 2) but depends on the location in the wafer. This is mainly due to differences of thickness of the SOI layer across the wafer. ISFET-type sensors may be fabricated using the above-described technology. Possibility of modification of device characteristics has been examined using PMOSFETs in 100 nm thick SOI layer on 400 nm BOX (Fig. 8). Poly-Si gate characteristics have emulated liquid gate characteristics. Two families of transfer characteristics have been measured: ID(VGS) for VBS = 0 and ID(VBS) for VGS = 0. They are shown together in Fig. 8 using arbitrary ratio of the VGS to VBS scale. It has been revealed that biasing the substrate allows for a change of operating point and a curve slope. A visible difference between ID control efficiencies by the front gate voltage (VGS) and by the back gate (substrate) voltage (VBS) can be directly related to a ratio of thicknesses of the gate and box oxides.
1165
M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
(a)
3,0E+5
thin & thick SOI finFETs 0,0e+0
2,5E+5
-5,0e-6
2,0E+5
1,5E+5
-1,0e-5
ID [ A ]
1,0E+5
contact res. of thin resistors
5,0E+4
-1,5e-5
0,0E+0 -5,0E-5
VGS= -2 V VGS= -3 V VGS= -4 V VGS= -5 V
-2,0e-5
contact res. of thick resistors 0,0E+0
5,0E-5
1,0E-4
1,5E-4
2,0E-4
L[m] Fig. 7. Resistances and regression lines versus double fin resistor length; the devices have been fabricated on SOI substrates.
-2,5e-5 -5
-4
-3
-2
-1
0
VDS [ V ]
(b)
ID (VGS)
0,0e+0
ID (VBS)
VBS 10V 8V 6V 4V 2V 0V - 2V - 4V - 6V - 8V -10V
-2,0e-6
thin & thick SOI finFETs VDS= - 0.1V
-4,0e-6
1e-6
-6,0e-6
1e-7
ID [ A ]
-8,0e-6 1e-8
ID [ A ]
1e-9
-1,0e-5 -1,2e-5
-12V -14V
-1,4e-5
1e-10
VGS
-1,6e-5 1e-11
-1,8e-5
-3
thick thin
1e-12 1e-13
-2
-20
VGS [ V ]
-15
-10
VBS [ V ]
1e-14 -5
-4
-3
-2
-1
0
VGS [ V ] Fig. 6. Output ID(VDS) and transfer |ID(VGS)| curves of two SOI double-fin FinFETs; heights of the thick and thin fins have been presented in Fig. 2.
-1
0
-5
0
2.0V 1.0V 0V -0.5V -1.0V -1.5V -2.0V -2.5V -3.0V
Fig. 8. Drain current dependence on gate voltage and substrate voltage for PMOSFET (L = 10 lm, W = 21 lm) for VDS = 0.5 V.
Acknowledgement The work was partially supported by the Polish Ministry of Science and Higher Education under Grant NR02001006/2009.
4. Conclusions P-channel FinFETs have been developed successfully in the thin Si nanowires, which cross-section area is 0.016 lm2 only. The goal of the work has been achieved by means of relatively simple CMOS-compatible technology and without use of expensive equipment for lithography. The bulk Si-based and SOI-based devices have been fabricated using the very similar processes. Channels of the SOI-based transistors represent a true nanowire shape. Due to the fact, that the gate area – to – channel volume ratio in such devices is very high, their operation is expected to be very sensitive to environmental conditions. For this reason they can be considered as better candidates for chemical detectors than standard large area CHEMFETs.
References [1] Zaborowski M, et al. pH and temperature microsensor for biological application. In: 20th conf EUROSENSORS, Göteborg, Sweden, 17–20.09.2006. [2] Jaroszewicz B, et al. Development of BSC ISFET design and technology for environment monitoring (WARMER), ELTE 2007, Kraków 04–07.09.2007. [3] Colinge J-P. FinFETs and other multi-gate transistors. New York: Springer; 2008. [4] Choi Y-K, King T-J, Hu C. Nanoscale CMOS spacer FinFET for the terabit era. IEEE Electron Dev Lett 2002;23(1):25. [5] Woo YS, Kang K, Joa M-H, Jeon J-M, Kim M. Solid-phase epitaxy of amorphous Si using single-crystalline Si nanowire seed templates. Appl Phys Lett 2007;91:223107. [6] Zaremba-Tymieniecki M, Li C, Fobelets K, Durrani ZAK. Field-effect transistors using silicon nanowires prepared by electroless chemical etching. IEEE Electron Dev Lett 2010;31(8):860. [7] Zaborowski M et al. Nanoscale pattern definition by edge oxidation of silicon under the Si3N4 mask – PaDEOx. Acta Phys Pol A 2009;116:139–41.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Development and characterisation of nanowire-based FETs Michał Zaborowski ⇑, Daniel Tomaszewski, Piotr Dumania, Piotr Grabiec Institute of Electron Technology (ITE), al. Lotników 32/46, 02-668 Warsaw, Poland
a r t i c l e
i n f o
Article history: Received 10 December 2010 Received in revised form 18 February 2011 Accepted 21 February 2011 Available online 23 March 2011
a b s t r a c t Development of Si nanowire-based FETs, suitable for sensor applications is reported. Process sequences for SOI and bulk p-channel FinFETs are described. SEM observations of the fabricated devices (180 nm wide, 87 nm or 175 nm high) are presented and discussed. Electrical characteristics measurements and basic characterisation results obtained for these devices are described. A procedure for serial resistance extraction has been mentioned in more detail, due to its high value inherent in the process used. Several aspects of the device sensitivity to front- and back-gate control have been discussed from the point of view of its application in biochemical detectors. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction
2. Development of technology
Standard bulk and SOI CMOS technologies have been adopted in ITE for fabrication of integrated Ion-Sensitive Field-Effect Transistor (ISFET) sensors [1] and of discrete large gate area ISFETs [2]. On the other hand it can be noted that the multi-gate MOSFETs have been extensively investigated in the last several years, due to perspectives for application in the sub-100 nm integrated circuits (ICs). Because of their better gate control over channel conduction as compared to planar MOSFETs, they are predestined for low-voltage applications. Among them triple-gate and double-gate MOSFETs (e.g. FinFETs) conducting along walls of a narrow silicon wire seem to be the most promising. Due to an almost ideal gate control and due to a small surface area these devices are expected to have also better sensitivity toward electrically active molecules [3]. Lithography-based patterning methods in a nano-scale reveal mostly a strong dependence of apparatus expenses on a smallest attainable pattern. Also nanoimprint lithography needs a relatively expensive mould. In order to avoid high cost of patterning a number of techniques have been developed, where the pattern width is determined not by the lithography step but by other methods. A widely used spacer technique [4] is a good example. Other class of techniques has been also developed, where Au or Ag are used for nanowires fabrication. Therefore it has a limited range of application [5,6]. Development of easily manufacturable Si-nanowirebased FETs suitable for sensor applications use has been the aim of this work.
ISFET-like devices have been fabricated in ITE clean-room using a NMOS process, described earlier in detail [2]. The device size down-scaling is possible but limited at 2–3 lm level determined by capabilities of the local equipment. In order to overcome these very conservative limitations and acquire capability to fabricate silicon narrow lines (wires), a Pattern Definition by Edge Oxidation (PaDEOx) method has been developed [7]. Width of the wire is controlled by conditions of lateral oxidation under a nitride mask, which appears by the LOCal Oxidation of Silicon (LOCOS) process. The minimum width of the Si line available in PaDEOx is close to 20 nm, irrespectively of a lithography technique. In the frame of this work, two PMOSFET processes have been developed with use of the PaDEOx method for definition of transistor channels. Bulk FinFET-type devices and SOI FinFETs have been fabricated in a very similar way. Flow charts of both processes are presented schematically in Table 1. The manufactured FinFET structures are illustrated in Fig. 1. In the reported experiment the n-type (100) SOI wafers with a 340 nm thick device layer of 0.1 X cm resistivity and 400 nm thick buried oxide (BOX) have been used for fabrication of SOI FinFETs. As the result of the operation no. 6 of the SOI FinFET processing (see Table 1) the closed-loop narrow oxide line has been obtained. It originates from ‘‘bird’s beak’’ region formed around the Si3N4/SiO2 stack, because the oxide layer in this region is thicker than the one growing at the neighbouring plane silicon surface. The narrow oxide line mentioned above serves as a mask in the Bosch plasma etching of silicon. As a result of the etching step a pair of transistor narrow channels has been formed between S and D contact areas (step no. 8 in Table 1 for SOI FinFETs). The gate oxidation and poly-Si gate preparation have
⇑ Corresponding author. E-mail address: [email protected] (M. Zaborowski). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.02.017
M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
1163
Table 1 Fabrication sequence of the transistors. SOI devices 1
Oxidation I xOx ¼ 135 nm
2 3
Nitride deposition 65 nm Nitride and oxide photolithography and etching Oxidation II 144 nm Nitride etching Oxide partially etching – thin oxide stays still in bird’s beak region Lithography of S/D contact surroundings Plasma etching of Si device layer through oxide and resist masks Gate oxidation 26 nm Poly-Si gate deposition, doping and patterning B+ S/D implantation BPSG passivation Contact etching Metallization deposition and patterning
4 5 6
7 8
9 10 11 12 13 14
Bulk devices 1 2 3 4 5 6 7 8
9 10
Initial oxidation B+ S/D implantation Oxidation I xOx ¼ 165 nm Nitride deposition 65 nm Nitride and oxide photolithography and etching Oxidation II 175 nm Nitride etching Oxide partially etching – thin oxide stays still in bird’s beak region Lithography of S/D contact surroundings Plasma etching of bulk Si through oxide and resist masks
11 12
Gate oxidation 29 nm Poly-Si gate deposition, doping and patterning
13 14 15
BPSG passivation Contact etching Metallization deposition and patterning
been the next steps. These have been followed by boron implantation across the gate oxide to form source and drain areas in selfaligned process. BPSG passivation and Ti:W/Al metallization have completed the process sequence on the SOI wafers. The device structure has been thoroughly examined via SEM observations. In order to reveal details of the Si-wire morphology the devices under observation have been post-processed. Passivating dielectric layers have been removed in HF bath. As may be seen in Fig. 2a the resulting transistors consist of two separate fin-shaped Si wires, serving as MOSFET channels. Height of these wires is approximately equal to 175 nm (Fig. 2b). However in order to obtain wires with different heights a group of the devices has been additionally oxidized. Their final height is 87 nm (Fig. 2c). Width of all the fins is 180 nm. Similar fin-type FETs have been developed using the standard bulk Si wafers. Main differences between the SOI and bulk processes are mentioned in Table 1. The preparation of drain and source regions has been shifted to the early beginning of the process sequence. Therefore a special care has been required in further thermal processing in order to form source/drain junction shallow enough. Due to this the fabrication has been preceded by SILVACO/ATHENA 1-D simulation (Fig. 3). This has allowed to design a shallow distribution of the B+ dopant, and the p–n junctions are expected to remain in the thin fins only, not in the bulk substrate. However, due to the changed source/drain
Fig. 2. SEM micrographs of double-fin SOI FETs with 180 nm wide fins. Passivation oxides have been removed in diluted HF: (a) general view; (b) single fin of ca 175 nm height; (c) single fin of 87 nm height, lowered by additional oxidation step.
preparation sequence, the bulk FinFET process is not self-aligned. So special efforts should be made to align the gate to diffusion patterns. The bulk FinFET structure after removing dielectric passivation (in order to clarify the view) is shown in Fig. 4. 3. Electrical characterisation Drain current (ID) versus gate and drain voltage (VGS, VDS) characteristics have been measured for series of FinFETs using a standard Keithley System 93 I–V setup. A test structure layout allows for evaluation of parameters of double fin devices with different
Fig. 1. Schematic view of the fabricated devices: (a) double-fin SOI FinFET; (b) double-fin bulk FinFET. Source contact has been cut off to demonstrate a pair of the fin-shape Si channels.
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M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
Fig. 3. Final 1-D distribution of doping concentration (cm3) versus depth (lm) in the bulk-type p MOSFET calculated using SILVACO/ATHENA.
Fig. 5. Transfer |ID(VGS)|, and transconductance gM(VGS) characteristics of bulk-type double-fin MOSFETs (shown in Fig. 4, fin length = 3 lm, fin separation = 6 lm).
proportionally to the fin heights, 175 nm and 87 nm. It may be concluded, that the current density becomes invariant. The wide subthreshold slope range mentioned above originates probably from wide spread of device local sizes, which have been achieved by subtraction of a part of device layer of the SOI wafer. It should be pointed out that the spread of the thinner device characteristics is larger than of the thicker ones. The test structure has been used also for measurements of resistance of the same pair of nanowires, which serve as the transistor channels. The resistors of length of 60 lm, 120 lm and 180 lm have been examined in several locations in the wafer. The resistance R can be described by an equation:
R ¼ Rc þ Lq=2A
Fig. 4. Bulk FinFET: one of the bulk fins after etching of passivation layer.
fin length and different fin separation (distance between the fins). Fin width has been a process controlled parameter. Both bulk and SOI transistors have been fabricated using this layout. The bulk double-fin FETs exhibit a reasonable reproducibility – Fig. 5, however small distortions of the characteristics shape may be noticed. There is a kind of hump in the medium inversion range of transconductance curves, which is supposed to be related to subsequent turning-on of different conduction paths in the device areas. More than one threshold voltage can be found for these devices. Measurements of transistors of two different separations between their fins allow to state that the main path for electric current flow is situated inside the fins. The SOI double-fin FinFETs also reveal correct electrical characteristics. The calculated value of the threshold voltage is in the range –2.4 to –2.2 V, and the subthreshold slope is in the range 100–150 mV/dec. I–V curves of two devices of different fin heights are shown in Fig. 6. The drain current is scaled nearly twice –
ð1Þ
where Rc is a sum of resistance of the two contacts, L and A are the length and cross-section area of the fin, respectively, and q is the fin mean resistivity. Mean resistance of the two contacts can be determined graphically – Fig. 7. Mean value and standard deviation of Rc parameter for 175 nmthick resistors have been estimated as 3.5 kX, and 0.8 kX, respectively. For the 87 nm-thick resistors these parameter are 7.4 kX and 1.3 kX. Next, after subtraction of the contact resistance fin resistance per unit length has been calculated. It has a mean value of 1.56 kX/lm for the individual thicker fin, whereas for the thinner fin – 2.72 kX/lm. A ratio of these values varies between 1.64 and 2.11. It corresponds to the ratio between fin mean heights (175 nm/87 nm 2) but depends on the location in the wafer. This is mainly due to differences of thickness of the SOI layer across the wafer. ISFET-type sensors may be fabricated using the above-described technology. Possibility of modification of device characteristics has been examined using PMOSFETs in 100 nm thick SOI layer on 400 nm BOX (Fig. 8). Poly-Si gate characteristics have emulated liquid gate characteristics. Two families of transfer characteristics have been measured: ID(VGS) for VBS = 0 and ID(VBS) for VGS = 0. They are shown together in Fig. 8 using arbitrary ratio of the VGS to VBS scale. It has been revealed that biasing the substrate allows for a change of operating point and a curve slope. A visible difference between ID control efficiencies by the front gate voltage (VGS) and by the back gate (substrate) voltage (VBS) can be directly related to a ratio of thicknesses of the gate and box oxides.
1165
M. Zaborowski et al. / Microelectronics Reliability 51 (2011) 1162–1165
(a)
3,0E+5
thin & thick SOI finFETs 0,0e+0
2,5E+5
-5,0e-6
2,0E+5
1,5E+5
-1,0e-5
ID [ A ]
1,0E+5
contact res. of thin resistors
5,0E+4
-1,5e-5
0,0E+0 -5,0E-5
VGS= -2 V VGS= -3 V VGS= -4 V VGS= -5 V
-2,0e-5
contact res. of thick resistors 0,0E+0
5,0E-5
1,0E-4
1,5E-4
2,0E-4
L[m] Fig. 7. Resistances and regression lines versus double fin resistor length; the devices have been fabricated on SOI substrates.
-2,5e-5 -5
-4
-3
-2
-1
0
VDS [ V ]
(b)
ID (VGS)
0,0e+0
ID (VBS)
VBS 10V 8V 6V 4V 2V 0V - 2V - 4V - 6V - 8V -10V
-2,0e-6
thin & thick SOI finFETs VDS= - 0.1V
-4,0e-6
1e-6
-6,0e-6
1e-7
ID [ A ]
-8,0e-6 1e-8
ID [ A ]
1e-9
-1,0e-5 -1,2e-5
-12V -14V
-1,4e-5
1e-10
VGS
-1,6e-5 1e-11
-1,8e-5
-3
thick thin
1e-12 1e-13
-2
-20
VGS [ V ]
-15
-10
VBS [ V ]
1e-14 -5
-4
-3
-2
-1
0
VGS [ V ] Fig. 6. Output ID(VDS) and transfer |ID(VGS)| curves of two SOI double-fin FinFETs; heights of the thick and thin fins have been presented in Fig. 2.
-1
0
-5
0
2.0V 1.0V 0V -0.5V -1.0V -1.5V -2.0V -2.5V -3.0V
Fig. 8. Drain current dependence on gate voltage and substrate voltage for PMOSFET (L = 10 lm, W = 21 lm) for VDS = 0.5 V.
Acknowledgement The work was partially supported by the Polish Ministry of Science and Higher Education under Grant NR02001006/2009.
4. Conclusions P-channel FinFETs have been developed successfully in the thin Si nanowires, which cross-section area is 0.016 lm2 only. The goal of the work has been achieved by means of relatively simple CMOS-compatible technology and without use of expensive equipment for lithography. The bulk Si-based and SOI-based devices have been fabricated using the very similar processes. Channels of the SOI-based transistors represent a true nanowire shape. Due to the fact, that the gate area – to – channel volume ratio in such devices is very high, their operation is expected to be very sensitive to environmental conditions. For this reason they can be considered as better candidates for chemical detectors than standard large area CHEMFETs.
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