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FETs and Other Devices
Chapter 7
F E T s and o t h e r d e v i c e s 7.1
Ge channel M O S transistors
Considerable work has been done on SiGe heterostructure Field Effect Transistors (FETs). Both Metal Oxide Semiconductor FETs (MOSFETs) and Modulation Doped FETs (MODFETs) have been fabricated and studied by several groups. Ge MOS technology is of interest because the mobility of holes in Ge is larger than in most other semiconductors [1]. At low temperatures both electron and hole mobilities are high (at 77 K they both exceed 20,000 cm2/Vs). Ge MOS technology is also of interest for fabricating monolithic fiber-optic receivers [1]. Both p- and n-channel Ge MOSFETs have been fabricated. As distinguished from the strained layer devices discussed later in this chapter, the devices discussed in this section are fabricated using unstrained Ge. Formation of a high quality insulator layer is the key to the fabrication of high-speed metal-insulator-semiconductor devices. Early attempts to grow the insulator on a Ge substrate using thermally grown native oxide, deposited oxide and nitride were not very successful. In almost all cases large interface state densities and leakage currents were observed through the insulator. The difficulties arise because of the formation of volatile GeO when oxidation is performed at a temperature > 400~ The n-channel MOSFETs can be grown on (111) p type Ge substrate [1, and references given therein]. Since GeO2 is hygroscopic, an 800 ~ SiO2 protective layer is electron beam-evaporated on top of the GeO2 layer. Electrical measurements showed that the fast interface state density was ,~ 4 x 1011 cm-2/eV. Fixed oxide charge density was also large. Surface mobilities were of the order of 22% of bulk mobility. Improved n-channel Ge MOS devices were fabricated by Rosenberg et al. [394], using a self-aligned process. Nitrided native oxide was used as a gate insulator. An arsenic dose of ,,~ 1015 cm -2 was implanted at 50 keV to form the source and drain regions. The common-source characteristics of a 6 #m gate length device showed good saturation and turn-off. Junction leakage, parasitic surface conduction and contact resistance were negligible. An interface state 195
196
C H A P T E R 7. F E T S A N D OTHER DEVICES
density of < 5 x 101~ cm-2/eV at mid-gap and a fixed insulator charge of < 3 x 10 l~ cm -2 were estimated from electrical measurements. The measured channel mobility was 940 cm2/Vs. In a subsequent paper [395] n-channel mobility in excess of 1200 cm2/Vs was measured. P-channel MOSFETs using the same process [394] were also fabricated by the same group [395]. Measured lowfield mobility was 770 cm2/Vs in a 7 #m gate length device. The mid-gap interface state density was measured by comparing 1 MHz and 100 Hz C - V characteristics and was found to be below 5 x 10 l~ cm-2/eV.
7.2
Strained layer p-channel MOSFETs
The speed of Si CMOS (complementary metal-oxide-semiconductor) circuits is limited by the p-channel MOSFETs because of the relatively low mobility of the holes and because the current drive capability of the p-MOS transistor is inferior. In-plane mobility of holes in the SiGe layer grown on Si(100) increases due to strain. Strain removes the degeneracy between the heavy and the light hole bands and the spin-orbit band moves further down. This reduces the intervalley scattering of the holes. In buried SiGe strained layers I scattering of holes by the Si-SiO2 interface is practically absent. Absence of these scattering mechanisms increases further the hole mobility. Therefore SiGe strained layer p-channel MOSFETs are expected to have superior performance. Considerable work on the SiGe p-channel MOSFETs was done before 1993 [1, 397, 404]. Finding a suitable gate dielectric for the SiGe MOSFETs has been a problem. Extensive work has been done on the oxidation of SiGe alloys in an effort to obtain a good interface between SiGe strained layers and the oxide of the alloy (see the review by Jain and Balk [396]). Similar problems also arise with growth of oxides on Sil_x_yGexCy layers [86]. Attempts have also been made to grow new gate dielectrics on SiGe strained layers [1]. However, it has not been possible to grow or deposit a good-quality oxide or another dielectric directly on SiGe strained layers with acceptable quality of the interface. This difficulty is avoided by growing a Si cap layer (also known as buffer layer) on the active SiGe strained layer and growing or depositing SiO2 on the Si cap layer [1]. A schematic cross section of a SiGe MOSFET is shown in Fig. 7.1(a) and that of a thin-body MOSFET (discussed later) is shown in Fig. 7.1(b). The band diagram of the thin-body MOSFET is shown in Fig. 7.1(c). Usually the substrate has an n type doping concentration of about 5 x 1016 cm -3. The Si spacer layer, strained SiGe layer and Si cap layer are generally undoped. The background doping in these layers is n type and is about 5 • 1015 cm -3. The band bending and position of the Fermi level under an applied negative voltage are shown in Fig. 7.1(c). For low gate voltage, holes are formed in the SiGe layer, making it a p type conducting channel. There are no holes yet at the Si-SiO2 interface. For higher gate voltage (Fig. 7.1(c)) the holes are also formed at the Si-SiO2 interface, giving rise to a parasitic channel in the Si cap layer. The one-dimensional Poisson's equation has been solved numerically by many 1There is a Si cap between the gate oxide and active SiGe layer in p-channel MOSFETs.
7.2. S T R A I N E D L A Y E R P - C H A N N E L M O S F E T S
197
Figure 7.1: (a) Schematic cross section of a conventional SiGe MOSFET. (b) Cross section of a thin-body SiGe MOSFET. (c) Schematic band diagram of the thin-body MOSFET along the dashed line (based on Yeo 2002 [18]). workers [397, 404, 393, 40] to calculate threshold voltage and to obtain carrier densities in the two channels under different biasing conditions. Iniewski et al. [393] have given an approximate analytical solution of the equation. They have also calculated the short channel effects on the performance of the SiGe strained layer MOSFETs. The calculated charge densities QSiGe [18] in the Sil-xGex (x = 0.3) channel and Qsi in the Si channel of a MOSFET are shown in Fig. 7.2. These results are similar to those obtained by Iniewski et al. [393]. More recently Palmer et al. [40] have investigated in detail the characteristics of p-channel MOSFETs fabricated with a thin Si capping layer. Two different n-dopings were used in the substrate to investigate the effects of punch-through and drain induced barrier lowering. In batch A the doping was 2 • 1017 cm-3 boron and in batch B it was 5 • 1015 cm -3. The active layer was a Si0.64Ge0.36 strained layer. A range of thicknesses of the Si capping layer were used. The mobility versus sheet carrier density for two values of substrate dopings and for several values of Si layer thickness are shown in Fig. 7.3. The point at which parasitic conduction in the Si channel sets in is shown by the plus sign. It is seen from Fig. 7.3(a) that the parasitic conduction sets in at lower sheet carrier densities (and hence at lower gate voltages) for smaller values of Si layer thickness. Comparison of Fig. 7.3(a) and Fig. 7.3(b) shows that substrate doping does not have a significant effect on the onset of parasitic conduction. Iniewski et al. [393] studied the effect of changing the design parameters on the performance of the MOSFETs. In any one calculation, only one parameter was changed; others were kept unchanged. The main results obtained by Iniewski et al. [393] can be summarized as follows: 1. As the Ge concentration x increases, VTH decreases and VTS increases. Therefore the gate voltage "window" VTH- VTS for which parasitic conduction is negligible increases with Ge concentration.
198
C H A P T E R 7. F E T S A N D OTHER DEVICES 9
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Gate Voltage V6 (V) Figure 7.2: The integrated charge densities QsiGe and Qsi in the SiGe channel and parasitic Si channel (Yeo 2002 [18]). 92002 IEEE
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Figure 7.3: (a) Batch (A), effective mobility vs carrier sheet density for devices with a 2 • 1017 cm -3 substrate doping punch-through stopper. (b) Batch (B), same as for batch (A) but without a punch-through stopper. The observed onset of conduction at the SiO2/Si interface is marked by a cross (+) in both cases (Palmer 2001 [40]).
7.2. S T R A I N E D L A Y E R P - C H A N N E L M O S F E T S @
199
The effect of increasing Si cap thickness is just the opposite. As the cap thickness increases, VTS decreases and VTH increases. Therefore small cap layer thicknesses are desirable for obtaining large values of the gate voltage window. If the thickness of the cap layer is very small, remote scattering of the channel holes by the Si-SiO2 interface becomes significant and adversely affects the performance of the device. It is therefore desirable to avoid very thin cap layers and to use a large value of Ge concentration to obtain a good value of the gate voltage window.
3. Both threshold voltages increase with gate oxide thickness and substrate doping concentrations. The relative increase of the two voltages is such that the gate voltage window increases with gate oxide thickness but decreases slowly with substrate doping concentration. 4. The threshold voltages are not very sensitive to the thicknesses of the SiGe strained layer and Si spacer layer below the strained layer. .
The effect of grading Ge (maximum concentration being close to the Si cap) was also studied. It was found that the threshold voltage depended mainly on the value of Ge concentration at the maximum; the grading has only a second-order effect. The large concentration of Ge is therefore needed only close to the Si cap; Ge concentration in the rest of the strained layer can be reduced, making the critical thickness of the layer larger and increasing the stability of the device. In the SiGe MOSFET fabricated by Verdonckt-Vandebroek et al. [404], the authors used graded Ge concentration in the strained layer and obtained good results.
As a result of these calculations, Iniewski et al. [393] concluded that the approximate values of the design parameters for optimum performance of a SiGe MOSFET are: n type doping in the substrate in the range 10 lr cm -3, undoped Si spacer and linearly graded (40-0% Ge) SiGe layers, each of 10 nm thickness, undoped 5 nm thick Si cap layer and 5 to 10 nm thick gate oxide. Subbanna et al. [397] used UHV/CVD to grow SiGe strained layers. No spacer layer was used below the SiGe layer. Gate oxides (7 nm and 10 nm thick) were grown either thermally or deposited using Plasma-Enhanced Chemical Vapour Deposition (PECVD). MOSFETs with two Ge concentrations, x = 0.1 and 0.2 were fabricated. No channel doping was used to adjust the threshold voltage. Nominal channel lengths were between 0.8 and 10 #m. The devices showed a sharp turn-off. The subthreshold slope was insensitive to the drain voltage; it varied from 175 to 200 mV/decade for values of drain voltage VDS from --0.3 to --3.3 V. Values of transconductance gm and threshold voltage VT for 10 nm thermal oxide and for x - 0.2 are shown in Table 7.1 along with the performance characteristics of SiGe MOSFETs fabricated by other groups. The results for devices with PECVD oxide were similar. The devices with smaller oxide thickness showed smaller (numerical) values of threshold voltage and larger values of transconductance. Values of mobilities were not extracted in these experiments. Similar devices were fabricated by Garone et al. [398]. SiGe
CHAPTER 7. FETS AND OTHER DEVICES
200
Table 7.1: Observed characteristics of SiGe strained layer p- and n-channel M O S F E T s . Mobility p is given in cm2/Vs and saturated transconductance gin, in m S / m m . The symbol VT is the threshold voltage (in V) and T is temperature (in K) at which mobility # and transconductance are measured. The symbols dl to d4 (in nm) indicate the thicknesses of the Si spacer layer, SiGe strained layer, Si cap layer and oxide layer. Any value of a parameter or characteristic not quoted in the original paper is indicated by a dash. Ge concentration x -- 0 indicates Si control MOSFET. p- Channel M O S F E T s
dl
d2
d3
d4
x
VT
#/T
gm/T
-
7
10 10
0.2 0
-2.0
-
3s/300 22/300
10.5
12.5 12.5
0.3 0
-1.1 -2.0
780/90 290/90
[398] [398]
7 -
5 5
0.2 0
-
155/300 122/300
[399] [399]
7 -
10 10
0.5 0
-1.3 -1.8
1500/77 560/77
[4001 [400]
12-30
7 7
~7 ~ 7
0.2 0
-0.22 -0.22
150/300 90/300
20
5
7
**
**
980/82
-
-
10
15
-
-
100
7
-
-
5
167/300 139/300
Ref. [3971 [397]
[405]* [4051" [404]
n-Channel M O S F E T s
vertical transistor
0.16 0
0.57 0.70
** **
-
0.15
-
***
45/300
-
**** **** *****
70/77 800/77 700/300 300/300
[403] [403] [65]
MODFETs p n n p
MODFETs MODFETs MODFETs MODFETs
strained SiGeC strained Si strained Si -
[161] [71] [35] [71]
*Values of VT and gm are for short channel (0.25#m) M O S F E T s (see text).
**See [1]. ***Mobility increased due to Ge and strain ****See Fig. 5 on p a2a of Ref. [71] *****See Fig. 10 on p 326 of Ref. [71]
7.2.
STRAINED
LAYER P-CHANNEL
MOSFETS
201
layers were grown by Rapid Thermal Chemical Vapour Deposition (RTCVD). Samples were grown with three Ge concentrations, x - 0.2, 0.3 and 0.4. The SiGe layer was doped n type to 1 x 1016 cm -3. Gate oxide was 12.5 nm and was grown by PECVD. Nayak et al. [399] fabricated strained layer MOSFETs using MBE. The highest Ge concentration (x - 0.5) has been used by Goto et al. [400]. The design parameters of selected MOSFETs and their characteristics observed by different authors are compared in Table 7.1. Submicron channel length SiGe MOSFETs have been fabricated by Kesan et al. [405] using a Si CMOS compatible process. Si epilayers, SiGe epilayers and oxide layers were grown by the same methods as those used by Subbanna et al. [397]. The values of Ge concentration were in the range 0 to 0.25 and the strained layers were 12.5 to 30 nm thick. The thickness of gate oxide was 7 nm. Characteristics were measured at 82 K and 300 K. The current drive capability of the SiGe devices was significantly better than that of the Si control devices. At 82 K, the subthreshold slope of the SiGe device (x = 0.2) is 40 mV/decade compared to 30 mV/decade for the Si control device. Transconductance values for a Sil_~Ge~ device with x - 0.2 and for a Si control device are shown in Table 7.1. Compared to the 300 K values given in the table, at 82 K the transconductance values (also for the short-channel devices, effective gate length = 0.25 #m) were 201 mS/mm and 160 mS/mm. For long-channel devices (channel length 1.85 #m) the threshold voltage at 300 K was -0.35 V for the SiGe device and -0.45 V for the Si control device. These are considerably larger than those given in the table for the short-channel devices. The decrease of the threshold voltage on decreasing the channel length is due to the short-channel effects and is expected theoretically [393]. The 82 K mobility for long-channel devices is 400 cm2/Vs for the SiGe device and 250 cm2/Vs for the Si control device. Mobility values at 300 K are shown in Table 7.1. Verdonckt-Vandebroek et al. [404] used a graded SiGe layer; x varied from 0.25 at the upper end near the Si cap to 0.15 at the lower end near the spacer. The channel layer was 20 nm thick and doped n type (3 x 1017 cm-3). The thickness of the spacer and the cap were 5 nm each. A heavily boron doped 5 nm Si layer was used below the spacer to adjust the threshold voltage and prevent carrier freeze-out at low temperatures. The values of room temperature threshold voltage varied between -0.1 to -1.1 V, corresponding to the integrated boron dose of 2.3 x 1012 cm -2 to 1.4 x 1012 cm -2. The subthreshold slope was 87 mV/decade at 300 K and decreased to 31 mV/decade at 82 K. The 82 K mobility was 980 cm2/Vs (see Table 7.1). Although a Si control MOSFET was not fabricated for comparison, this value of mobility is considerably higher than the value reported in the literature for Si MOSFETs [404]. It is seen from Table 7.1 that in all cases the threshold voltages are lower and mobilities and transconductance values are higher in the SiGe device than those obtained with Si control devices. Among the results cited in Table 7.1, highest mobilities were obtained by Goto et al. [400] who used the largest Ge concentration. Nayak et al. [401] studied SiGe MOSFETs fabricated on a SIMOX substrate. In these SOI devices, vertical field and band bending are smaller; hence parasitic
202
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
conduction in the Si channel occurs at higher gate voltages. The SiGe SOI devices showed 90% improvement in the mobility over the Si control devices. They also showed considerable improvement in the transconductance and saturation current drive. More recently Nayak et al. [402] have fabricated a MOSFET in an active Si layer channel (as distinguished from SiGe layer channel) under tensile strain. A thick relaxed Si0.75Ge0.25 was first grown on a Si substrate. The active Si layer was grown on this buffer. In-plane hole mobility in the Si layer is expected to increase due to tensile strain. At higher magnitude of gate bias, the channel mobility of the strained Si p-MOSFET was 50% higher than that of a control Si p-MOSFET processed under identical conditions. Most work has been done on the p-channel heterostructure MOSFETs because the speed of the present CMOS circuits is limited by the poor performance of the p channel Si MOSFETs. Recently Yeo et al. [91] have fabricated short channel p- and n-MOSFETs with 24% Ge in the channel. The drive current increased by up to 25% down to channel length to 9.1 #m. The drive current of n-channel MOSFETs also increased up to channel length of 0.4 #m.
7.3 7.3.1
Strained layer n-channel MOSFETs Si quantum well channel with tensile strain
SiGe n-channel MOSFETs have been fabricated by Selvakumar et al. [403]. In these MOSFETs, the SiGe channel region was created by implanting a dose of 6 • 1016 cm -2 of Ge + at an energy of 80 keV. This resulted in the formation of a channel with a Ge concentration x = 0.16. A control Si MOSFET was fabricated using identical processing steps. The nominal channel length of both devices was 7 #m. The measured threshold voltage VT for the SiGe devices was 0.57 V, as compared to the value 0.70 V for the control device (see Table 7.1). At any given effective gate voltage V c - VT, the drain current for the SiGe device was considerably larger. Electron mobility #~ in the channel could not be extracted from these measurements because exact values of oxide capacitance Co~ and effective channel length L were not determined. The value of Co~#~W(Vc VT) VD/L determined from the slopes of drain current versus drain voltage plots was higher for the SiGe devices. If it is assumed that the effective channel length is the same in the two cases, electron mobility comes out to be larger in the SiGe devices. From theoretical considerations, the in-plane mobility of electrons in the strained SiGe layers should be smaller. Recently Yeo et al. [91] have fabricated both n- and p MOSFETs with a 10 nm Si0.~6Ge0.24 channel grown on Si substrate. The measured mobilities of holes and electrons in the two devices are shown in Fig. 7.4. As expected the electron mobility in the compressed SiGe channel is smaller, a result different from that obtained in Ref. [403]. However the drive current in both the p- and n-MOSFETs was higher in the strained layer devices. To take advantage of the increase in electron mobility by tensile strain,
203
7.3. S T R A I N E D L A Y E R N - C H A N N E L M O S F E T S 200
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0.5
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1.5
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Effective E-field Eelf (MV/cm)
Effective E-field Eeff (MV/cm)
(a)
(b)
3.0 ~ r
Q
Figure 7.4: (a) Hole mobility and (b) electron mobility from long channel devices. The universal mobility curves [191,238] are also shown (Yeo 2000 [91]). Welser et al. [239] designed and fabricated n-MOSFETs in tensile strained Si layers grown on relaxed graded SiGe buffer layers. Ge concentration in the top layer was 30%. Two designs, one with surface channel and the other with a buried channel were implemented. The buried channel device had a SiGe layer on top of the strained Si layer. A sacrificial Si layer was grown to form the gate oxide. The surface channel device showed 80% enhancement of electron mobility over that of the control Si device. Similar enhancement was found in transconductance. We have already discussed the work of Hbck et al. [101] on both n and pMOSFETs in chapter 5. The mobility in the strained p-channel increased and became comparable to the electron mobility in conventional Si n-channels. 7.3.2
Vertical
SiGe
n-MOS
transistors
In a vertical transistor the carriers move in the out-of-plane direction and mobilities of both electrons and holes are increased in the compressive strain. It is not necessary to fabricate tensile strained Si channel on relaxed SiGe layers to obtain the enhancement in electron mobility due to strain. Very short channel transistors can be obtained without the need of advanced lithographic technology. In view of these advantages both p-type [166] and n-type [65] vertical MOS transistors have been demonstrated. The structure of the n-type transistor is shown in Fig. 7.5. The SiGe channel is formed by Ge implantation after the oxide growth so that no Si cap is required during oxidation. The Ge concentration in the channel is graded, the maximum being x - 0.15, 1500/k
204
CHAPTER 7. FETS AND OTHER DEVICES
Figure 7.5: Cross section of the graded SiGe vertical n-channel MOSFET [65].
below the surface. Boron was implanted to a concentration of 8 • 101~ cm -3 in the channel. Identical control Si devices were also fabricated. The subthreshold characteristics of the SiGe and control Si devices are shown in Fig. 7.6(a). The output characteristics of the devices are shown in Fig. 7.6(b). The on-off characteristics of both devices are quite good. SiGe devices have a higher drive current. SiGe devices also have a higher off-state current. Due to the smaller bandgap of the channel, the effect of drain induced barrier lowering (DIBL) is larger in the SiGe devices. The threshold voltage VT and subthreshold swing (S) was large for both devices. This is due to the thick gate oxide used in the structure and unoptimized channel doping. For drain-source voltage VDS equal to V a - VT the drive current for the SiGe device is 50% higher than that of the Si control device due to enhancement of the electron mobility in the out of plane direction. However the enhancement is not as large as for the holes [65]. The actual electron mobility could not be extracted because a channel of only one single length was used and because source and drain resistances were not known accurately. Values of transconductance for both devices were determined from linear and saturation regimes. The linear peak transconductance of the SiGe device was 0.45 mS/mm and that of the Si device it was 0.3 mS/mm. As the Ge content and the strain increase, the separation between the two sets of valleys increases. Population of electrons in the lower valleys increases and intervalley scattering is reduced. Therefore in the out of plane direction the mobility of both electrons and holes increases as the Ge content in the alloy increases. However alloy scattering also increases with increase of Ge concentration. Therefore there should be an optimum Ge content for which the
205
7.3. S T R A I N E D L A Y E R N - C H A N N E L M O S F E T S 10"z 10" ~" I0 "6 ~
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. , ]
i
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c:
lxlo6 lxlO 5 ~ 0
lx103 0.5
1.0
1.5
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Thickness of ramp to 30% Ge (ram)
Figure 7.7: Effect of grading rate of Ge-content in the buffer on the density of threading dislocations and on the electron mobility measured at 0.4 K. The dotted line is an extrapolation showing that mobility is not limited by the threading dislocations once their density is below 1 x l0 s c m - 2 [215].
206
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
mobility is maximum [65].
7.4 7.4.1
M o d u l a t i o n doped Field Effect Transistors Enhanced
mobility
in 2D gas
The 2-Dimensional (2D) character of electron or hole gas was predicted more than 40 years ago and observed experimentally about 25 years ago at the interface in Si MOSFETs [1, and references given therein]. Since the valence band-edge in Sil_~Gex strained layers is always higher than in Si (lower in energy for holes), a thin layer of strained SiGe sandwiched between two Si layers offers the possibility of confining the holes and forming a 2D hole gas. Similarly, if the strain is tensile, a lower energy well for electrons is obtained in a Si quantum well in which a 2D electron gas can be formed. The carriers are supplied by neighbouring layers which are doped p or n type and the structures are known as modulation doped structures. The devices fabricated using modulation doped strained layers are known as Modulation doped Field Effect Transistors (MODFETs). In MODFETs the dopants are not present in the active layer and the impurity scattering is absent which results in additional enhancement of the mobilities. Miyao et al. [244] have obtained very high mobilities in the 2D hole gas. The structures were fabricated on Ge(100) substrate followed by a Sil_~Ge~ buffer layer. This was followed by a 20 nm Ge channel layer and a 30 nm Si0.sGe0.5 layer. A Ga doping spike was introduced in the middle of the top Si0.5Ge0.5 layer. The gate oxide was made of CVD SiO2 (50 nm at 400~ Hole mobilities of 9000 cm2V-ls-1 [243] and 10,000 cm2V-ls -1 [244] were reported in t h e e structures. Recently K~inel et al. [7] have measured mobilities in modulation doped strained Ge channels grown on a Si0.4Ge0.6 layer. The Si0.4Ge0.3 layer was grown on a Si0.3Ge0.~ buffer layer and the whole structure was grown on a Si substrate. Hole mobilities up to 3000 cm2/Vs at room temperature and 87000 cm2/Vs liquid He temperature were observed. Extensive work has been done on the growth of buffers with a reduced concentration of threading dislocations. A detailed description of the methods of growing graded layers is given in chapter 2. The concentration of threading dislocations depends, among other factors, on the grading rate of Ge concentration. The results of an experiment on the effect of the grading rate of Ge are shown in Fig. 7.7. This figure shows that the concentration of dislocations can be reduced from 1 x 1011 cm -2 down to 1 x 105 cm -2 by changing the grading rate of Ge. The mobility of electrons in the Si epilayers grown on the buffer is also shown. Electron mobility exceeding 3 x 105 cm2/Vs were obtained in the Si layers under tension. The dotted line shows that if the density of threading dislocations is less than 1 x l0 s cm -2, other factors (e.g. phonons and other defects) start limiting the mobility. Selected mobilities reported in the 2D carrier gas are summarized in Table 7.2. The large values of the mobilities shown in Table 7.2 make it possible for the SiGe based transistors to work at high frequencies.
7.4. M O D U L A T I O N D O P E D FIELD E F F E C T T R A N S I S T O R S
207
Table 7.2: Best mobilities of 2D electron and hole gases in strained Si or SiGe quantum wells. Type Electron Electron Electron Electron Hole gas Hole gas Hole gas
/ Ti/Pt/Au contact Source I
T-gate Pt/Au
gas gas gas gas
Temp. (K) 300 77 < 2 0.4 300 77 < 10 K
cmU/Vs 2830 18000 180000 300000 1050 3500 18000
Ti/Au T-gate
/
/ I
5 nm Si-cap 10 nm Sio.6Geo.4
, , Drain' j
9 nm Si-channel I 3nm Si0 6Ge04spacer nm Sio6Geo4Sb, 8*101Scm3~'graded buffer SiGen---.n 4
/
Pt-contact
4 nm Si cap 7 nm Si0 4Geo.6
f 3rim si0C;eo.,.sb -Sio,6Geo.4spacer iI
(a)
Reference [241] [241] [98] [215] [242] [242] [98]
(b)
9 nm Ge channel
graded buffer SiGeo . o 6
Figure 7.8: Typical layer structure of (a) n-MODFET [392] and (b) p-MODFET [131] (quoted by g5nig 2000 [71]). 7.4.2
Design of MODFETs
Early n-MODFETs were fabricated by Ds et al. [392] by MBE. The substrate was p - with a resistivity p = 1000 flcm. The layer structure is shown in Fig. 7.8(a). The buffer layer is graded from 0% to 40% Ge. A tensile strained 9 nm Si channel is embedded in undoped Si0.6Ge0.4 layers which separate the channel from the doped carrier supply layers. Due to large tensile strain a high conduction band offset is achieved. Carrier densities up to n8 = 7 • 1012 cm -2 and mobilities up to 28000 cm2/Vs were obtained. The structure of a compressively strained Ge channel p-MODFET is shown in Fig. 7.8(b) [131]. The layer thicknesses, doping concentrations and Ge contents are clearly shown. To summarize a n-type MODFET consists of tensile strained Si layer with n-doping in the neighbouring layers. A p-type MODFET consists of compressively strained SiGe layer with p-doping in the neighbouring layers. The technology of fabri-
CHAPTER 7. FETS AND OTHER DEVICES
208 n-MODFETs or HFET 1000
n, p-SiGe
HFET Si_:__l.mu O---~ .~-,~,-~ I T! DIBM n-rirt~i 9IBM
N
n_S~im ' ~
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p-MODFETs or HFET
.
fmax "DC
=
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9
p-~T
~,
~
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IBM fmax 9
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0
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,
0.05
llll
0.1
, , , , , ,,,I 0.2 0.5 1.0 Gate Length LG (gm)
p-Si--- IBM, et al. 1
i
0.05
II
'I
0.1
0'2. ' , , , , , , I 0.5 1.0 Gate Length LG (~m)
Figure 7.9: Review of frequency data reported (a) for n-MODFETs (also known as HFETs) and (b) for p-MODFETs (S6nig 2000 [71]). Frequencies in p-Si MOSFETs are considerable lower than in n-MOSFETs. Simulated frequencies in both types of MODFETs are similar. Experimental data also show much larger improvement in the p-devices. cating the MODFETs has been reviewed by KSnig [71]. 7.4.3
AC and DC performance
of MODFETs
The very high mobility of electrons in n-MODFETs makes it possible to operate the transistor at low power and at supply voltages of about 1 V and zero gate bias. By using recessed gates, the gate to channel distance can be varied and the operation mode can be adjusted. The threshold voltages can be varied between -1.6 V and +0.2 V. The fT and fmax data obtained with n-MODFETs are plotted in Fig. 7.9(a) and for p-MOSFETs in Fig. 7.9(b). The frequencies depend on gate length. Data for optimized devices, particularly for LG < 0.25 #m are not yet available. The devices are also not optimized for low parasitics and optimum dopings. The data points lie above those for Si MOSFETs even in the unoptimized devices. Experimental values of transconductance of both n- and p-MODFETs are shown in Fig. 7.10. All devices were fabricated with Schottky gates. The drain current can be made zero by applying negative bias to the n-type devices (at zero bias the channel is not depleted). The operation mode of the devices can be changed by using recessed gates with different depths. Therefore both types of devices can be made on the same chip. MODFETs show good transconductance over a wide range of gate-bias values. The saturation current values obtained for n-devices are 230-320 mA/mm for depletion mode and about 200 mA/mm for enhancement mode n-MODFETs. The results for p-MODFETs shown in Fig. 7.10(b) are also very promising. Transconductance of 314 mS/ram at LG =
7.4. MODULATION DOPED FIELD EFFECT TRANSISTORS n-MODFETs at 77 K and at 300 K 800 . . . . . . . . . . ~ 7 0 0 t 1 - ..... 300K77K] (a) ' ::": ~= 600'... ........ : 9 3500r "" il
........
;
/ t--,
/ """
p-MODFETs at 300 K 1000
_ .
. -
-0.5 Gate
o Sio.aGeo.r pMOS (IX;) 9 Sio.aGeo.rpMOD (IBM) O Ge pMOD (DC), do<:: = 19 nm r Ge, MOD (IBM). doc 10 nm
Co)
- i~ g '";
i
o
,00
,.'* - .0
/DC 9
209
. . : Lc,-~.4, 0.15 ~tm 0.0 0.5 1.( Bias VG (V)
Jl 0,1
1
1
.~
i
i
J i J]
L 1
Gate Length LG [pm]
Figure 7.10: DC transfer characteristics of depletion and enhancement mode (a) n-SiGe MODFETs and (b) p-MODFETs (compiled by KSnig 2000 [71]). Note that the transconductance is plotted as a function of gate-bias for n-type devices but as a function of gate-length for the p-type devices. For n-MODFETs data at 77 K are also shown. The abbreviation DC is used for the company name Daimler-Chrysler. 0.1 tzm and 212 m S / m m at Lc = 0.8 #m is obtained. The performance characteristics of MODFETs are compared with those of HBTs in Table 7.3 and Fig. 7.11. Table 7.3 shows that the values of transconductance, fT and fm~x have shown large improvements over the 1994 values quoted in Ref. [1].
7.4.4
N o i s e in n - M O D F E T s
Several groups have investigated noise characteristics of SiGe MODFETs [35, 94, 226, 164]. Simulations show that the noise characteristics are better than those of the devices based on III-V semiconductors. Recently Enciso et al. [35] have measured the noise performance of strained Si/Si0.58Ge0.42 n-MODFETs. The structure was grown by MBE on a 1000 f~cm p-type Si substrate. There was a relaxed SiGe buffer with graded Ge concentration from 0 to 43%. The active layer was a 9 nm strained Si layer sandwiched between two 3 nm Si0.58Ge0.42 layers and two Sb-doped SiGe carrier supply layers. The noise parameters were determined by measuring noise figure variation with frequency. The measurements were made for two impedance sources, a 50 f~ and an offset short line presented at the input transistor. The maximum gm of the devices was 700 m S / m m which is a record value for SiGe based FETs. The frequency behaviour was also good, maximum values of fT and fmax were 49 GHz and 70 GHz respectively. The values of gate source and drain resistances were extracted: RG -- 65~2mm, Rs - 1.8f~mm, and RD = 1.85f~mm. The measured noise characteristics of the 0.13 #m gate MODFETs are shown in Fig. 7.12. Figs. 7.12(a), and (b) show NFmin, Ga~8, and Rn as a function of I n s at 2.5 GHz. In the initial stages NFmin decreases as I n s increases because
210
CHAPTER 7. FETS AND OTHER DEVICES
Table 7.3: Performance of transistors fabricated using SiGe strained layers (see Figs. 7.9(a)and 7.9(5)). Device HBT n-MODFETs p-MODFETs
*LG ---- 0 . 8
State of the /3(77K) fT GHz 13000 210 100 80
/3(RT) 5000
art
fmax
Fb
gm(RW) gm(77K)
GHz 180 120 100
dB 0.2 -
mS/mm
mS/mm
388 212"
670 300
#m
Potential Device
ft, fmax
HBT n-MODFETs p-MODFETs
GHz 225 ~ 300 > 200
T Delay ps <4 3-6 5-10
gm (RT) mS/mm
m
> 800 > 600
300 measured ----
N
HFET t s
extrapolated
200,
Si MOS r
100 ~m
1985
1990
1995 Years
m
m
Si BJT mmm
mm
m
m
2000
Figure 7.11: Progress in frequency of SiGe HBTs, standard Si BJTs, MOSFETs and SiGe HFETs (MODFETs) is shown. Data up to 1995 was compiled in Ref. [216]. We have updated the data for HBTs and HFETs up to 2002. Expected increase in the frequency beyond 2002 is also shown.
7.4. MODULATION DOPED FIELD EFFECT TRANSISTORS ~ 6O
-
(a)
'
'
'
(c)
211
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I 2:
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40
O
z 30 ~- 5
1: J.
Z
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I I
4
- 1 5 ~*>
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u~ 3 O
=
-10~
2
-5 0
t
!
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50 100 150 200 Drain current (mA/mm)
0
i
5 10 15 Frequency (GHz)
~
0
20
Figure 7.12: (a) Equivalent noise resistance R~, minimum noise figure NFmin, and available gain Ga~ plotted against drain current n s for 0.13 #m n-Si/SiGe MODFET at VDS = 1.25 V and 2.5 GHz. (c) and (d) same as (a) and (b) plotted against frequency at the same VDS and at I n s -- 70.7 mA/mm (Enciso 2001 [35]). gm increases faster than the channel noise current. Also id is screened more efficiently by the associated power gain. At large I n s gm saturates and becomes nearly constant. After obtaining a shallow minimum, NFmin starts increasing in this region. Now the associated gain Ga** decreases and noise resistance increases. Figs. 7.12(c), and (d) show NFmin, Ga,~, and Rn as a function of frequency. At 2.5 GHz the characteristics are: NFmi~ = 0.3 dB, G~,~ = 19 dB and Rn - 41 f~. These results are comparable to the noise characteristics of SiGe HBTs [35]. The good noise performance is due to collision free transport of electrons in tile strained Si channel. The results of Enciso et al. [35] show that the n-Si MODFETs have a good potential for application in mobile microwave communications.
7.4.5
Circuit performance of M O D F E T s
Due to their low power consumption, CMOS transistors are important building blocks in digital integrated circuits [214]. CMOS technology is very mature. Recently it has been shown that speed-power performance of CMOS can be significantly improved by using the MOS transistors fabricated using SiGe strained layers [214]. The design suggested in [214] is planar and avoids inversion of the Si layer at the oxide interface. The CMOS is fabricated on a relaxed Si0.rGe0.a buffer. It consists of a Si quantum well under tensile strain for the electron
C H A P T E R 7. F E T S AND OTHER DEVICES
212
100
vm.e.s v
1_=._-=--=0.2 um k)aded)
oaOed) =10 fF)
o
=1o fF)
2 0=
lO
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~L
l
I
l
I
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t
l
l I
015 V
.
.
l
100 stage delay (ps)
.
.
I
!
I
I
I
I
I
1000
Figure 7.13: Power delay product versus delay for Si/SiGe HCMOS and Si bulk CMOS. The corresponding drain bias values are indicated on the curves (Sadek 1996 [214]). 9 1996IEEE channel and a Sil_xGex compressed quantum well for the hole channel. Simulated performance of an 11-stage CMOS inverter ring oscillator is shown in Fig. 7.13. This figure shows the power-delay product as a function of average stage delay for the unloaded and loaded cases. The energy per switch decreases as V2D (VDDis the drain bias) but at the same time stage delay increases making the performance of the circuit poorer. Assuming that all the design parameters (device length, width, oxide thickness, series resistance, threshold voltage and interconnect and junction capacitances) have been optimized, the performance at a given voltage can be improved only by increasing the mobility of the carriers. It is here that SiGe quantum wells play a crucial role. It can be seen from Fig. 7.13 that the performance of the SiGe CMOS is superior in both the loaded and the unloaded cases. In the loaded cases the SiGe circuit can operate at 1.2 V retaining the same stage delay as the pure Si circuit operating at, 2.5 V. For a stage delay of 55 ps, the power-delay product in the SiGe CMOS improves by a factor of 4.6.
7.5
Strained-layer M O S F E T s on insulator
Gs et al. [12]have again emphasized the importance of tensile strain in Si channel for increasing the electron mobility. We have already discussed that tensile strain splits the 6-fold degenerate conduction band valley, a 2-fold degenerate state moves down and a 4-fold state moves up. The inplane effective mass of the electron decreases and intervalley scattering is suppressed resulting in considerable enhancement of the electron mobility. A spectacular velocity
7.5. S T R A I N E D - L A Y E R
MOSFETS ON INSULATOR
213
overshoot [12] is also predicted. In spite of these advantages bulk Si/SiGe subb100 nm CMOS technology still suffers some inherent limitations. Some of the inherent limitations can be overcome by using SOI technology. SOI devices are more radiation tolerant, short-channel effects van be more effectively controlled and have lower parasitic capacitance. By combining the strained channel with SOI technology (i.e. strained SOI technology) one can use advantages of both and remove some of the deficiencies they present when used separately. The mobility in strained SOI or strained SGOI are significantly larger than in SOI. Gs et al. [12]have investigated the electron transport in strained Si inversion layers by solving the Boltzmann transport equation and confirmed the above advantages. They have also found that enhancement of mobility depends on the thickness of both the SiGe layer on which strained Si layer is grown and on the thickness of the Si layer.
7.5.1
Strained-layer p-MOSFETs on insulator (strained SO1)
Silicon on insulator (SOI) MOSFETs are useful for sub-100 nm CMOS circuits. They have reduced parasitic source drain capacitance. The short channel effects can be suppressed and mobility can be increased by thinning the active semiconductor layer without increasing the dopant concentration [42]. The fluctuations in the threshold voltage are also reduced. Simple mesa isolation technology can be easily used in this technology. However hole mobility being small, the switching speed of the sub-100 nm devices is limited. The mobility can be increased and the advantages of SOI can be realized if strain is combined with SOI technology. Mizuno et al. [42, 21] have constructed SOI p-MOSFETs with a strained Si channel. The process flow and schematic structure of the MOSFET are shown in Fig. 7.14. Important steps in the process are the fabrication of relaxed SiGe layer on the buried-oxide layer produced by SIMOX (separation by implanted ox_Kygen) technology and growth of high quality strained Si layer on the relaxed SiGe film. A 5 nm gate-oxide was formed by thermal oxidation at 800~ [42, 21]. Source and drain regions were formed by implantation of 35 keV BF2 and annealing at 900~ for 30 min. TEM pictures showed that interfaces of the buried oxide were flat and there were no misfit dislocations in the strained Si layer. AFM pictures showed good surface morphology after SIMOX and also after growth of the strained Si layer. The Raman shift from the SiGe layer and from the strained Si layer showed that Ge content was 10%. The Ge content of the GeSi layer remained constant even after the high temperature SIMOX annealing because the buried oxide prevented diffusion of Ge towards the substrate. The MOSFET showed good FET characteristics. Hole mobility was higher than the universal mobility [191,238] of conventional MOSFETs. Transconductance of the strained layer MOSFETs was also higher than that of the control Si MOSFETs. However some amount of drain leakage was observed in the subthreshold region. Recently it has been demonstrated that relaxed SiGe layers can be grown on a insulator layer resulting in the SGOI (SiGe on insulator) technology. Mizuno
214
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
Figure 7.14: (a) Process steps for fabrication of strained-SOI substrate (I, II, and III) and MOSFET (IV and V). (b) Schematic cross section of strained SOI MOSFET (Mizuno 2001 [42]). 92001 IEEE
et al. [4] deposited a 300 nm strained Si0.9Ge0.1 layer directly on a Si substrate. The SIMOX process was then used to create an oxide layer between the Si substrate and strained SiGe layer. During this process the strained SiGe layer relaxes by a slip between the layer and the buried oxide. Since the Ge content is low and the thickness of the layer is small, annealing could be carried out at 1300~ to form the continuous buried layer. Finally the SiGe layer was thinned and its Ge content increased by low temperature annealing in Ar-O2 mixture. The relaxation now was 93%. Tezuka et al. [3] have used a somewhat different technology to produce small mesas of relaxed SiGe (without any dislocations) on silicon oxide. First thin pseudomorphic SiGe layers were deposited on SOI substrates. Circular mesas of SiGe and Si were produced by chemical dry etching. These mesas were oxidized in pure oxygen ambient at 1200~ and 1050~ Ge content in the SGOI layer and in Si layer increased as the Ge atoms were rejected from the growing Silicon oxide. The oxide layer blocked the diffusion of Ge out of the SiGe layer. The radius of the mesas varied between 0.2 and 5 #m. The mesas were relaxed and completely free from dislocations. This provides a good substrate for growing strained Si layers for n-MOSFETs. In their most recent paper [21] Mizuno et al. improved further the design of the MOSFET. They fabricated a double SiGe (second-Si0.s2Ge0.1s/firstSi0.93Ge0.07) relaxed structure which made it possible to introduce higher strain in the Si channel. The hole mobility increased by 30% over the universal mobility and 45% over the control Si MOSFET mobility. In SIMOX technology the structure is subjected to temperatures > 1300~ During this step misfit defects can be created in the SiGe or Si strained layers. Huang et al. [50] have used the wafer bonding and hydrogen induced transfer
7. 6. H I G H - K G A T E - I N S U L A T O R S
215
technique to prepare SiGe layers on insulator substrates. Strain relaxed SiGe layers (15% to 30% Ge) were grown by UHVCVD at 500-550~ The thickness of the SiGe layers was 1-2 #m. The degree of strain relaxation was > 90%. H + with a dose of 2.5-5 • 1016/cm 2 was implanted with an energy such that its peak was near the top portion (away from the network of misfit dislocations) of the SiGe layer. After the chemical mechanical polishing and cleaning process the substrate (known as a donor wafer [39]) was bonded to a Si wafer (known as a handle wafer) with 300 nm of thermally grown oxide. The structure was thermally treated in the temperature range 300-500~ to separate the two parts at the peak of the hydrogen concentration (this technique is known as the "smart cut" technique). A high quality strained Si layer was grown on the relaxed SiGe layer. Modulation doping was used to produce carriers in the strained channel. Electron mobility of more than 35000 cm2/Vs were obtained at low temperatures. Cheng et al. [39] have also used the wafer bonding technique to fabricate strained Si layer on insulator. They removed the donor wafer by the etch-back technique. Electron mobility larger than the universal mobility was observed.
7.5.2
Thin-body MOSFETs
A thin-body (i.e. with small thickness of the channel) MOSFET is essentially an extension of the fully depleted SOI MOSFET discussed in the previous subsection. Yeo et al. [18] have demonstrated a 50 nm thin-body SiGe strained layer MOSFET on insulator. 50 nm channel is the shortest channel length of any MOSFET reported so far. A schematic cross section of the thin-body MOSFET was shown in Fig. 7.1(b) and the band-structure was shown in Fig. 7.1(c). The carrier profile is also shown schematically in Fig. 7.1(c). In the thin channel the source to drain current is restricted to a path close to the gate and therefore control of the gate is better. Subsurface leakage currents are suppressed. Short channel effects are suppressed without the need to dope the channel heavily. Dopant impurities in the channel cause degradation of mobility and fluctuation of threshold voltage [18]. The thin-body MOSFET has a buried oxide wall below the channel. The Ge concentration in the channel was graded from 0 to 30% (bottom to top). A 4 nm Si cap provides a good interface. The simulated charge density in the SiGe channel and in the parasitic Si channel is shown in Fig. 7.2. Process steps have been described in detail by Yeo et al. [18] (see Fig. 8 of their paper). The output characteristics of the MOSFET are compared with that of the control Si channel MOSFET in Fig. Fig. 7.15. There is significant (up to 70%) improvement in the drive current due to both the strain in the channel and to the thin-body structure.
7.6
High-k gate-insulators
The SiO2 gate dielectric has to be made ultra-thin for sub-100 nm MOSFET devices. As the thickness is scaled to a few nano-meters, gate leakage current due
216
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
0.5 W/L = 5 . 0 ~ / 0 . 0 5 ~ n
~,, 0.4
- - - a - - SiGe-channel --o--
Si-channel
_~
"-,~0.3
0.2
0.1 0.~
90
-0.5 -1.0 Drain Voltage gns (V)
-1.5
Figure 7.15: Output characteristics of the SiGe channel and Si channel thinbody p-MOSFETs. The higher hole mobility in the SiGe channel results in a 70% improvement in the drain current at VDS = --1.5 V and V c s - V T H - - -1.2 V (Yeo 2002 [18]). 92002 IEEE
to direct tunnelling becomes a problem. This has provided the motivation for finding alternative high k gate insulators [28, 70, 16]. A1203 and HfO2 reduce the gate leakage current of Si MOSFETs by orders of magnitude. However these dielectrics cause instability of threshold voltage and degrade the mobility. These disadvantages can be overcome to some extent by using strain to increase the mobility [16]. Several other insulators with high-k have been investigated. Notable among them are Ta205, TiO2, Zr202, ZrSi~O~, and HfO2. Equivalent oxide thickness (EOT) with some of these materials is as small as 5 A. Recently efforts have been made to find new high k insulators [28, 70]. Rim et al. [16] have fabricated strained Si n-MOSFETs using Hf20 as the gate dielectric. A thin tensile strained Si layer was grown on a 1.5 #m relaxed Si0.8~Ge0.15 layer by UHVCVD. Control devices on CZ Si (with no strain in the Si channel) were fabricated for comparison. As compared to the CZ Si devices, the leakage current was reduced by a factor more than 1000 and hole mobility in the channel increased by 30%. Ngai et al. [28] have designed and fabricated SiGe strained layer p-MOSFETs using high-k ZrO2 as the gate insulator. ZrO2 was deposited by the dc magnetron reactive sputtering from a
7. 6. H I G H - K G A T E - I N S U L A T O R S
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Figure 7.16: Output characteristics of Si and SiGe p-channel MOSFETs with ZrO2 gate dielectric ( W / L - 800 #m/30 pm). Comparison of the two characteristics shows a net increase in the drive current of the SiGe transistor (Ngai 2001 [28]).
Zr target in an Ar+O2 ambient. No Si capping layer was used between the active SiGe layer and the gate dielectric. The active layer consisted of an n-type 350 A UHVCVD grown Si0.s5Ge0.15 strained layer. The output characteristics of the transistor are shown in Fig. 7.16. Pal et al. [70] have investigated the properties of Gd203, Ga203(Gd203), Y203, and Ga203 deposited on boron (1-2 x 101~ cm -a) doped Si0.74Ge0.26 strained layers. Dielectric films were deposited by electron beam evaporation. The insulator films were characterized by energy dispersed x-ray analysis, secondary ion mass spectroscopy, and ellipsometry. The metal-insulator-semiconductor structures were characterised using current-voltage, capacitance-voltage and conductunce~voltage techniques to determine the resistivities, breakdown strength, fixed oxide charge and interface state densities. A summary of the properties of the oxides is given in Table 7.4. All the rare-earth oxides (except Ga203) show good dielectric properties. They passivate the SiGe surface. The passivating property was optimised and the interface state density was the lowest with Ga203(Gd203).
These experiments [16, 28, 70] show that strained layers used with high-k gate insulators show great promise.
218
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.4: A comparison of various electrical parameters of the gate insulators (annealed at 450~ investigated by Pal et al. (2001) [70]. Ga20 3 (Sl)
Ga203(Gd203)
Gd203(S3)
Y203($4)
Film thickness
1975
2088
2056
2063
Refractive index er p (D.cm) Eb (MV/cm) JL (A/cm2) Dit(eV-lcm2) Qox (cm2)
1.59
1.77
1.83
1.95
(h)
7.7 7.7.1
10.0 1.6x1010 1.0 3.6X105 2.4x1012 6.0x1012
(s2)
12.3 6.1x1012 3.25 1.9x105 4.9x1011 8.4x101~
13.6 1.0xl014 3.3 3.5x10"8 6.3x1011 6.4x1011
16.0 6.8x103 4.0 3"6x108 5.4x1011 8.8x1011
MOSFETs containing Sil_x_yGe Cy alloys Sil_yCy channel n - M O S F E T s
As discussed earlier, tensile strain is required to fabricate a quantum well for electrons in Si. The graded SiGe buffer layers required to construct such channels are expensive and time consuming. Moreover they introduce threading dislocations in the active layer. Rim et al. [162] avoided the graded layer buffers and obtained tensile strain by introducing C in the channel. They fabricated n-MOSFETs with a Sil_uCy channel. The conduction band offset was found to be proportional to tensile strain and is equal to ,-~ 166 meV for each one percent of strain (see Fig. 1 of Ref. [162]).The MOSFETs had good turn-on characteristics and good sub-threshold behaviour. At room temperature the electron mobility is comparable (slightly smaller) to the mobility obtained with CZ control transistors. At 77 K the mobility was considerably degraded. Strain induced enhancement in the mobility was not observed. Presumably carbon introduces charged defects. Coulomb scattering by the defects and alloy scattering offset the increase in the mobility due to strain. Degradation of mobility in C containing layers has also been reported by Osten and Gaworzewski [190] and by Duschl et al. [90].
7.7.2
SiGeC p-channel M O S F E T s
John et al. [130] have investigated the characteristics of SiGeC channel pMOSFETs. Three transistors with different compositions of the channel were fabricated, a Sio.8Geo.2 channel, a Si0.793Ge0.2C0.07 channel and a Si channel
7.8.
ULTRA-SHALLOW JUNCTIONS
219
control device. In each case the channel length was 10 #m. The layers were deposited by UHVCVD. The thickness of the Si cap layer was 50/~. The dc characteristics were measured at room temperature and at 77 K. Hole mobility was extracted from the measured I - V curves. The subthreshold slopes were 101, 90 and 75 mV/dec in the three devices. At low fields and room temperature the mobility in C containing devices was higher. At room temperature the peak mobilities was 190 cm2/Vs in the device containing C and 140 cm2/Vs in the SiGe device without C. The enhanced mobility in C containing devices was attributed to lower density of process induced defects. However at high fields and/or at 77 K the mobility degraded and became smaller than the mobility in the SiGe device without C. The mobility in the Si control device was lower than that in the SiGe device. It was also lower that the mobility in bulk Si. Devices with larger concentrations of C to compensate the strain completely also investigated. They showed significantly degraded performance. There are other applications of carbon in Si based devices. Heinemann et al. [114]have shown that by using a carbon doped buried layer, Latchup can be suppressed. We have already discussed application of carbon in SiGe HBT technology in chapter 6
7.8 7.8.1
Ultra-shallow junctions Series resistance
Currently many groups are working on developing the technology for formation of shallow junctions with low series resistance [80, 81, 97, 106]-[113]. The International Technology Roadmap for Semiconductors (ITRS) [144] imposes several constraints on dimensions and dopant profiles in sub-100 nm gate-length transistors [108]. The expected evolution of junction depths and extension lengths (the distance between the silicide and the channel) as a function of year of introduction is shown in Fig. 7.17. The CPU gate-lengths are also shown in the figure. If the lengths are scaled as shown in this figure, it becomes necessary to scale the implantation dose and dopant concentrations to keep the series resistance within the acceptable limit. The series resistance has three components: the contact resistance Re, extension resistance P8 ^~xtr ~r and link-up or tip resistance Rtnk. The three components are shown in Fig. 7.18. Gossmann et al. [108] have discussed at length the contact resistance and the link-up (tip) resistance in the future sub-100 nm devices. (The link-up resistance is the resistance between two points A and B: The point A is the point where the doping concentration begins to decreases below its solubility limit and doping induced carriers also begin to decrease; the point boron is the point where the channel can be considered to begin i.e. where the carriers supplied by the inversion exceed the doping induced carriers.) These two resistances impose severe limitations on the technology. Gossmann et al. [108] have suggested possible methods to circumvent the limitations. We do not discuss the contact resistance here. The link-up resistance can be reduced by making the doping profile fall steeply by epitaxial
220
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
L gCPU-gate (nm) 22 I
......
200
32 I
70 85 120 65 80 100140 IIII III
--
EXTENSION
_
SOURCE:
LENGTH DEPTH
ITRS-99
99
-
00
-
02
03
-
*Y ~oo -
YEAR
_
50
04
08 l
ll
--
14 0
I
97 JUNCTION
150
45 I
.
IJ
I
35
"
~,
I
50
ii
: :,,,.,, lJl', _
I
I
i I
llJ
wd
I
70
IIII III 1O0120 150180 110130 165
I 250
L ~echnology(nm)
Figure 7.17: Junction depths and extension lengths as a function of technology node (bottom abscissa) and CPU gate-length (top abscissa). Also shown is the year of introduction [144, 108].
Figure 7.18" Schematic cross-section of a MOSFET. Three series resistance components, contact resistance Re , extension resistance t,~ .~=tr~ x t and link-up or tip resistance R~nk are shown [108].
221
7.8. U L T R A - S H A L L O W J U N C T I O N S
22
32
I
I
10 -
L~ Pu'gate (nm) 7 0 8 5 120 45 65 80 100140 I IIII III
SOURCE: ITRS-99
-
IMSIL
97
PMOS I SD = 0.35mA/pm
>6
Vextl + Vext2 = 0.05VDD
u.I YEAR
02
0403
os .,., ,, .,,,,
:
'~ --
In m
I 35
50
9II 9
9l
,,,.,'
11
0
99 O0 9 01 9
itlt 70
l ttl
I I
100120 150180 110130 165 I_}:jechnologY(nm)
250
Figure 7.19: Required boron implant energy for PMOS extension regions [108]. techniques. However this impacts the performance of the intrinsic device adversely due to spilling of carriers into the channel and increase of the leakage current. The optimal lateral steepness depends on many variables and has been discussed by Gossmann et al. [108]. For 5% voltage drop in both the extension regions, the sheet resistivity of the extension regions is given by [108],
pext _____0 . 0 5 VDD I/I/ s
2
1
Io---N Lr
(7.1)
where IoN is the on-current (=0.75 m A / # m for NMOS and 0.35 m A / p m for PMOS), L~=t is the length of the extension, and W is the width of the device. Gossmann et al. [108] calculated the extension sheet resistance for different technology nodes. These calculations show that to keep the resistance within the limits imposed by Eq. (7.1) the implantation dose and peak dopant concentration should increase by a factor between 5 and 100 in sub-100 nm devices. Since we know the geometry, dose and peak concentration of the dopant, it is possible to calculate the required implant energy. The calculated implant energy is shown in Fig. 7.19. We see that ultra-low energy implants are necessary. Today's implanters are capable of implanting species at 0.1 keV [109]. However very low energy implants cause technological problems. Ion implantation causes sputtering of the surface atoms. First Si surface atoms are removed and the Si surface recedes. The high boron concentration
222
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Figure 7.20: Retained boron dose is plotted as a function of boron implant dose for two different implant energies [109]. 92000 IEEE region moves closer to the surface. Now the sputtering yield of boron atoms increases. As the implantation proceeds and the concentration of boron increases, the loss of boron ions by sputtering increases [109] and the relative retained dose decreases further. The measured retained dose as a function of nominal dose is shown in Fig. 7.20. The results obtained using two different implant energies are shown. At high energies (> 2 keV) the retained dose is close to the normal implant dose and follows the dashed straight line. As the implant energy decreases to below 2 keV, the retained dose decreases dramatically. If BF2 instead of boron is used for implantation, loss of boron by sputtering becomes larger [109] (not shown in the figure). During thermal annealing of the shallow junctions, a larger fraction of boron is lost by out diffusion into the ambient. If low energy implantation is done through a deposited or native oxide layer, a significant fraction of boron is implanted into the oxide and is lost. We conclude that the implant energy should not be decreased too much. 7.8.2
High ramp
rates and spike anneals
Effect of ramp-rates The TED decreases with the depth of the junction (the junction depth is approximately equal to the projected range of the implant) [109, 20, and references given therein]. However TED is still a problem in the shallow junctions. The early experiments showed that the duration and magnitude of TED decreases rapidly as the temperature of annealing increases [20]. The {311} extended defects are not stable at high temperatures. Instead of inducing significant TED, the Si interstitials find other pathways (diffusion to the surface, into the substrate, recombination with vacancies or pairing with other defects) to disappear. At high temperatures the effective activation energy for the TED is negative [109]. This means that if the temperature can be increased to high
7.8.
ULTRA-SHALLOW JUNCTIONS
223
values very rapidly TED is suppressed. Two methods of rapid annealing, conventional rapid thermal annealing (RTA) and spike anneal, are used to suppress TED. Mannino et al. [80, 81] have investigated the effect of RTA ramp rates on boron marker-layers implanted in Si. RTA was done with ramp rates of 0.1, 1.0, 10, 100 and 300~ Two peak temperatures, 950 and 1100~ were used with a soak time of a few seconds. In each case diffusion length LTED Was calculated using the relation L~E D -- (a 2 --a02) where a is the standard deviation and the subscript '0' indicates the as grown layer. LTED decreases substantially with the increase in the ramp rate. For example while annealing at 1100~ LTED decreases from 40 nm to 20 nm by increasing the ramp rate from 1 to 100~ At this high ramp rate the thermal displacement is only 3 nm. It appears possible to suppress the TED completely by increasing the ramp rate sufficiently. However very high ramp rates will be required. The TED increases with the total implantation dose because the total number of injected interstitials becomes large. Thermal diffusion becomes significant above 900~ If the peak annealing temperature is 1100~ the thermal diffusion becomes quite large. The thermal diffusion is also suppressed considerably by increasing the ramp rate.
Spike anneals There is 0 s soak time in the ideal spike anneal. In practice the soak time is finite but small. Spike anneal has several advantages over the conventional RTA with several seconds of soak time [109, 110]. Spike anneal yields significant improvements in the junction depth and reduces overall thermal budget. This in-turn reduces total lateral diffusion per side in a p-MOSFET by 25% without changing the extension implant. More recently Lindsay et al. [110] have investigated the effects of RTA, spike anneal and oxide thickness on the boron profile (see Fig. 7.21). In the RTA the soak time was 10 s and in the spike anneal it was 1 s. The up-ramp rates were 100~ for the spike anneal and 50~ for the soak anneal. The corresponding down rates were 80~ and 50~ respectively [111]. Fig. 7.21 shows that the TED is significantly higher in the slow-ramp soak anneal than in the fast-ramp spike anneal. The abruptness also degrades by the soak time and by the thicker oxide. Lindsay et al. [110] found that the oxygen content in the ambient also affects the junction depth and the resistance (not shown in the figure). The literature values of resistance versus junction depth [109] are plotted in Fig. 7.22. This figure shows that several data points overlap even though their process parameters are not identical [109]. This happens because both junction depths and resistance do not depend uniquely on any one parameter e.g. the ramp-rate. They depend on implant energy, implant dose, ramp rate and soak time. If smaller energy or dose are used, shallow junctions with higher resistance are obtained. The same result is obtained with somewhat larger doses or energies but high ramp rate [109]. Agarwal et al. [109] have investigated the SIMS profiles in Si implanted with boron without removing the native oxide
224
C H A P T E R 7. FETS AND OTHER DEVICES
lx1021~--~ ]~t ~'E 1 • o ~'~ lxlO19
I
Rs ah,pt] 1x1021~ SpikelxlO15328 8nm I ]~ llnml ~".~ ~ Eo lx1020
--
~'
O0
I
spike\
~oak
~ lxl018 8
6 lx1017
Rs abrupt SpikelxlO15 598 8nm 5 480 lZlnm - -- --
20
40 60 depth (nm)
lx1017
100
80
O0
20
40 60 depth (nm)
100
80
Figure 7.21: SIMS profiles and resistance R s for spike and soak annealed boron implanted samples. The implantation was done at 0.5 keV with a dose of 1 x 1015 cm -2 through i nm and 4 nm oxides. The abruptness degrades by the soak in RTA and also by the thicker oxide. The abruptness (abbreviated as abrupt) is defined as the change in depth corresponding to the change in concentration from 1 x 1019 cm -3 to 1 x 1018 cm -3 and is measured in nm as shown [110].
2000
'
I
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'
I
'
I
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1000 E 9
lO0_J
O0
I
t
I
20
40
60
80
I00
,
120
xj at 1x 1018 cm-3 (nm) Figure 7.22- Comparison of sheet resistance and junction depth data from various sources compiled by Agarwal et al. [109]. Despite the fact that different rates and ion implantation parameters were used, all the data from spike anneal fall in a rather narrow band with approximate 1Ix dependence [109].
225
7.8. U L T R A - S H A L L O W J U N C T I O N S 1021 --, 1020
%__
g 1019 ~ 10TM
r~
1017 ]
_ , J !
O0 10
~
20
1
30
---r-
40 50 60 Depth (nm)
-
. - -
70
-
.
. . . .
80
90
Figure 7.23: SIMS profiles of boron junctions after implantation (A - 1 keV B, 1 x 1015 cm -2 into crystalline Si; B - 4.5 keV BF2, 1 x 1015 cm -2 into GeF2 pre-amorphized Si) and after spike annealing (A-*C, B--+D; ll00~ 1 s) [60].
from the Si surface. Several doses and two energies, 0.5 keV and 0.2 keV, were used. The implanted wafers were spike annealed at 1050~ The SIMS profiles for the 0.2 keV implant with a dose of 3 x 10 TM cm -2 and for the 0.5 keV implant with a dose of 1.7 x 10 TM cm -2 were nearly identicM. It is therefore possible to avoid the ultra-fast ramp rates but modify the implant parameters to obtain the same results. In order to avoid non-uniformity and non-repeatability the ramp rates should not be too high. For future sub-100 nm devices sub-1 keV implants will be required. The discussion of this section shows that the implant energies below 0.5 keV are not desirable and may not be necessary. Similarly spike anneal with high ramp rates is required but too high ramp rates are not recommended. The ambient in which annealing is done also affects the junction depth and resistance. It is a challenging task to achieve an optimum design for sub-lO0 nm transistors by adjusting implant dose, energy, ramp rates, ambient and oxide layer thickness so that each of these parameters is utilised optimally. The design must ensure that the uniformity is maintained and the process is repeatable. Other methods of reducing TED are also being tried. TED can be reduced by amorphization prior to ion implantation using isoelectric ions [20]. The clustering of boron near the peak which makes the boron immobile is eliminated by the amorphization process. Pre-amorphization of the Si surface prior to boron implantation leads to a reduction of the channeling tail, thereby allowing for shallower, more abrupt junctions. In addition, it has been found that implanting BF2 instead of boron (at the same equivalent boron energy) results in shallower junctions after annealing, a result which is tentatively ascribed to the co-implanted fluorine. In an approach to combine these two benefits, pre-amorphization with GeF2 ions has been used to fabricate shallow p-type junctions. Fig. 7.23 shows boron concentration profiles after implantation and after spike anneMing (ll00~ 1
226
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
s). By changing from a 1 keV boron implant into crystalline Si to a 4.5 keV BF2 implant into GeF2-pre-amorphized Si, a significant reduction of the channeling tail is seen, as expected. A spectacular difference in junction depths is observed for these two samples after spike annealing: the junction depth Xj is decreased from 65 nm for the reference sample to 30 nm for the GeF2/BF2 sample. Changing the concentrations of co-implanted fluorine by using other implant variants (always with the same effective Ge and boron implant energies) leads to a proportional scMing of X j in between 30 and 65 nm. This suggests that the junction depth reduction is strongly related to the co-implanted F. Indeed, SIMS measurements after RTA show that going from BF2 implantation to GeF2/BF2 leads to a significantly stronger incorporation of F into the near surface region. This suggests that fluorine probably traps Si interstitiMs and reduces the driving force for TED. Alternatively, the reduced junction depth may result from a chemical interaction between F and B. Clearly, this subject needs further investigation. The sheet resistance Psh for the shallowest junction (Xg-30 nm) is 390 ~/sq. These junction parameters are among the best obtained until today using ion implantation and rapid thermal annealing, breaking through the trade-off curve between Xj and Psh that is generally observed for ptype junctions. It is expected that further optimization of the pre-amorphization and implantation conditions (e.g., < 1 keV B) together with more aggressive spike anneals will lead to additional improvements in junction performance. The approach of pre-amorphization with co-implanted fluorine (PAF) was used for forming extensions in a 0.13 #m PMOS process flow, featuring a 2.3 nm pure gate oxide. From electrical analysis it is found that the underdiffusion of the extension decreases with increasing fluorine concentration. For the implant/anneM variants shown in Fig. 7.23, the overall source/drain underdiffusion is reduced by 25 nm when using GeF2/BF2, consistent with the measured reduction in X j. Furthermore, the measured source/drain series resistance was ~ 500 f~#m, with a 10% improvement with the PAF approach. It can therefore be concluded that PAF is suitable for the fabrication of sub-100 nm PMOS transistors. One drawback, however, is that the co-implanted fluorine is observed to enhance the penetration of boron through the thin gate oxides, leading to undesired shifts in the threshold voltage. This implies that a successful implementation of PAF may require the utilisation of heavily nitrided gate oxides (or high-k dielectrics) to increase the resistance against boron penetration. Alternatively, the CMOS processing scheme could be modified to prevent the introduction of fluorine atoms into the gate electrode during extension implantation.
7.9 7.9.1
Application junctions Raised
of
SiGe
source and drain
to
ultrashallow
junctions
Recently several groups have used SiGe technology to improve ultrashallow junctions for deep submicron technology [102, 49, 50, 51, 24, 75, 23]. Raised
7.9. A P P L I C A T I O N OF SIGE TO U L T R A S H A L L O W J U N C T I O N S 20
A
v
E
. . . . . . . . . . . . . . . V --4-- Conventional at 0~ 18 \ . . o - . Conventional at -50~ - Sio.aeGeo.14at 0~ 16 , ' ~ " 'r Sio aeGeo14 at-50~ O
14
,
=. " ~ " V .
'
"
~
1
.
2
'o 1.16
W = 100 p,m .
9
,
0.2
o
O.3 Lg
(~m)
.
9
0.4
.
.~.
Sio.se_Geo.141,
0
m .
~ ... 0-9 . Sio.91Geo.oelOOnm 00nml~"~.,~,o~.~
1.22
E C~ 12
8
"conve'n~afSi .......
1.26 o~----~1.24
227
.
1.14
~ a +Ion[-50~176bLg
. w = I(X) ~m . . . . . . . . . . 0.2
o.3
0.4
d
]
1 o.s
Lg (l~m)
Figure 7.24: (a) Saturated transconductance gm versus effective gate length at different temperatures for conventional and Si0.s6Ge0.14 RSD devices, and (b) Ratio of values of ION at -50~ and at 100~ versus effective channel length for conventional and Si0.s6Ge0.14 RSD devices (Huang 2001 [49]). 9 2001IEEE source drain (RSD) junctions have received considerable attention. Ultrashallow junctions with solid-state diffusion from SiGe have been formed. Sub-70 nm CMOS devices have been fabricated using recessed junction selective SiGe source/drains. Raised (also known as elevated) source and drain MOSFETs allow fabrication of shallow junctions and thicker sacrificial layers for silicided contacts to the junctions [319, 224, 49, 51]. In RSD technology Sil_=Ge= offers many advantages. Like Si, Sil_=Ge= can be deposited selectively over the exposed source and drain areas but SiGe can be deposited at lower temperatures. Sil_=Ge= gives lower contact resistance and higher current drivability [49]. Huang et al. [49] fabricated the RSD p-MOSFETs using UHVCVD. The experiments confirmed that the use of Sil_=Ge= improves transconductance and decreases the contact resistance. The improvements increase as the channel length is reduced. Due to the shallow junction depths and lesser implantation damage both drain induced barrier lowering and leal~ge current decrease when channel length becomes small ,~ 100 nm (see Fig. 7.24(a)). The low temperature behaviour of the devices shown in Fig. 7.24(a) and Fig. 7.24(b) is also very good. Gannavaram et al. [102] have presented a new technology useful for sub-70 nm CMOS. They selectively deposited in-situ boron doped SiGe at 500~ in the source drain windows recessed to the required junction depth. The technology meets the Roadmap requirement. For 30 nm junctions the sheet resistivity was < 100 gt/sq, and contact resistivity was 1.5 • 10-s ~tcm2. Reverse leakage was less than 1% of the I o f / b u d g e t . The lateral abruptness was perfectly box shaped. Thermal integration was compatible with high-k gate dielectrics using gate-last CMOS process flow. A comparison of sheet resistance vs junction depth curves of their technology with other technologies is shown in Fig. 7.25. In the current technology, low energy ion implantation (< 5 keV) is used to
228
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S 1
"~1
I
I
I
1
I
I~
~ ~ ~
"""
",~
~o ,,m " " " - ..
4.1 I ~.1.~, t '
'
-
~
b.
In
I
~,,~gSO
70 n m " -.
~0~"~~
I
-'-._
t
" ~
~
. . . . . .
~
~ : . . ,,v " - ~ _
I
I
I
I
Higher C R/TA temp
I
I
RTA -limit -~ curve
a,;" :: p.(o&~ I - "
. . . . . . . .
--
_
"~
-
102o," :, ..I
,,~ __~_.~_~___~a___
~t ~
"-..
/
This w o r k
1
~
"~
-
"~'-~.~10~0 ~ ~ Vc
~..
-
3
-...-./o%,, ?. '-t
I
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/
Figure 7.25" Compilation of best case junction RSH values for various junction formation techniques compared against future technology window (Gannavaram 2000 [102]). 9 2000IEEE form shallow junctions for nm channel-length regime. This results in degradation of current drivability [24]. The degradation occurs on two accounts: (1) source drain extension (SDE) overlap with gate is reduced and (2) carrier activation efficiency is degraded. To solve this problems Uchino et al. [24] have developed an advanced CMOS technology in which RSD windows and contact windows are formed over the field oxide. Ultrashallow junction formation occurs by solid-state diffusion from P doped SiGe and boron doped Si layers. Process steps for the raised source/drain n-MOSFET are shown in Figs. 7.26(a), 7.26(b) and 7.26(c). A cross-sectional SEM photograph of the n-MOSFET is shown in Fig. 7.26(d). Further details of the device are given in Tables 7.5(a) and 7.5(b). The junction depth was 25 nm and SDE resistance was 350 f~/sq for n-MOSFETs and 390 9t/sq for p-MOSFETs. Measurements showed excellent short channel characteristics. Drain-junction capacitance was reduced by 70 to 80%. A suitable overlap between SDE and gate was obtained and current drivability was high. 7.9.2
Poly-SiGeC
gate
It is advantageous to use n+-polycrystalline Si as the gate in n-MOSFETs and p+-polycrystalline Si as gate in p-MOSFETs in CMOS technology. Unfortunately boron from p+-polycrystalline gate penetrates through the gate oxide which results in changes in the threshold voltages. Polycrystalline SiGe gate is used because the workfunction of the gate can be adjusted by a few tenths of a volt by changing the Ge content. The sheet resistance of polycrystalline SiGe is lower than that of polycrystalline Si because grain size in the former is larger. However the problem of boron penetration and instability of threshold voltage
7.9. A P P L I C A T I O N OF SIGE T O U L T R A S H A L L O W J U N C T I O N S
229
Figure 7.26: Process steps for the raised source/drain n-MOSFET. (a)PolySi patterning and pocket implantation. (b) Selective p-doped SEG and SDE formation. (c) Tungsten local interconnection. (d) Cross-sectional SEM photograph of the finished n-MOSFET (Uchino 2001 [24]). 9 2001IEEE
230
C H A P T E R 7. F E T S A N D OTHER DEVICES
T~ble 7.5- (a) Device specifications and fabrication method. (b) Device purameters (Uchino 2001 [24]).
(a)
_
.|
,
Device
This work L
NMOS
i, ii ii
,i
.
l l llJIL
___
Drain area
0.35x10 pm
6.0xl 0 pm
S/D doping
Diffusion from P-doped SiGe
As i/i15 keV, 3x1014cm.2
Gate SiO2 thickness
4.6 nm
4.6 nm
i
PMOS
,
Cony.
ill
__
.
Drain area
0.40xl 0 pm
6.0xl 0 pm
SID doping
Diffusion from B-doped Si
BF2 i/i 10 keV, 5xl 014-cm.2
5.2 nm
4.0 nm
Gate SiO2 thickness |
i.
_ _
(b) Device
This work .
NMOS
,, .,,.,
Cony. , , .
Drain area
0.35x10 pm
6.0x10 pm
Drain capacitance
6.2 fF
19 fF
350 .Q/sq.
570 Q/sq.
Drain area
0.40x10 IJm
6.0x10 pm
Drain capacitance
11 fF
58 fF
Rext ,,,,,,,
PMOS
, |.
,
,,
, , , , ,
....
=
,.
...
Rext , . , , . . , . ,
390 .Q/sq. . . . . .
1.,
1060 .Q/sq
7.10. R E S O N A N T
231
TUNNELLING DIODES
persists. Chang et al. [136] fabricated p-MOS transistors in which a layer of polycrystalline SiGeC was introduced between the poly-Si gate and gate oxide. First n-Si was oxidized in dry oxygen at 900~ for 15 min, and a 80-90 A layer of silicon oxide was produced. Polycrystalline gates were deposited on top of the gate oxide by rapid thermal vapor deposition at 625 to 700~ After the growth of gate electrodes, 60 keV BF + was implanted to a dose of 5 x 1015 cm -2. Three types of samples were prepared. In one type, 400 nm of poly-Si gate was used. In the second type a layer of poly-SiGe was used between the gate oxide and the poly-Si gate. In the third type the SiGe layer was replaced by a SiGeC layer. The samples were annealed at 900~ for 40, 60 and 80 min and the threshold voltages of the devices were measured. The results are shown in Fig. 7.27. SIMS '
I
'
I
'
I
'
I
'
I
'
I
'
I
I 40
,
I 50
,
I 60
,
I 70
Oxide/Si
_
---<>---- O x i d e / S i G e / S i
>
6 -
~
Oxide/SiGeC/Si
e~0 o
>
4
O
2
0
, 0
I 10
,
I 20
,
I 30
,
,
I 80
A n n e a l i n g t i m e @ 900 C ( m i n )
Figure 7.27: Threshold voltages of the three devices are plotted as a function of annealing time (Chang 1999 [136]). measurements showed that boron diffused through SiGeC layer and segregated in the layer. Chang et al. [136] suggested that carbon reduces the potential of boron in the SiGeC layer and suppresses its outdiffusion into the oxide.
7.10 7.10.1
Resonant tunnelling diodes NDC
and
PVR
The principle of resonant carrier tunnelling has been known for a long time (see first edition of this book [1] for references). Applying a bias across a structure consisting of a quantum well and thin barriers surrounding it induces a small current by quantum mechanical tunnelling of the carriers through the barriers. The overall current through the device reaches a maximum whenever the energy of the injected carriers is in resonance with the energy of an eigen state of the
232
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
quantum well. Thus I - V curves show sharp peaks, and every peak is followed by a region of Negative Differential Conductance (NDC). The current voltage curves of the diodes show maxima (known as peaks) and minima (known as valleys). The Peak to valley ratio, PVR, is an important figure of merit of the device. The devices, known as resonant tunnelling diodes (RTDs), are very useful for high-frequency detection and oscillations. If there is one quantum well with two barriers, the device is known as a double barrier or DB device. If there are two quantum wells and three barriers, the device is known as a three barrier (TB) device. Discrete energy levels in a double barrier quantum well structure were observed in 1974 and resonant tunnelling experiments in the 1012 Hz range were performed in 1984 [1]. Interest in negative resistance devices has grown steadily over the past several years. Most early work been has been done on tunnelling of electrons in GaAs/A1GaAs [1]. PVR of 30:1 at 300 K, frequency of oscillation exceeding 400 GHz and switching time of the order of picoseconds have been obtained [406]. These RTDs are likely to play an important role in submillimeter-wave analogue applications and as multiterminal high-speed logic devices. Several papers have also been published on GeSi strained layer RTDs. Work has been done on tunnelling of both holes and electrons. Because of several inherent difficulties, the performance of these diodes is still not as impressive as that of the RTDs based on III-V compound semiconductors. 7.10.2
Resonant
tunnelling
of holes in GeSi devices
Temperature effects Since the valence band offset in GeSi layers under biaxial compression is large, GeSi strained layers grown on Si(100) substrate are well suited for the study of resonant tunnelling of holes. As discussed earlier, strain removes the degeneracy of the heavy and the light hole bands. It is possible to adjust the strain in such a manner that only the heavy or the light holes are injected into the system. GeSi strained layer RTDs were first fabricated in 1988 by Liu et al. [407] and by Rhee et al. [412]. The structure of diodes fabricated by Liu et al. [407] consisted of a GeSi quantum well separated by Si barriers and grown on a Si(100) substrate. Rhee et al. [412] fabricated the diodes on relaxed buffer layers of different Ge concentrations. They were able to distribute the strain between the well and barriers in any desired manner. By changing Ge concentration in the buffer layer, the barrier or the quantum well or both can be strained. This work was followed by several papers published from 1989 through 1993 (see references [410, 408, 409, 416]). However, the best PVR obtained until recently was only 3 at 4.2 K (the value has improved recently, see Table 7.7 given later). Gennser et al. [413] made extensive measurements of I - V characteristics of GeSi hole RTDs over a large temperature range. They derived resonant energies from the observed characteristics and compared them with the theoretically predicted values. The characteristics remain practically independent of temper-
7.10. RESONANT TUNNELLING DIODES
233
ature up to 70 K. In this temperature range, interface scattering probably limits the performance. If this explanation is valid, it should be possible to increase the PVR by improving the quality of the interface. Two resonances at 150 meV and 300 meV were seen in the I - V curve. They were identified as being due to the lowest heavy hole (HH0) and light hole (LH0) states, respectively. An additional resonance due to second heavy hole state (HH1) was seen in the (dI/dV) - V curve. For any bias value a temperature-dependent current was observed above 70 K. Temperature-dependent currents can arise due to thermionic current or thermally assisted tunnelling. At any bias value well below the resonant state, the current density JrCs can be approximated by [413],
J~s = A~Tln
(
l+exp-(Er-EF,
c-e~eV)/kT
1 + e x p - ( E ~ - EF,~- (1 - a ) e V ) / k T
)
'
(7.2)
where the prefactor A~ depends oil the transmission coefficient and effective mass, V is the applied bias, Er is the energy of the resonant level, EF, c is the Fermi level of the contact and aeV is the energy difference between the emitter valence band edge and the bottom of the quantum well. If the activation energy r = ( E ~ - EF, c - ~eY) >> kT, Eq. (7.2) reduces to
J ~ - A~T 2 exp(-r
(7.3)
The thermionic current is given by, Jthermionic
--
A*T 2 exp(-r
(7.4)
where A* is the effective Richardson constant and r162 is the barrier height. The two equations are similar as far as the temperature dependence is concerned. Gennser et al. [413] were able to fit the currents observed at different temperatures with two thermally activated terms of the form given in Eq. (7.3) or Eq. (7.4) plus a temperature-independent part I0 due to a pure tunnelling component. The magnitude of the activation energy did not correspond to any reasonable value of the barrier heights and it was therefore concluded that the thermionic component was negligible. By extrapolating the activation energy to 0, values of resonant state energy with respect to the Fermi level in the cathode were extracted. By allowing for the temperature effect on the Fermi energy, resonant energies were determined. The resonant energies were also calculated by solving self-consistently the SchrSdinger equation separately for the light hole and the heavy hole in square well potentials. Table 7.6 shows that the measured and calculated energies are in good agreement. In the analysis no mixing of the heavy hole and light hole bands was assumed. Since tunnelling measurements under applied magnetic fields show considerable mixing of these states, the agreement is somewhat surprising. The mixing might have been masked by the uncertainties of the calculations, resolution of the experiment and the simplicity of tile model used. Gennser et al. [413] also studied relative contributions of different resonances and concluded that at high temperatures the PVR is reduced due to tunnelling through higher-order resonances.
234
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.6: Calculated and measured values of the resonant states in meV measured from the valence band edge of the well (see text) [413]. HH0 LHO HH1 LH1
Calculated 25 + 3.5 57 + 7 100 + 12.5 220 + 35
Measured 37 + 5 50 • 5 81 • 10 191 + 20
Effect of magnetic field Extensive theoretical and experimental investigations of hole tunnelling in the GeSi RTDs under applied magnetic field have been made [351, 408]. As the magnetic field is applied parallel to the interface, the path of the holes passing through the interface is deflected. This is equivalent to reduction in the kinetic energy in the tunnelling direction and therefore additional voltage is needed to obtain the tunnelling currents. Using WKB approximation, the shift in resonant peak position is given approximately as eB2(2s 2 + 2b2 + w2)/3m *, where s, b and w are the thicknesses of the spacer, barrier and well, respectively, and B is the applied magnetic field [351]. This relation is well satisfied by the experimental data [351]. For a magnetic field in a direction perpendicular to the interface, the results are more complicated and not well understood.
Noise in R T D s Noise behaviour of a RTD is very complex [415]. The diode produced more noise at 77 K in the resonant tunnelling mode than at room temperature as a bulk resistor. The flicker noise varied as 1 / f 2 rather than 1 / f commonly observed in other devices. The magnitude of the flicker noise depended on both the magnitude of the current and on the polarity.
7.10.3
Electron tunnelling in GeSi RTDs
Electron resonance tunnelling in the GeSi structures has been studied by Ismail et al. [414], Chiang et al. [409], Krstelj et al. [416] and more recently by Suda et al. [25] and by Paul et al. [26]. Ismail et al. [414] fabricated the device on a highquality Ge0.3Si0.7 relaxed n type doped buffer layer grown on Si(100) substrate. The tunnelling structure consisted of a 5 nm Si well sandwiched between two unstrained Ge0.3Si0.7 barriers. There were two 15 nm Si layers on both sides of this structure. A phosphorous doped 30 nm GeSi layer and a 4 nm Si cap layer were deposited on the top of the device. Current voltage characteristics were measured at room temperature and at 77 K. At room temperature the PVR was 1.2. At 77 K the PVR improved to 1.5. There was a finite current at vanishingly small voltage, which indicates that the Fermi level on both sides
7.10.
RESONANT
TUNNELLING
DIODES
235
of the tunnelling junction is within -., l k T of the position of the lowest sublevel in the well. The slopes close to zero bias for the two polarities were different, indicating that the RTD was asymmetrical. Circuit oscillations in the NDC regime were seen. The onset voltage for NDC was about 0.5 V, considerably higher than the theoretically estimated value of 0.1 V, which shows that the internal resistance of the device was high. RTDs with qualitatively similar structure have been fabricated and studied by Krstelj et al. [416]. Ge concentration in the relaxed buffer layer and in the barrier layers was x -- 0.35, the width of the well was 2 to 5 nm and that of the barriers, 4 to 7 nm. The characteristics of the diode were symmetrical. Two distinct peaks were observed in the current voltage characteristics at 150 K. As the temperature was lowered, the low-voltage peak disappeared below 50 K. At 4.2 K, the PVR had its largest value of 2. Krstelj et al. [416] suggested that the anomalous behaviour of the lowvoltage peak may be due to phonon-assisted tunnelling or quantization of the emitter states. At higher temperature both mechanisms can cause tunnelling. In the first case, the phonons are available only at the higher temperatures. In the second mechanism, higher states of the barrier are occupied at higher temperatures, from which tunnelling is possible at a lower voltage. Like the hole RTDs, the PVR is small in the electron RTDs. The performance of GeSi RTDs has not yet reached a level that can be exploited in any useful device. However, according to theoretical predictions, a high value of PVR in the range of 10 to 30 is possible at 77 K [409].
7.10.4
R e c e n t work
Recently several groups have reported improved SiGe resonant tunnelling diodes [26, 25, 2]. We have collected the PVR values obtained by different groups in Table 7.7. This Table shows that in the earlier data the highest value of PVR is about 2 and this value was obtained only at low temperatures. No NDC in hole devices has been observed above 77 K. Best value of PVR (>_ 7.6) at room temperature has been observed recently in electron devices by Suda et al. [25]. We discuss this work in detail in this section. Suda et al. [25] fabricated both DB and TB electron devices and compared their NDC performance. The devices were fabricated using gas-source MBE on a 0 . 8 - 1.2 flcm n-type Si(001) substrate. The Ge fraction x in the Sil_xGex barriers was 0.3. The structure, layer compositions and thicknesses are shown in Fig. 7.28(a). The SiGe barriers were unstrained and were grown on strain relaxed SiGe buffer layers. The buffer layers consisted of alternating Si0.8Ge0.2 and Si0.rGe0.3 layers as shown in the figure. The tensile strained Si layer was grown on top of the strain relaxed layers. A DB or a TB device was fabricated on this layer. Fig. 7.28(a) shows the structure of the TB device. The observed current voltage curves for both the DB and the TB devices are shown in Fig. 7.28(b). The performance of the TB device is very superior. The PVR of the first resonance is a record value of 7.6.
236
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.7: Comparison of observed PVR values of Sil_xGex RTDs.
x
Carder
Number of barriers
0.21
hole
2
0.22
hole
3
0.4
hole
2
0.5 0.3
hole electron
2 2
0.35
electron
2
0.3
electron
3
4.2 77 10 > 100 4.2 77 15 77 300 4.2 > 220 300
0.3
electron
3
77
Temperature (K)
PVR
Ref. No.
2. 1.8 1.1 NO 2.1 1.6 1.5 1.5 1.2 2.0 NO > 7.6
a a b b c c d e e f f g
1.67
h
(a) Liu 1988 [407], (b)Xu 1992 [411], (c) Rhee 1988 [412], (d)Gennser 1991 [413], (e) Ismail 1991 [414], (f) grstelj 1993 [416], (g)Suda 2001 [25], (h) Paul 2001 [26].
7.11
Photodetectors, waveguide switch and laser
7.11.1
IR
photodetectors
We have given an exhaustive review of SiGe based photodetectors in the first edition of this book [1]. More recently Jutzi and Berroth [89] have written a good review of SiGe photodetectors for optical communication application. We discuss more recent work on the detectors [14, 89, 87, 88] in this section. Because of the indirect bandgap, the absorption coefficient in SiGe alloys is small and large thicknesses of the layers are required for efficient detection of light. However the maximum thickness of the layer is limited by the critical thickness. Li et al. [14] inserted the absorption layer between two mirrors which form a resonant-cavity. Incident light is reflected by the two mirrors and travels back and forth which increases the total amount of light absorbed and enhances the performance of the detector. The detector is known as a resonant-cavityenhanced (RCE) photodetector. The pattern of interdigitated contacts and the schematic cross section of the metal-semiconductor-metal (MSM) detector is shown in Fig. 7.29. The absorption region consists of Sil_xGex/Si MQWs. The MQWs consisted of twenty periods, each period contained Si0.70Ge0.30(6 nm)/Si(25 nm) layers. An optimized detector requires that RI -- R2e -~d where R1 and R2 are the reflectivity of the front and back mirrors [14]. To increase the
237
7.11. PHOTODETECTORS, WAVEGUIDE SWITCH AND LASER
C'O'nO i Layer
si 6~ x
t.
9
L
t
....
9
-
.
PVR = 1.3 HE,->HF~
PVR = 7.6
/
eV
=
P,= J
50 !"
I I si?,~o~ 30A I 1 " Layer
9
I Sil.xGexlSi RTD 70l" RoomTemperature
..... B Sio.?Geo.3 30 h B " Si 60 A (well) I" TripleBarrier BB SioTGeOS30 X BB" Structure C s,~o, ,w,,, j -
Strained
|
HEo'>H~
'%
O
~' HEr
.. _.
Strain Relief
~yer
,~./////////4[ Si epilayer1500A YI~ V / / / / / / / / / ~
(a)
V////////A
n-Si(O01) ~,......,, ~
u0
0.5
(b)
1
1.5 Voltage
2
(V)
Figure 7.28: (a) Structure of TB Si]_~Ge~ electron tunnelling RTD and the band lineups calculated using the model of Ref. [341] and (b) Typical I - V curves observed at RT from the DB and TB electron RTDs (Suda 2001 [25]).
Figure 7.29: (a) Pattern of interdigitated electrodes and (b) schematic cross section (along the dotted line in (a)) of the SiGe/Si RCE MSM photodetector by wafer bonding technique (Li 2002 [14]).
238
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
reflection coefficient, the bottom mirror is a SiO2/Si distributed Bragg reflector (DBR) and the top mirror is A1203/Si DBR. The device was fabricated by the "smart cut"" and bonding technique described earlier. The area of the active region was 100 x 100 #m 2. The simulated photoresponse of the detector is shown in Fig. 7.30(a). Refractive indices of 3.5 for Si and 4.0 for Ge were 0.30
(a)
0.25
~', r @
0.20
E KI
0.15
"~; E =
0.10
r
0
0.05 0.00 ....
L __
I .....
i
1300
1290
1310
Wavelength(nm)
4O
,~
.z-
35
.>_ w r-
o
e,i
30
o
25 l
1260
0
!
1270
1
i 0
l 1290
.
i 1300
.
I 1310
i
l 1320
,
i 1330
,
i 1340
,
i 1350
, i360
Wavelength (nm)
Figure 7.30: (a) Simulated quantum efficiency of Si0.TGe0.3 of the SiGe/Si MQW RCE MSM photodetector and (b)Observed responsivity spectra of the same detector (Li 2002 [14]). used in the simulations. The refractive index of SiGe alloy was obtained by linear interpolation. The absorption coefficient of Si0.70Ge0.30 at 1300 nm was estimated to be 40 cm -1. The peak quantum efficiency at 1300 nm was about 25% and the FWHM of the responsivity was less than 1 nm. The breakdown voltage of the detector was 10 V and the dark current at 5 V was 230 nA. Fig. 7.30(b) shows the experimental responsivity of the detector. The figure shows a responsivity of 44 m A / W at 1314 nm and an FWHM of 6 nm. The measured quantum efficiency at 1314 nm was 4.2%, considerably lower than expected on the basis of the simulations. The discrepancy was attributed to the poor quality of the DBR due to inaccuracy in processing and scattering of light due to surface roughness. Nevertheless the detector fabricated by wafer
7.11. P H O T O D E T E C T O R S ,
WAVEGUIDE SWITCH AND LASER
239
bonding technique with DBR mirrors is a significant advance in the detector technology for application to 1.3 #m operation. Krapf et al. [27] have reported a Si/SiGe quantum well Infrared photodetector (QWIP) suitable for multispectral imaging. A QWIP was grown by MBE on a high resistivity n-type Si substrate. The device consisted of 20 periods of SiGe/Si QWs. Each period consisted a of boron (9.6 x 1011 cm -2) doped 30 /~ Si0.77Ge0.23 well and a 500/~ undoped Si barrier. A 300 A wide Si0.77Ge0.23 emitter p-doped to a concentration of 4 x 1018 cm -3 was grown on top of the QWs. Finally the whole structure was capped with heavily p-doped 5000/~ Si layers at the top and bottom. The photocurrent response of the detector was measured at 10 K. It showed peaks at 1300, 1800, and 2500 cm -1. A broad band at 4000 cm -1 was also observed. The first three peaks were assigned to HHI-~HH2 inter-subband transitions in the QWs, HH--.(SO+LH) intervalence band transitions in the SiGe emitter and H H ~ ( S O + L H ) transitions in the QWs. The device is capable of detecting at long, mid and short wavelength atmospheric windows. Luan et al. [141] have fabricated Ge photodetectors using 1 #m Ge epilayers grown by the two step method described in chapter 2. The external responsivities were 550 mA/W at 1.32 #m and 250 mA/W at 1.55-#m. The electron mobility in the Ge layers was 3500 cm2/V s. 7.11.2
Optical
waveguide
switch
Optical switches have many useful characteristics. They have small size, singlemode operation and they are independent of polarization. Li et al. [10] have given a list of references on the optical switches fabricated using SiGe materials. The switches rely on carrier induced refractive index changes. In the reflection type switch the reflecting interface must be precisely controlled. Li et al. [10] have fabricated an intersectional rib optical waveguide switch with a bow-tie electrode. These switches are better than those with straight electrodes. The switch is based on the totM internal reflection and the plasma dispersion effect of SiGe alloy. It is suitable for 1.3- and 1.5-#m operation. The schematic structure of the switch is shown in Fig. 7.31(a) and that of the waveguide in Fig. 7.31(b). The width of the rib is 2a)~, the inner rib height is 2bA and the etched depth of the rib is 2b(1 - r)A. Here A is the free space wavelength of light and r is the fractional height of side regions compared to the rib-center. The switch was fabricated on a p-type Si substrate. A lightly p-doped SiGe (~ 4% Ge) was grown on a 59-nm p-type Si buffer. The rib waveguide was formed by reactive ion etching. The n + injection region and the p+ collector were formed by phosphorus and boron ion implantation respectively. The chip was mounted on a copper heat sink to maintain the temperature constant during the measurements. 1.3- or 1.5-#m light from InGaAsP laser diodes was coupled into the input port 1 of the waveguide and light from the waveguide rib was collected by a lens and measured by an infrared image converter tube or an optical power meter and displayed on a video monitor. At zero injection current only port 4 shows the output signal. As the injection current increases to 85 mA for 1.3
240
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
2a~ (a)
no (b) f - ~ ~ ~ ~ . ~
In
-r)k
Si(100) substrate
Figure 7.31" (a) Schematic structure of a SiGe-Si intersectional rib optical waveguide switch with a bow tie electrode and (b) configuration of the waveguide (Li 2002 [10]). 92002 IEEE
#m light and 78 mA for 1.3 #m light the output light switches to port 3. This happens because when carriers are injected, the refractive index of SiGe layer decreases and total internal reflection takes place. The extinction ratio was larger than 38.5 dB and insertion loss was less than 1.70 dB. The refractive index can be changed and an optical waveguide can be constructed by applying stress to a localized stripe region in a semiconductor. The stress can be created by growing a stripe of different lattice constant on the semiconductor [193]. Rho et al. [78] have demonstrated the fabrication of such a waveguide by depositing a Si3N4 stressor stripe on a SiGe layer.
7.11.3
SiGe
QW
resonant-state
terahertz
laser
Currently quantum cascade lasers (QCLs) are based on III-V compound technology and operate at 10 #m. However it is difficult to build QCLs at longer wavelengths [6]. Attempts have also been made to fabricate QCL based on SiGe [84]. Altukhov et al. [6] have built a resonant-state laser (RSL) based on a SiGe quantum well. The laser structure, design and emission spectrum are shown in Fig. 7.32. The p-type Sil_xGex quantum wells were grown by MBE on a 5-mm thick n-type Si substrate. The SiGe layer was 5 doped to a concentration of 6 x 1011 cm -2. The Ge concentration in the well layers was 0.15. The layer thicknesses and sequence of layers are shown in Fig. 7.32(a). The two Si layers were 5-doped in the middle to a concentration of 4 x 1011 to 1012cm -2. The finished structure of the laser including contacts and emission of light is shown schematically in Fig. 7.32(b). Spectra of 4 samples were measured in the energy range 10-15.5 meV and at different applied voltages. Fig. 7.32(c) shows intense THz emission at 104 pm at 1000 V. The inset shows the spectrum at 1500 V. The modal structure of the emission was studied at 1000 V and 500 V. At the higher voltage structure was complex probably because several modes were excited. The authors suggested that it was laser emission from a population inversion in the QW due to the resonant states of boron.
7.11. P H O T O D E T E C T O R S , W A V E G UIDE S W I T C H A N D L A S E R
241
Figure 7.32: (a) Schematic view of the laser structure, (b) laser design and (c) spectrum of stimulated THz emission at 1000 V and in the inset at 1500 V (Altukhov 2001 [6]). 7.11.4
Miscellaneous
devices
Conventionally Thermoelectric (TE) cooling in solid-state is done by devices based on Bi2We3 coolers. They are used extensively in microelectronic and optoelectronic devices for cooling and for temperature stabilization [46]. Polycrystalline SiGe alloys are also used as thermoelectric materials. It has been shown recently that thermoelectric coolers fabricated using Si/Ge superlattices show very good performance. Interested readers may read papers by Koga et al. and by Fan et al. [127, 85, 45, 46] and earlier references given in these papers. Several other devices based on SiGe technology are discussed in the first edition of this book [1]. Notable among them are Bipolar Inversion Channel Field Effect Transistors (BICFETs) and Mixed Tunnelling Avalanche Transit Time (MITATT) diodes.
F E T s and o t h e r d e v i c e s 7.1
Ge channel M O S transistors
Considerable work has been done on SiGe heterostructure Field Effect Transistors (FETs). Both Metal Oxide Semiconductor FETs (MOSFETs) and Modulation Doped FETs (MODFETs) have been fabricated and studied by several groups. Ge MOS technology is of interest because the mobility of holes in Ge is larger than in most other semiconductors [1]. At low temperatures both electron and hole mobilities are high (at 77 K they both exceed 20,000 cm2/Vs). Ge MOS technology is also of interest for fabricating monolithic fiber-optic receivers [1]. Both p- and n-channel Ge MOSFETs have been fabricated. As distinguished from the strained layer devices discussed later in this chapter, the devices discussed in this section are fabricated using unstrained Ge. Formation of a high quality insulator layer is the key to the fabrication of high-speed metal-insulator-semiconductor devices. Early attempts to grow the insulator on a Ge substrate using thermally grown native oxide, deposited oxide and nitride were not very successful. In almost all cases large interface state densities and leakage currents were observed through the insulator. The difficulties arise because of the formation of volatile GeO when oxidation is performed at a temperature > 400~ The n-channel MOSFETs can be grown on (111) p type Ge substrate [1, and references given therein]. Since GeO2 is hygroscopic, an 800 ~ SiO2 protective layer is electron beam-evaporated on top of the GeO2 layer. Electrical measurements showed that the fast interface state density was ,~ 4 x 1011 cm-2/eV. Fixed oxide charge density was also large. Surface mobilities were of the order of 22% of bulk mobility. Improved n-channel Ge MOS devices were fabricated by Rosenberg et al. [394], using a self-aligned process. Nitrided native oxide was used as a gate insulator. An arsenic dose of ,,~ 1015 cm -2 was implanted at 50 keV to form the source and drain regions. The common-source characteristics of a 6 #m gate length device showed good saturation and turn-off. Junction leakage, parasitic surface conduction and contact resistance were negligible. An interface state 195
196
C H A P T E R 7. F E T S A N D OTHER DEVICES
density of < 5 x 101~ cm-2/eV at mid-gap and a fixed insulator charge of < 3 x 10 l~ cm -2 were estimated from electrical measurements. The measured channel mobility was 940 cm2/Vs. In a subsequent paper [395] n-channel mobility in excess of 1200 cm2/Vs was measured. P-channel MOSFETs using the same process [394] were also fabricated by the same group [395]. Measured lowfield mobility was 770 cm2/Vs in a 7 #m gate length device. The mid-gap interface state density was measured by comparing 1 MHz and 100 Hz C - V characteristics and was found to be below 5 x 10 l~ cm-2/eV.
7.2
Strained layer p-channel MOSFETs
The speed of Si CMOS (complementary metal-oxide-semiconductor) circuits is limited by the p-channel MOSFETs because of the relatively low mobility of the holes and because the current drive capability of the p-MOS transistor is inferior. In-plane mobility of holes in the SiGe layer grown on Si(100) increases due to strain. Strain removes the degeneracy between the heavy and the light hole bands and the spin-orbit band moves further down. This reduces the intervalley scattering of the holes. In buried SiGe strained layers I scattering of holes by the Si-SiO2 interface is practically absent. Absence of these scattering mechanisms increases further the hole mobility. Therefore SiGe strained layer p-channel MOSFETs are expected to have superior performance. Considerable work on the SiGe p-channel MOSFETs was done before 1993 [1, 397, 404]. Finding a suitable gate dielectric for the SiGe MOSFETs has been a problem. Extensive work has been done on the oxidation of SiGe alloys in an effort to obtain a good interface between SiGe strained layers and the oxide of the alloy (see the review by Jain and Balk [396]). Similar problems also arise with growth of oxides on Sil_x_yGexCy layers [86]. Attempts have also been made to grow new gate dielectrics on SiGe strained layers [1]. However, it has not been possible to grow or deposit a good-quality oxide or another dielectric directly on SiGe strained layers with acceptable quality of the interface. This difficulty is avoided by growing a Si cap layer (also known as buffer layer) on the active SiGe strained layer and growing or depositing SiO2 on the Si cap layer [1]. A schematic cross section of a SiGe MOSFET is shown in Fig. 7.1(a) and that of a thin-body MOSFET (discussed later) is shown in Fig. 7.1(b). The band diagram of the thin-body MOSFET is shown in Fig. 7.1(c). Usually the substrate has an n type doping concentration of about 5 x 1016 cm -3. The Si spacer layer, strained SiGe layer and Si cap layer are generally undoped. The background doping in these layers is n type and is about 5 • 1015 cm -3. The band bending and position of the Fermi level under an applied negative voltage are shown in Fig. 7.1(c). For low gate voltage, holes are formed in the SiGe layer, making it a p type conducting channel. There are no holes yet at the Si-SiO2 interface. For higher gate voltage (Fig. 7.1(c)) the holes are also formed at the Si-SiO2 interface, giving rise to a parasitic channel in the Si cap layer. The one-dimensional Poisson's equation has been solved numerically by many 1There is a Si cap between the gate oxide and active SiGe layer in p-channel MOSFETs.
7.2. S T R A I N E D L A Y E R P - C H A N N E L M O S F E T S
197
Figure 7.1: (a) Schematic cross section of a conventional SiGe MOSFET. (b) Cross section of a thin-body SiGe MOSFET. (c) Schematic band diagram of the thin-body MOSFET along the dashed line (based on Yeo 2002 [18]). workers [397, 404, 393, 40] to calculate threshold voltage and to obtain carrier densities in the two channels under different biasing conditions. Iniewski et al. [393] have given an approximate analytical solution of the equation. They have also calculated the short channel effects on the performance of the SiGe strained layer MOSFETs. The calculated charge densities QSiGe [18] in the Sil-xGex (x = 0.3) channel and Qsi in the Si channel of a MOSFET are shown in Fig. 7.2. These results are similar to those obtained by Iniewski et al. [393]. More recently Palmer et al. [40] have investigated in detail the characteristics of p-channel MOSFETs fabricated with a thin Si capping layer. Two different n-dopings were used in the substrate to investigate the effects of punch-through and drain induced barrier lowering. In batch A the doping was 2 • 1017 cm-3 boron and in batch B it was 5 • 1015 cm -3. The active layer was a Si0.64Ge0.36 strained layer. A range of thicknesses of the Si capping layer were used. The mobility versus sheet carrier density for two values of substrate dopings and for several values of Si layer thickness are shown in Fig. 7.3. The point at which parasitic conduction in the Si channel sets in is shown by the plus sign. It is seen from Fig. 7.3(a) that the parasitic conduction sets in at lower sheet carrier densities (and hence at lower gate voltages) for smaller values of Si layer thickness. Comparison of Fig. 7.3(a) and Fig. 7.3(b) shows that substrate doping does not have a significant effect on the onset of parasitic conduction. Iniewski et al. [393] studied the effect of changing the design parameters on the performance of the MOSFETs. In any one calculation, only one parameter was changed; others were kept unchanged. The main results obtained by Iniewski et al. [393] can be summarized as follows: 1. As the Ge concentration x increases, VTH decreases and VTS increases. Therefore the gate voltage "window" VTH- VTS for which parasitic conduction is negligible increases with Ge concentration.
198
C H A P T E R 7. F E T S A N D OTHER DEVICES 9
!
-
!
i
9
|
9
!
9
!
9
l
9
m
10~3 .... ~
"gl~
//
-
lO,i ,, / S
100.0
9
t
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Gate Voltage V6 (V) Figure 7.2: The integrated charge densities QsiGe and Qsi in the SiGe channel and parasitic Si channel (Yeo 2002 [18]). 92002 IEEE
35O
(a)
~p4nm)
300
W02 (Tcap~Jnm)
"~ 250 m,t ot
2OO
H
. .~. .~. . . . ~, . 2
1/ _(Tea~p-2'u_m.)
150
=2. 10o 5O
W06 (Si epiUmxy)
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WI0 (Tcsp~mm)
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"- 2oo M
lso 190
W12 (Sl non-ep#axlal eomtroQ
50 0
2
4
6
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10
N s (1012 cm4)
Figure 7.3: (a) Batch (A), effective mobility vs carrier sheet density for devices with a 2 • 1017 cm -3 substrate doping punch-through stopper. (b) Batch (B), same as for batch (A) but without a punch-through stopper. The observed onset of conduction at the SiO2/Si interface is marked by a cross (+) in both cases (Palmer 2001 [40]).
7.2. S T R A I N E D L A Y E R P - C H A N N E L M O S F E T S @
199
The effect of increasing Si cap thickness is just the opposite. As the cap thickness increases, VTS decreases and VTH increases. Therefore small cap layer thicknesses are desirable for obtaining large values of the gate voltage window. If the thickness of the cap layer is very small, remote scattering of the channel holes by the Si-SiO2 interface becomes significant and adversely affects the performance of the device. It is therefore desirable to avoid very thin cap layers and to use a large value of Ge concentration to obtain a good value of the gate voltage window.
3. Both threshold voltages increase with gate oxide thickness and substrate doping concentrations. The relative increase of the two voltages is such that the gate voltage window increases with gate oxide thickness but decreases slowly with substrate doping concentration. 4. The threshold voltages are not very sensitive to the thicknesses of the SiGe strained layer and Si spacer layer below the strained layer. .
The effect of grading Ge (maximum concentration being close to the Si cap) was also studied. It was found that the threshold voltage depended mainly on the value of Ge concentration at the maximum; the grading has only a second-order effect. The large concentration of Ge is therefore needed only close to the Si cap; Ge concentration in the rest of the strained layer can be reduced, making the critical thickness of the layer larger and increasing the stability of the device. In the SiGe MOSFET fabricated by Verdonckt-Vandebroek et al. [404], the authors used graded Ge concentration in the strained layer and obtained good results.
As a result of these calculations, Iniewski et al. [393] concluded that the approximate values of the design parameters for optimum performance of a SiGe MOSFET are: n type doping in the substrate in the range 10 lr cm -3, undoped Si spacer and linearly graded (40-0% Ge) SiGe layers, each of 10 nm thickness, undoped 5 nm thick Si cap layer and 5 to 10 nm thick gate oxide. Subbanna et al. [397] used UHV/CVD to grow SiGe strained layers. No spacer layer was used below the SiGe layer. Gate oxides (7 nm and 10 nm thick) were grown either thermally or deposited using Plasma-Enhanced Chemical Vapour Deposition (PECVD). MOSFETs with two Ge concentrations, x = 0.1 and 0.2 were fabricated. No channel doping was used to adjust the threshold voltage. Nominal channel lengths were between 0.8 and 10 #m. The devices showed a sharp turn-off. The subthreshold slope was insensitive to the drain voltage; it varied from 175 to 200 mV/decade for values of drain voltage VDS from --0.3 to --3.3 V. Values of transconductance gm and threshold voltage VT for 10 nm thermal oxide and for x - 0.2 are shown in Table 7.1 along with the performance characteristics of SiGe MOSFETs fabricated by other groups. The results for devices with PECVD oxide were similar. The devices with smaller oxide thickness showed smaller (numerical) values of threshold voltage and larger values of transconductance. Values of mobilities were not extracted in these experiments. Similar devices were fabricated by Garone et al. [398]. SiGe
CHAPTER 7. FETS AND OTHER DEVICES
200
Table 7.1: Observed characteristics of SiGe strained layer p- and n-channel M O S F E T s . Mobility p is given in cm2/Vs and saturated transconductance gin, in m S / m m . The symbol VT is the threshold voltage (in V) and T is temperature (in K) at which mobility # and transconductance are measured. The symbols dl to d4 (in nm) indicate the thicknesses of the Si spacer layer, SiGe strained layer, Si cap layer and oxide layer. Any value of a parameter or characteristic not quoted in the original paper is indicated by a dash. Ge concentration x -- 0 indicates Si control MOSFET. p- Channel M O S F E T s
dl
d2
d3
d4
x
VT
#/T
gm/T
-
7
10 10
0.2 0
-2.0
-
3s/300 22/300
10.5
12.5 12.5
0.3 0
-1.1 -2.0
780/90 290/90
[398] [398]
7 -
5 5
0.2 0
-
155/300 122/300
[399] [399]
7 -
10 10
0.5 0
-1.3 -1.8
1500/77 560/77
[4001 [400]
12-30
7 7
~7 ~ 7
0.2 0
-0.22 -0.22
150/300 90/300
20
5
7
**
**
980/82
-
-
10
15
-
-
100
7
-
-
5
167/300 139/300
Ref. [3971 [397]
[405]* [4051" [404]
n-Channel M O S F E T s
vertical transistor
0.16 0
0.57 0.70
** **
-
0.15
-
***
45/300
-
**** **** *****
70/77 800/77 700/300 300/300
[403] [403] [65]
MODFETs p n n p
MODFETs MODFETs MODFETs MODFETs
strained SiGeC strained Si strained Si -
[161] [71] [35] [71]
*Values of VT and gm are for short channel (0.25#m) M O S F E T s (see text).
**See [1]. ***Mobility increased due to Ge and strain ****See Fig. 5 on p a2a of Ref. [71] *****See Fig. 10 on p 326 of Ref. [71]
7.2.
STRAINED
LAYER P-CHANNEL
MOSFETS
201
layers were grown by Rapid Thermal Chemical Vapour Deposition (RTCVD). Samples were grown with three Ge concentrations, x - 0.2, 0.3 and 0.4. The SiGe layer was doped n type to 1 x 1016 cm -3. Gate oxide was 12.5 nm and was grown by PECVD. Nayak et al. [399] fabricated strained layer MOSFETs using MBE. The highest Ge concentration (x - 0.5) has been used by Goto et al. [400]. The design parameters of selected MOSFETs and their characteristics observed by different authors are compared in Table 7.1. Submicron channel length SiGe MOSFETs have been fabricated by Kesan et al. [405] using a Si CMOS compatible process. Si epilayers, SiGe epilayers and oxide layers were grown by the same methods as those used by Subbanna et al. [397]. The values of Ge concentration were in the range 0 to 0.25 and the strained layers were 12.5 to 30 nm thick. The thickness of gate oxide was 7 nm. Characteristics were measured at 82 K and 300 K. The current drive capability of the SiGe devices was significantly better than that of the Si control devices. At 82 K, the subthreshold slope of the SiGe device (x = 0.2) is 40 mV/decade compared to 30 mV/decade for the Si control device. Transconductance values for a Sil_~Ge~ device with x - 0.2 and for a Si control device are shown in Table 7.1. Compared to the 300 K values given in the table, at 82 K the transconductance values (also for the short-channel devices, effective gate length = 0.25 #m) were 201 mS/mm and 160 mS/mm. For long-channel devices (channel length 1.85 #m) the threshold voltage at 300 K was -0.35 V for the SiGe device and -0.45 V for the Si control device. These are considerably larger than those given in the table for the short-channel devices. The decrease of the threshold voltage on decreasing the channel length is due to the short-channel effects and is expected theoretically [393]. The 82 K mobility for long-channel devices is 400 cm2/Vs for the SiGe device and 250 cm2/Vs for the Si control device. Mobility values at 300 K are shown in Table 7.1. Verdonckt-Vandebroek et al. [404] used a graded SiGe layer; x varied from 0.25 at the upper end near the Si cap to 0.15 at the lower end near the spacer. The channel layer was 20 nm thick and doped n type (3 x 1017 cm-3). The thickness of the spacer and the cap were 5 nm each. A heavily boron doped 5 nm Si layer was used below the spacer to adjust the threshold voltage and prevent carrier freeze-out at low temperatures. The values of room temperature threshold voltage varied between -0.1 to -1.1 V, corresponding to the integrated boron dose of 2.3 x 1012 cm -2 to 1.4 x 1012 cm -2. The subthreshold slope was 87 mV/decade at 300 K and decreased to 31 mV/decade at 82 K. The 82 K mobility was 980 cm2/Vs (see Table 7.1). Although a Si control MOSFET was not fabricated for comparison, this value of mobility is considerably higher than the value reported in the literature for Si MOSFETs [404]. It is seen from Table 7.1 that in all cases the threshold voltages are lower and mobilities and transconductance values are higher in the SiGe device than those obtained with Si control devices. Among the results cited in Table 7.1, highest mobilities were obtained by Goto et al. [400] who used the largest Ge concentration. Nayak et al. [401] studied SiGe MOSFETs fabricated on a SIMOX substrate. In these SOI devices, vertical field and band bending are smaller; hence parasitic
202
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
conduction in the Si channel occurs at higher gate voltages. The SiGe SOI devices showed 90% improvement in the mobility over the Si control devices. They also showed considerable improvement in the transconductance and saturation current drive. More recently Nayak et al. [402] have fabricated a MOSFET in an active Si layer channel (as distinguished from SiGe layer channel) under tensile strain. A thick relaxed Si0.75Ge0.25 was first grown on a Si substrate. The active Si layer was grown on this buffer. In-plane hole mobility in the Si layer is expected to increase due to tensile strain. At higher magnitude of gate bias, the channel mobility of the strained Si p-MOSFET was 50% higher than that of a control Si p-MOSFET processed under identical conditions. Most work has been done on the p-channel heterostructure MOSFETs because the speed of the present CMOS circuits is limited by the poor performance of the p channel Si MOSFETs. Recently Yeo et al. [91] have fabricated short channel p- and n-MOSFETs with 24% Ge in the channel. The drive current increased by up to 25% down to channel length to 9.1 #m. The drive current of n-channel MOSFETs also increased up to channel length of 0.4 #m.
7.3 7.3.1
Strained layer n-channel MOSFETs Si quantum well channel with tensile strain
SiGe n-channel MOSFETs have been fabricated by Selvakumar et al. [403]. In these MOSFETs, the SiGe channel region was created by implanting a dose of 6 • 1016 cm -2 of Ge + at an energy of 80 keV. This resulted in the formation of a channel with a Ge concentration x = 0.16. A control Si MOSFET was fabricated using identical processing steps. The nominal channel length of both devices was 7 #m. The measured threshold voltage VT for the SiGe devices was 0.57 V, as compared to the value 0.70 V for the control device (see Table 7.1). At any given effective gate voltage V c - VT, the drain current for the SiGe device was considerably larger. Electron mobility #~ in the channel could not be extracted from these measurements because exact values of oxide capacitance Co~ and effective channel length L were not determined. The value of Co~#~W(Vc VT) VD/L determined from the slopes of drain current versus drain voltage plots was higher for the SiGe devices. If it is assumed that the effective channel length is the same in the two cases, electron mobility comes out to be larger in the SiGe devices. From theoretical considerations, the in-plane mobility of electrons in the strained SiGe layers should be smaller. Recently Yeo et al. [91] have fabricated both n- and p MOSFETs with a 10 nm Si0.~6Ge0.24 channel grown on Si substrate. The measured mobilities of holes and electrons in the two devices are shown in Fig. 7.4. As expected the electron mobility in the compressed SiGe channel is smaller, a result different from that obtained in Ref. [403]. However the drive current in both the p- and n-MOSFETs was higher in the strained layer devices. To take advantage of the increase in electron mobility by tensile strain,
203
7.3. S T R A I N E D L A Y E R N - C H A N N E L M O S F E T S 200
"'1
180
....
i ....
i ....
t'"
200 . . . . I . . . . 180
o SiGe channel 9Si channel
160
~"
160
140_
~E
140
"~
120 -
=
100
Universal mobility model
~t ~ 120 =
100 E o
80
o
60
_
1
-
~
40 _
=E
80
E
60
~
20 _
o~ 0.0
~r 0.5
~ _
1.0
1.5
2.0
I .... I .... I'" o SiGe channel 9Si channel
Universal mobility model
40
20
-=
2.5
o
0.0
0.5
1.0
1.5
2.0
2.5
Effective E-field Eelf (MV/cm)
Effective E-field Eeff (MV/cm)
(a)
(b)
3.0 ~ r
Q
Figure 7.4: (a) Hole mobility and (b) electron mobility from long channel devices. The universal mobility curves [191,238] are also shown (Yeo 2000 [91]). Welser et al. [239] designed and fabricated n-MOSFETs in tensile strained Si layers grown on relaxed graded SiGe buffer layers. Ge concentration in the top layer was 30%. Two designs, one with surface channel and the other with a buried channel were implemented. The buried channel device had a SiGe layer on top of the strained Si layer. A sacrificial Si layer was grown to form the gate oxide. The surface channel device showed 80% enhancement of electron mobility over that of the control Si device. Similar enhancement was found in transconductance. We have already discussed the work of Hbck et al. [101] on both n and pMOSFETs in chapter 5. The mobility in the strained p-channel increased and became comparable to the electron mobility in conventional Si n-channels. 7.3.2
Vertical
SiGe
n-MOS
transistors
In a vertical transistor the carriers move in the out-of-plane direction and mobilities of both electrons and holes are increased in the compressive strain. It is not necessary to fabricate tensile strained Si channel on relaxed SiGe layers to obtain the enhancement in electron mobility due to strain. Very short channel transistors can be obtained without the need of advanced lithographic technology. In view of these advantages both p-type [166] and n-type [65] vertical MOS transistors have been demonstrated. The structure of the n-type transistor is shown in Fig. 7.5. The SiGe channel is formed by Ge implantation after the oxide growth so that no Si cap is required during oxidation. The Ge concentration in the channel is graded, the maximum being x - 0.15, 1500/k
204
CHAPTER 7. FETS AND OTHER DEVICES
Figure 7.5: Cross section of the graded SiGe vertical n-channel MOSFET [65].
below the surface. Boron was implanted to a concentration of 8 • 101~ cm -3 in the channel. Identical control Si devices were also fabricated. The subthreshold characteristics of the SiGe and control Si devices are shown in Fig. 7.6(a). The output characteristics of the devices are shown in Fig. 7.6(b). The on-off characteristics of both devices are quite good. SiGe devices have a higher drive current. SiGe devices also have a higher off-state current. Due to the smaller bandgap of the channel, the effect of drain induced barrier lowering (DIBL) is larger in the SiGe devices. The threshold voltage VT and subthreshold swing (S) was large for both devices. This is due to the thick gate oxide used in the structure and unoptimized channel doping. For drain-source voltage VDS equal to V a - VT the drive current for the SiGe device is 50% higher than that of the Si control device due to enhancement of the electron mobility in the out of plane direction. However the enhancement is not as large as for the holes [65]. The actual electron mobility could not be extracted because a channel of only one single length was used and because source and drain resistances were not known accurately. Values of transconductance for both devices were determined from linear and saturation regimes. The linear peak transconductance of the SiGe device was 0.45 mS/mm and that of the Si device it was 0.3 mS/mm. As the Ge content and the strain increase, the separation between the two sets of valleys increases. Population of electrons in the lower valleys increases and intervalley scattering is reduced. Therefore in the out of plane direction the mobility of both electrons and holes increases as the Ge content in the alloy increases. However alloy scattering also increases with increase of Ge concentration. Therefore there should be an optimum Ge content for which the
205
7.3. S T R A I N E D L A Y E R N - C H A N N E L M O S F E T S 10"z 10" ~" I0 "6 ~
~_1 W~-:ZOOp~O.2lua
-
10-so
10"u 0.0
2.0
4.0
6.0
8.0
V c (V) (a) 3.5 ....... 3
, ....
~ ....
, ....
Vo-VT=O,O.5,1,1.5,2
zs
, ....
V
t
......
.--
"]
.-"'" ...............
~ s l
,.pl.S 1 0.5 0
0.0
'
'
'
0.5
'
'
*
.
1.0
.
.
.
.
1.S
.
.
.
'
2.0
'
2.5
voo0 (b)
Figure 7.6: (a) Subthreshold characteristics and (b) output characteristics of the graded SiGe and Si channel vertical transistors (Chen 2001 [65]). Values of Ira - VT (Ira is the gate voltage) are shown in the figure. lxl011
. , ]
i
,
o
_ lx106 - 5xlO 5
lxlO10
1•176 5• 4
lx109 ..~ lxlO 8
]
lxlO 7 @
lx104
5xiO3
c:
lxlo6 lxlO 5 ~ 0
lx103 0.5
1.0
1.5
2.0
Thickness of ramp to 30% Ge (ram)
Figure 7.7: Effect of grading rate of Ge-content in the buffer on the density of threading dislocations and on the electron mobility measured at 0.4 K. The dotted line is an extrapolation showing that mobility is not limited by the threading dislocations once their density is below 1 x l0 s c m - 2 [215].
206
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
mobility is maximum [65].
7.4 7.4.1
M o d u l a t i o n doped Field Effect Transistors Enhanced
mobility
in 2D gas
The 2-Dimensional (2D) character of electron or hole gas was predicted more than 40 years ago and observed experimentally about 25 years ago at the interface in Si MOSFETs [1, and references given therein]. Since the valence band-edge in Sil_~Gex strained layers is always higher than in Si (lower in energy for holes), a thin layer of strained SiGe sandwiched between two Si layers offers the possibility of confining the holes and forming a 2D hole gas. Similarly, if the strain is tensile, a lower energy well for electrons is obtained in a Si quantum well in which a 2D electron gas can be formed. The carriers are supplied by neighbouring layers which are doped p or n type and the structures are known as modulation doped structures. The devices fabricated using modulation doped strained layers are known as Modulation doped Field Effect Transistors (MODFETs). In MODFETs the dopants are not present in the active layer and the impurity scattering is absent which results in additional enhancement of the mobilities. Miyao et al. [244] have obtained very high mobilities in the 2D hole gas. The structures were fabricated on Ge(100) substrate followed by a Sil_~Ge~ buffer layer. This was followed by a 20 nm Ge channel layer and a 30 nm Si0.sGe0.5 layer. A Ga doping spike was introduced in the middle of the top Si0.5Ge0.5 layer. The gate oxide was made of CVD SiO2 (50 nm at 400~ Hole mobilities of 9000 cm2V-ls-1 [243] and 10,000 cm2V-ls -1 [244] were reported in t h e e structures. Recently K~inel et al. [7] have measured mobilities in modulation doped strained Ge channels grown on a Si0.4Ge0.6 layer. The Si0.4Ge0.3 layer was grown on a Si0.3Ge0.~ buffer layer and the whole structure was grown on a Si substrate. Hole mobilities up to 3000 cm2/Vs at room temperature and 87000 cm2/Vs liquid He temperature were observed. Extensive work has been done on the growth of buffers with a reduced concentration of threading dislocations. A detailed description of the methods of growing graded layers is given in chapter 2. The concentration of threading dislocations depends, among other factors, on the grading rate of Ge concentration. The results of an experiment on the effect of the grading rate of Ge are shown in Fig. 7.7. This figure shows that the concentration of dislocations can be reduced from 1 x 1011 cm -2 down to 1 x 105 cm -2 by changing the grading rate of Ge. The mobility of electrons in the Si epilayers grown on the buffer is also shown. Electron mobility exceeding 3 x 105 cm2/Vs were obtained in the Si layers under tension. The dotted line shows that if the density of threading dislocations is less than 1 x l0 s cm -2, other factors (e.g. phonons and other defects) start limiting the mobility. Selected mobilities reported in the 2D carrier gas are summarized in Table 7.2. The large values of the mobilities shown in Table 7.2 make it possible for the SiGe based transistors to work at high frequencies.
7.4. M O D U L A T I O N D O P E D FIELD E F F E C T T R A N S I S T O R S
207
Table 7.2: Best mobilities of 2D electron and hole gases in strained Si or SiGe quantum wells. Type Electron Electron Electron Electron Hole gas Hole gas Hole gas
/ Ti/Pt/Au contact Source I
T-gate Pt/Au
gas gas gas gas
Temp. (K) 300 77 < 2 0.4 300 77 < 10 K
cmU/Vs 2830 18000 180000 300000 1050 3500 18000
Ti/Au T-gate
/
/ I
5 nm Si-cap 10 nm Sio.6Geo.4
, , Drain' j
9 nm Si-channel I 3nm Si0 6Ge04spacer nm Sio6Geo4Sb, 8*101Scm3~'graded buffer SiGen---.n 4
/
Pt-contact
4 nm Si cap 7 nm Si0 4Geo.6
f 3rim si0C;eo.,.sb -Sio,6Geo.4spacer iI
(a)
Reference [241] [241] [98] [215] [242] [242] [98]
(b)
9 nm Ge channel
graded buffer SiGeo . o 6
Figure 7.8: Typical layer structure of (a) n-MODFET [392] and (b) p-MODFET [131] (quoted by g5nig 2000 [71]). 7.4.2
Design of MODFETs
Early n-MODFETs were fabricated by Ds et al. [392] by MBE. The substrate was p - with a resistivity p = 1000 flcm. The layer structure is shown in Fig. 7.8(a). The buffer layer is graded from 0% to 40% Ge. A tensile strained 9 nm Si channel is embedded in undoped Si0.6Ge0.4 layers which separate the channel from the doped carrier supply layers. Due to large tensile strain a high conduction band offset is achieved. Carrier densities up to n8 = 7 • 1012 cm -2 and mobilities up to 28000 cm2/Vs were obtained. The structure of a compressively strained Ge channel p-MODFET is shown in Fig. 7.8(b) [131]. The layer thicknesses, doping concentrations and Ge contents are clearly shown. To summarize a n-type MODFET consists of tensile strained Si layer with n-doping in the neighbouring layers. A p-type MODFET consists of compressively strained SiGe layer with p-doping in the neighbouring layers. The technology of fabri-
CHAPTER 7. FETS AND OTHER DEVICES
208 n-MODFETs or HFET 1000
n, p-SiGe
HFET Si_:__l.mu O---~ .~-,~,-~ I T! DIBM n-rirt~i 9IBM
N
n_S~im ' ~
~oo
p-MODFETs or HFET
.
fmax "DC
=
1000 : n,
9
p-~T
~,
~
100 .:"
10
HFET Simul.----
p-SiGe
IBM fmax 9
fT
0
(b)
"~o l O t
0 ~
-"n-Si--- Toshiba, IBM, et al. 1
,
0.05
llll
0.1
, , , , , ,,,I 0.2 0.5 1.0 Gate Length LG (gm)
p-Si--- IBM, et al. 1
i
0.05
II
'I
0.1
0'2. ' , , , , , , I 0.5 1.0 Gate Length LG (~m)
Figure 7.9: Review of frequency data reported (a) for n-MODFETs (also known as HFETs) and (b) for p-MODFETs (S6nig 2000 [71]). Frequencies in p-Si MOSFETs are considerable lower than in n-MOSFETs. Simulated frequencies in both types of MODFETs are similar. Experimental data also show much larger improvement in the p-devices. cating the MODFETs has been reviewed by KSnig [71]. 7.4.3
AC and DC performance
of MODFETs
The very high mobility of electrons in n-MODFETs makes it possible to operate the transistor at low power and at supply voltages of about 1 V and zero gate bias. By using recessed gates, the gate to channel distance can be varied and the operation mode can be adjusted. The threshold voltages can be varied between -1.6 V and +0.2 V. The fT and fmax data obtained with n-MODFETs are plotted in Fig. 7.9(a) and for p-MOSFETs in Fig. 7.9(b). The frequencies depend on gate length. Data for optimized devices, particularly for LG < 0.25 #m are not yet available. The devices are also not optimized for low parasitics and optimum dopings. The data points lie above those for Si MOSFETs even in the unoptimized devices. Experimental values of transconductance of both n- and p-MODFETs are shown in Fig. 7.10. All devices were fabricated with Schottky gates. The drain current can be made zero by applying negative bias to the n-type devices (at zero bias the channel is not depleted). The operation mode of the devices can be changed by using recessed gates with different depths. Therefore both types of devices can be made on the same chip. MODFETs show good transconductance over a wide range of gate-bias values. The saturation current values obtained for n-devices are 230-320 mA/mm for depletion mode and about 200 mA/mm for enhancement mode n-MODFETs. The results for p-MODFETs shown in Fig. 7.10(b) are also very promising. Transconductance of 314 mS/ram at LG =
7.4. MODULATION DOPED FIELD EFFECT TRANSISTORS n-MODFETs at 77 K and at 300 K 800 . . . . . . . . . . ~ 7 0 0 t 1 - ..... 300K77K] (a) ' ::": ~= 600'... ........ : 9 3500r "" il
........
;
/ t--,
/ """
p-MODFETs at 300 K 1000
_ .
. -
-0.5 Gate
o Sio.aGeo.r pMOS (IX;) 9 Sio.aGeo.rpMOD (IBM) O Ge pMOD (DC), do<:: = 19 nm r Ge, MOD (IBM). doc 10 nm
Co)
- i~ g '";
i
o
,00
,.'* - .0
/DC 9
209
. . : Lc,-~.4, 0.15 ~tm 0.0 0.5 1.( Bias VG (V)
Jl 0,1
1
1
.~
i
i
J i J]
L 1
Gate Length LG [pm]
Figure 7.10: DC transfer characteristics of depletion and enhancement mode (a) n-SiGe MODFETs and (b) p-MODFETs (compiled by KSnig 2000 [71]). Note that the transconductance is plotted as a function of gate-bias for n-type devices but as a function of gate-length for the p-type devices. For n-MODFETs data at 77 K are also shown. The abbreviation DC is used for the company name Daimler-Chrysler. 0.1 tzm and 212 m S / m m at Lc = 0.8 #m is obtained. The performance characteristics of MODFETs are compared with those of HBTs in Table 7.3 and Fig. 7.11. Table 7.3 shows that the values of transconductance, fT and fm~x have shown large improvements over the 1994 values quoted in Ref. [1].
7.4.4
N o i s e in n - M O D F E T s
Several groups have investigated noise characteristics of SiGe MODFETs [35, 94, 226, 164]. Simulations show that the noise characteristics are better than those of the devices based on III-V semiconductors. Recently Enciso et al. [35] have measured the noise performance of strained Si/Si0.58Ge0.42 n-MODFETs. The structure was grown by MBE on a 1000 f~cm p-type Si substrate. There was a relaxed SiGe buffer with graded Ge concentration from 0 to 43%. The active layer was a 9 nm strained Si layer sandwiched between two 3 nm Si0.58Ge0.42 layers and two Sb-doped SiGe carrier supply layers. The noise parameters were determined by measuring noise figure variation with frequency. The measurements were made for two impedance sources, a 50 f~ and an offset short line presented at the input transistor. The maximum gm of the devices was 700 m S / m m which is a record value for SiGe based FETs. The frequency behaviour was also good, maximum values of fT and fmax were 49 GHz and 70 GHz respectively. The values of gate source and drain resistances were extracted: RG -- 65~2mm, Rs - 1.8f~mm, and RD = 1.85f~mm. The measured noise characteristics of the 0.13 #m gate MODFETs are shown in Fig. 7.12. Figs. 7.12(a), and (b) show NFmin, Ga~8, and Rn as a function of I n s at 2.5 GHz. In the initial stages NFmin decreases as I n s increases because
210
CHAPTER 7. FETS AND OTHER DEVICES
Table 7.3: Performance of transistors fabricated using SiGe strained layers (see Figs. 7.9(a)and 7.9(5)). Device HBT n-MODFETs p-MODFETs
*LG ---- 0 . 8
State of the /3(77K) fT GHz 13000 210 100 80
/3(RT) 5000
art
fmax
Fb
gm(RW) gm(77K)
GHz 180 120 100
dB 0.2 -
mS/mm
mS/mm
388 212"
670 300
#m
Potential Device
ft, fmax
HBT n-MODFETs p-MODFETs
GHz 225 ~ 300 > 200
T Delay ps <4 3-6 5-10
gm (RT) mS/mm
m
> 800 > 600
300 measured ----
N
HFET t s
extrapolated
200,
Si MOS r
100 ~m
1985
1990
1995 Years
m
m
Si BJT mmm
mm
m
m
2000
Figure 7.11: Progress in frequency of SiGe HBTs, standard Si BJTs, MOSFETs and SiGe HFETs (MODFETs) is shown. Data up to 1995 was compiled in Ref. [216]. We have updated the data for HBTs and HFETs up to 2002. Expected increase in the frequency beyond 2002 is also shown.
7.4. MODULATION DOPED FIELD EFFECT TRANSISTORS ~ 6O
-
(a)
'
'
'
(c)
211
'
5o ~
I 2:
~z
40
O
z 30 ~- 5
1: J.
Z
! ,,,!
I I
4
- 1 5 ~*>
( d ) ~
u~ 3 O
=
-10~
2
-5 0
t
!
J
50 100 150 200 Drain current (mA/mm)
0
i
5 10 15 Frequency (GHz)
~
0
20
Figure 7.12: (a) Equivalent noise resistance R~, minimum noise figure NFmin, and available gain Ga~ plotted against drain current n s for 0.13 #m n-Si/SiGe MODFET at VDS = 1.25 V and 2.5 GHz. (c) and (d) same as (a) and (b) plotted against frequency at the same VDS and at I n s -- 70.7 mA/mm (Enciso 2001 [35]). gm increases faster than the channel noise current. Also id is screened more efficiently by the associated power gain. At large I n s gm saturates and becomes nearly constant. After obtaining a shallow minimum, NFmin starts increasing in this region. Now the associated gain Ga** decreases and noise resistance increases. Figs. 7.12(c), and (d) show NFmin, Ga,~, and Rn as a function of frequency. At 2.5 GHz the characteristics are: NFmi~ = 0.3 dB, G~,~ = 19 dB and Rn - 41 f~. These results are comparable to the noise characteristics of SiGe HBTs [35]. The good noise performance is due to collision free transport of electrons in tile strained Si channel. The results of Enciso et al. [35] show that the n-Si MODFETs have a good potential for application in mobile microwave communications.
7.4.5
Circuit performance of M O D F E T s
Due to their low power consumption, CMOS transistors are important building blocks in digital integrated circuits [214]. CMOS technology is very mature. Recently it has been shown that speed-power performance of CMOS can be significantly improved by using the MOS transistors fabricated using SiGe strained layers [214]. The design suggested in [214] is planar and avoids inversion of the Si layer at the oxide interface. The CMOS is fabricated on a relaxed Si0.rGe0.a buffer. It consists of a Si quantum well under tensile strain for the electron
C H A P T E R 7. F E T S AND OTHER DEVICES
212
100
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1000
Figure 7.13: Power delay product versus delay for Si/SiGe HCMOS and Si bulk CMOS. The corresponding drain bias values are indicated on the curves (Sadek 1996 [214]). 9 1996IEEE channel and a Sil_xGex compressed quantum well for the hole channel. Simulated performance of an 11-stage CMOS inverter ring oscillator is shown in Fig. 7.13. This figure shows the power-delay product as a function of average stage delay for the unloaded and loaded cases. The energy per switch decreases as V2D (VDDis the drain bias) but at the same time stage delay increases making the performance of the circuit poorer. Assuming that all the design parameters (device length, width, oxide thickness, series resistance, threshold voltage and interconnect and junction capacitances) have been optimized, the performance at a given voltage can be improved only by increasing the mobility of the carriers. It is here that SiGe quantum wells play a crucial role. It can be seen from Fig. 7.13 that the performance of the SiGe CMOS is superior in both the loaded and the unloaded cases. In the loaded cases the SiGe circuit can operate at 1.2 V retaining the same stage delay as the pure Si circuit operating at, 2.5 V. For a stage delay of 55 ps, the power-delay product in the SiGe CMOS improves by a factor of 4.6.
7.5
Strained-layer M O S F E T s on insulator
Gs et al. [12]have again emphasized the importance of tensile strain in Si channel for increasing the electron mobility. We have already discussed that tensile strain splits the 6-fold degenerate conduction band valley, a 2-fold degenerate state moves down and a 4-fold state moves up. The inplane effective mass of the electron decreases and intervalley scattering is suppressed resulting in considerable enhancement of the electron mobility. A spectacular velocity
7.5. S T R A I N E D - L A Y E R
MOSFETS ON INSULATOR
213
overshoot [12] is also predicted. In spite of these advantages bulk Si/SiGe subb100 nm CMOS technology still suffers some inherent limitations. Some of the inherent limitations can be overcome by using SOI technology. SOI devices are more radiation tolerant, short-channel effects van be more effectively controlled and have lower parasitic capacitance. By combining the strained channel with SOI technology (i.e. strained SOI technology) one can use advantages of both and remove some of the deficiencies they present when used separately. The mobility in strained SOI or strained SGOI are significantly larger than in SOI. Gs et al. [12]have investigated the electron transport in strained Si inversion layers by solving the Boltzmann transport equation and confirmed the above advantages. They have also found that enhancement of mobility depends on the thickness of both the SiGe layer on which strained Si layer is grown and on the thickness of the Si layer.
7.5.1
Strained-layer p-MOSFETs on insulator (strained SO1)
Silicon on insulator (SOI) MOSFETs are useful for sub-100 nm CMOS circuits. They have reduced parasitic source drain capacitance. The short channel effects can be suppressed and mobility can be increased by thinning the active semiconductor layer without increasing the dopant concentration [42]. The fluctuations in the threshold voltage are also reduced. Simple mesa isolation technology can be easily used in this technology. However hole mobility being small, the switching speed of the sub-100 nm devices is limited. The mobility can be increased and the advantages of SOI can be realized if strain is combined with SOI technology. Mizuno et al. [42, 21] have constructed SOI p-MOSFETs with a strained Si channel. The process flow and schematic structure of the MOSFET are shown in Fig. 7.14. Important steps in the process are the fabrication of relaxed SiGe layer on the buried-oxide layer produced by SIMOX (separation by implanted ox_Kygen) technology and growth of high quality strained Si layer on the relaxed SiGe film. A 5 nm gate-oxide was formed by thermal oxidation at 800~ [42, 21]. Source and drain regions were formed by implantation of 35 keV BF2 and annealing at 900~ for 30 min. TEM pictures showed that interfaces of the buried oxide were flat and there were no misfit dislocations in the strained Si layer. AFM pictures showed good surface morphology after SIMOX and also after growth of the strained Si layer. The Raman shift from the SiGe layer and from the strained Si layer showed that Ge content was 10%. The Ge content of the GeSi layer remained constant even after the high temperature SIMOX annealing because the buried oxide prevented diffusion of Ge towards the substrate. The MOSFET showed good FET characteristics. Hole mobility was higher than the universal mobility [191,238] of conventional MOSFETs. Transconductance of the strained layer MOSFETs was also higher than that of the control Si MOSFETs. However some amount of drain leakage was observed in the subthreshold region. Recently it has been demonstrated that relaxed SiGe layers can be grown on a insulator layer resulting in the SGOI (SiGe on insulator) technology. Mizuno
214
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
Figure 7.14: (a) Process steps for fabrication of strained-SOI substrate (I, II, and III) and MOSFET (IV and V). (b) Schematic cross section of strained SOI MOSFET (Mizuno 2001 [42]). 92001 IEEE
et al. [4] deposited a 300 nm strained Si0.9Ge0.1 layer directly on a Si substrate. The SIMOX process was then used to create an oxide layer between the Si substrate and strained SiGe layer. During this process the strained SiGe layer relaxes by a slip between the layer and the buried oxide. Since the Ge content is low and the thickness of the layer is small, annealing could be carried out at 1300~ to form the continuous buried layer. Finally the SiGe layer was thinned and its Ge content increased by low temperature annealing in Ar-O2 mixture. The relaxation now was 93%. Tezuka et al. [3] have used a somewhat different technology to produce small mesas of relaxed SiGe (without any dislocations) on silicon oxide. First thin pseudomorphic SiGe layers were deposited on SOI substrates. Circular mesas of SiGe and Si were produced by chemical dry etching. These mesas were oxidized in pure oxygen ambient at 1200~ and 1050~ Ge content in the SGOI layer and in Si layer increased as the Ge atoms were rejected from the growing Silicon oxide. The oxide layer blocked the diffusion of Ge out of the SiGe layer. The radius of the mesas varied between 0.2 and 5 #m. The mesas were relaxed and completely free from dislocations. This provides a good substrate for growing strained Si layers for n-MOSFETs. In their most recent paper [21] Mizuno et al. improved further the design of the MOSFET. They fabricated a double SiGe (second-Si0.s2Ge0.1s/firstSi0.93Ge0.07) relaxed structure which made it possible to introduce higher strain in the Si channel. The hole mobility increased by 30% over the universal mobility and 45% over the control Si MOSFET mobility. In SIMOX technology the structure is subjected to temperatures > 1300~ During this step misfit defects can be created in the SiGe or Si strained layers. Huang et al. [50] have used the wafer bonding and hydrogen induced transfer
7. 6. H I G H - K G A T E - I N S U L A T O R S
215
technique to prepare SiGe layers on insulator substrates. Strain relaxed SiGe layers (15% to 30% Ge) were grown by UHVCVD at 500-550~ The thickness of the SiGe layers was 1-2 #m. The degree of strain relaxation was > 90%. H + with a dose of 2.5-5 • 1016/cm 2 was implanted with an energy such that its peak was near the top portion (away from the network of misfit dislocations) of the SiGe layer. After the chemical mechanical polishing and cleaning process the substrate (known as a donor wafer [39]) was bonded to a Si wafer (known as a handle wafer) with 300 nm of thermally grown oxide. The structure was thermally treated in the temperature range 300-500~ to separate the two parts at the peak of the hydrogen concentration (this technique is known as the "smart cut" technique). A high quality strained Si layer was grown on the relaxed SiGe layer. Modulation doping was used to produce carriers in the strained channel. Electron mobility of more than 35000 cm2/Vs were obtained at low temperatures. Cheng et al. [39] have also used the wafer bonding technique to fabricate strained Si layer on insulator. They removed the donor wafer by the etch-back technique. Electron mobility larger than the universal mobility was observed.
7.5.2
Thin-body MOSFETs
A thin-body (i.e. with small thickness of the channel) MOSFET is essentially an extension of the fully depleted SOI MOSFET discussed in the previous subsection. Yeo et al. [18] have demonstrated a 50 nm thin-body SiGe strained layer MOSFET on insulator. 50 nm channel is the shortest channel length of any MOSFET reported so far. A schematic cross section of the thin-body MOSFET was shown in Fig. 7.1(b) and the band-structure was shown in Fig. 7.1(c). The carrier profile is also shown schematically in Fig. 7.1(c). In the thin channel the source to drain current is restricted to a path close to the gate and therefore control of the gate is better. Subsurface leakage currents are suppressed. Short channel effects are suppressed without the need to dope the channel heavily. Dopant impurities in the channel cause degradation of mobility and fluctuation of threshold voltage [18]. The thin-body MOSFET has a buried oxide wall below the channel. The Ge concentration in the channel was graded from 0 to 30% (bottom to top). A 4 nm Si cap provides a good interface. The simulated charge density in the SiGe channel and in the parasitic Si channel is shown in Fig. 7.2. Process steps have been described in detail by Yeo et al. [18] (see Fig. 8 of their paper). The output characteristics of the MOSFET are compared with that of the control Si channel MOSFET in Fig. Fig. 7.15. There is significant (up to 70%) improvement in the drive current due to both the strain in the channel and to the thin-body structure.
7.6
High-k gate-insulators
The SiO2 gate dielectric has to be made ultra-thin for sub-100 nm MOSFET devices. As the thickness is scaled to a few nano-meters, gate leakage current due
216
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
0.5 W/L = 5 . 0 ~ / 0 . 0 5 ~ n
~,, 0.4
- - - a - - SiGe-channel --o--
Si-channel
_~
"-,~0.3
0.2
0.1 0.~
90
-0.5 -1.0 Drain Voltage gns (V)
-1.5
Figure 7.15: Output characteristics of the SiGe channel and Si channel thinbody p-MOSFETs. The higher hole mobility in the SiGe channel results in a 70% improvement in the drain current at VDS = --1.5 V and V c s - V T H - - -1.2 V (Yeo 2002 [18]). 92002 IEEE
to direct tunnelling becomes a problem. This has provided the motivation for finding alternative high k gate insulators [28, 70, 16]. A1203 and HfO2 reduce the gate leakage current of Si MOSFETs by orders of magnitude. However these dielectrics cause instability of threshold voltage and degrade the mobility. These disadvantages can be overcome to some extent by using strain to increase the mobility [16]. Several other insulators with high-k have been investigated. Notable among them are Ta205, TiO2, Zr202, ZrSi~O~, and HfO2. Equivalent oxide thickness (EOT) with some of these materials is as small as 5 A. Recently efforts have been made to find new high k insulators [28, 70]. Rim et al. [16] have fabricated strained Si n-MOSFETs using Hf20 as the gate dielectric. A thin tensile strained Si layer was grown on a 1.5 #m relaxed Si0.8~Ge0.15 layer by UHVCVD. Control devices on CZ Si (with no strain in the Si channel) were fabricated for comparison. As compared to the CZ Si devices, the leakage current was reduced by a factor more than 1000 and hole mobility in the channel increased by 30%. Ngai et al. [28] have designed and fabricated SiGe strained layer p-MOSFETs using high-k ZrO2 as the gate insulator. ZrO2 was deposited by the dc magnetron reactive sputtering from a
7. 6. H I G H - K G A T E - I N S U L A T O R S
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Zr target in an Ar+O2 ambient. No Si capping layer was used between the active SiGe layer and the gate dielectric. The active layer consisted of an n-type 350 A UHVCVD grown Si0.s5Ge0.15 strained layer. The output characteristics of the transistor are shown in Fig. 7.16. Pal et al. [70] have investigated the properties of Gd203, Ga203(Gd203), Y203, and Ga203 deposited on boron (1-2 x 101~ cm -a) doped Si0.74Ge0.26 strained layers. Dielectric films were deposited by electron beam evaporation. The insulator films were characterized by energy dispersed x-ray analysis, secondary ion mass spectroscopy, and ellipsometry. The metal-insulator-semiconductor structures were characterised using current-voltage, capacitance-voltage and conductunce~voltage techniques to determine the resistivities, breakdown strength, fixed oxide charge and interface state densities. A summary of the properties of the oxides is given in Table 7.4. All the rare-earth oxides (except Ga203) show good dielectric properties. They passivate the SiGe surface. The passivating property was optimised and the interface state density was the lowest with Ga203(Gd203).
These experiments [16, 28, 70] show that strained layers used with high-k gate insulators show great promise.
218
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.4: A comparison of various electrical parameters of the gate insulators (annealed at 450~ investigated by Pal et al. (2001) [70]. Ga20 3 (Sl)
Ga203(Gd203)
Gd203(S3)
Y203($4)
Film thickness
1975
2088
2056
2063
Refractive index er p (D.cm) Eb (MV/cm) JL (A/cm2) Dit(eV-lcm2) Qox (cm2)
1.59
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7.7 7.7.1
10.0 1.6x1010 1.0 3.6X105 2.4x1012 6.0x1012
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13.6 1.0xl014 3.3 3.5x10"8 6.3x1011 6.4x1011
16.0 6.8x103 4.0 3"6x108 5.4x1011 8.8x1011
MOSFETs containing Sil_x_yGe Cy alloys Sil_yCy channel n - M O S F E T s
As discussed earlier, tensile strain is required to fabricate a quantum well for electrons in Si. The graded SiGe buffer layers required to construct such channels are expensive and time consuming. Moreover they introduce threading dislocations in the active layer. Rim et al. [162] avoided the graded layer buffers and obtained tensile strain by introducing C in the channel. They fabricated n-MOSFETs with a Sil_uCy channel. The conduction band offset was found to be proportional to tensile strain and is equal to ,-~ 166 meV for each one percent of strain (see Fig. 1 of Ref. [162]).The MOSFETs had good turn-on characteristics and good sub-threshold behaviour. At room temperature the electron mobility is comparable (slightly smaller) to the mobility obtained with CZ control transistors. At 77 K the mobility was considerably degraded. Strain induced enhancement in the mobility was not observed. Presumably carbon introduces charged defects. Coulomb scattering by the defects and alloy scattering offset the increase in the mobility due to strain. Degradation of mobility in C containing layers has also been reported by Osten and Gaworzewski [190] and by Duschl et al. [90].
7.7.2
SiGeC p-channel M O S F E T s
John et al. [130] have investigated the characteristics of SiGeC channel pMOSFETs. Three transistors with different compositions of the channel were fabricated, a Sio.8Geo.2 channel, a Si0.793Ge0.2C0.07 channel and a Si channel
7.8.
ULTRA-SHALLOW JUNCTIONS
219
control device. In each case the channel length was 10 #m. The layers were deposited by UHVCVD. The thickness of the Si cap layer was 50/~. The dc characteristics were measured at room temperature and at 77 K. Hole mobility was extracted from the measured I - V curves. The subthreshold slopes were 101, 90 and 75 mV/dec in the three devices. At low fields and room temperature the mobility in C containing devices was higher. At room temperature the peak mobilities was 190 cm2/Vs in the device containing C and 140 cm2/Vs in the SiGe device without C. The enhanced mobility in C containing devices was attributed to lower density of process induced defects. However at high fields and/or at 77 K the mobility degraded and became smaller than the mobility in the SiGe device without C. The mobility in the Si control device was lower than that in the SiGe device. It was also lower that the mobility in bulk Si. Devices with larger concentrations of C to compensate the strain completely also investigated. They showed significantly degraded performance. There are other applications of carbon in Si based devices. Heinemann et al. [114]have shown that by using a carbon doped buried layer, Latchup can be suppressed. We have already discussed application of carbon in SiGe HBT technology in chapter 6
7.8 7.8.1
Ultra-shallow junctions Series resistance
Currently many groups are working on developing the technology for formation of shallow junctions with low series resistance [80, 81, 97, 106]-[113]. The International Technology Roadmap for Semiconductors (ITRS) [144] imposes several constraints on dimensions and dopant profiles in sub-100 nm gate-length transistors [108]. The expected evolution of junction depths and extension lengths (the distance between the silicide and the channel) as a function of year of introduction is shown in Fig. 7.17. The CPU gate-lengths are also shown in the figure. If the lengths are scaled as shown in this figure, it becomes necessary to scale the implantation dose and dopant concentrations to keep the series resistance within the acceptable limit. The series resistance has three components: the contact resistance Re, extension resistance P8 ^~xtr ~r and link-up or tip resistance Rtnk. The three components are shown in Fig. 7.18. Gossmann et al. [108] have discussed at length the contact resistance and the link-up (tip) resistance in the future sub-100 nm devices. (The link-up resistance is the resistance between two points A and B: The point A is the point where the doping concentration begins to decreases below its solubility limit and doping induced carriers also begin to decrease; the point boron is the point where the channel can be considered to begin i.e. where the carriers supplied by the inversion exceed the doping induced carriers.) These two resistances impose severe limitations on the technology. Gossmann et al. [108] have suggested possible methods to circumvent the limitations. We do not discuss the contact resistance here. The link-up resistance can be reduced by making the doping profile fall steeply by epitaxial
220
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
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Figure 7.17: Junction depths and extension lengths as a function of technology node (bottom abscissa) and CPU gate-length (top abscissa). Also shown is the year of introduction [144, 108].
Figure 7.18" Schematic cross-section of a MOSFET. Three series resistance components, contact resistance Re , extension resistance t,~ .~=tr~ x t and link-up or tip resistance R~nk are shown [108].
221
7.8. U L T R A - S H A L L O W J U N C T I O N S
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Figure 7.19: Required boron implant energy for PMOS extension regions [108]. techniques. However this impacts the performance of the intrinsic device adversely due to spilling of carriers into the channel and increase of the leakage current. The optimal lateral steepness depends on many variables and has been discussed by Gossmann et al. [108]. For 5% voltage drop in both the extension regions, the sheet resistivity of the extension regions is given by [108],
pext _____0 . 0 5 VDD I/I/ s
2
1
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where IoN is the on-current (=0.75 m A / # m for NMOS and 0.35 m A / p m for PMOS), L~=t is the length of the extension, and W is the width of the device. Gossmann et al. [108] calculated the extension sheet resistance for different technology nodes. These calculations show that to keep the resistance within the limits imposed by Eq. (7.1) the implantation dose and peak dopant concentration should increase by a factor between 5 and 100 in sub-100 nm devices. Since we know the geometry, dose and peak concentration of the dopant, it is possible to calculate the required implant energy. The calculated implant energy is shown in Fig. 7.19. We see that ultra-low energy implants are necessary. Today's implanters are capable of implanting species at 0.1 keV [109]. However very low energy implants cause technological problems. Ion implantation causes sputtering of the surface atoms. First Si surface atoms are removed and the Si surface recedes. The high boron concentration
222
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Figure 7.20: Retained boron dose is plotted as a function of boron implant dose for two different implant energies [109]. 92000 IEEE region moves closer to the surface. Now the sputtering yield of boron atoms increases. As the implantation proceeds and the concentration of boron increases, the loss of boron ions by sputtering increases [109] and the relative retained dose decreases further. The measured retained dose as a function of nominal dose is shown in Fig. 7.20. The results obtained using two different implant energies are shown. At high energies (> 2 keV) the retained dose is close to the normal implant dose and follows the dashed straight line. As the implant energy decreases to below 2 keV, the retained dose decreases dramatically. If BF2 instead of boron is used for implantation, loss of boron by sputtering becomes larger [109] (not shown in the figure). During thermal annealing of the shallow junctions, a larger fraction of boron is lost by out diffusion into the ambient. If low energy implantation is done through a deposited or native oxide layer, a significant fraction of boron is implanted into the oxide and is lost. We conclude that the implant energy should not be decreased too much. 7.8.2
High ramp
rates and spike anneals
Effect of ramp-rates The TED decreases with the depth of the junction (the junction depth is approximately equal to the projected range of the implant) [109, 20, and references given therein]. However TED is still a problem in the shallow junctions. The early experiments showed that the duration and magnitude of TED decreases rapidly as the temperature of annealing increases [20]. The {311} extended defects are not stable at high temperatures. Instead of inducing significant TED, the Si interstitials find other pathways (diffusion to the surface, into the substrate, recombination with vacancies or pairing with other defects) to disappear. At high temperatures the effective activation energy for the TED is negative [109]. This means that if the temperature can be increased to high
7.8.
ULTRA-SHALLOW JUNCTIONS
223
values very rapidly TED is suppressed. Two methods of rapid annealing, conventional rapid thermal annealing (RTA) and spike anneal, are used to suppress TED. Mannino et al. [80, 81] have investigated the effect of RTA ramp rates on boron marker-layers implanted in Si. RTA was done with ramp rates of 0.1, 1.0, 10, 100 and 300~ Two peak temperatures, 950 and 1100~ were used with a soak time of a few seconds. In each case diffusion length LTED Was calculated using the relation L~E D -- (a 2 --a02) where a is the standard deviation and the subscript '0' indicates the as grown layer. LTED decreases substantially with the increase in the ramp rate. For example while annealing at 1100~ LTED decreases from 40 nm to 20 nm by increasing the ramp rate from 1 to 100~ At this high ramp rate the thermal displacement is only 3 nm. It appears possible to suppress the TED completely by increasing the ramp rate sufficiently. However very high ramp rates will be required. The TED increases with the total implantation dose because the total number of injected interstitials becomes large. Thermal diffusion becomes significant above 900~ If the peak annealing temperature is 1100~ the thermal diffusion becomes quite large. The thermal diffusion is also suppressed considerably by increasing the ramp rate.
Spike anneals There is 0 s soak time in the ideal spike anneal. In practice the soak time is finite but small. Spike anneal has several advantages over the conventional RTA with several seconds of soak time [109, 110]. Spike anneal yields significant improvements in the junction depth and reduces overall thermal budget. This in-turn reduces total lateral diffusion per side in a p-MOSFET by 25% without changing the extension implant. More recently Lindsay et al. [110] have investigated the effects of RTA, spike anneal and oxide thickness on the boron profile (see Fig. 7.21). In the RTA the soak time was 10 s and in the spike anneal it was 1 s. The up-ramp rates were 100~ for the spike anneal and 50~ for the soak anneal. The corresponding down rates were 80~ and 50~ respectively [111]. Fig. 7.21 shows that the TED is significantly higher in the slow-ramp soak anneal than in the fast-ramp spike anneal. The abruptness also degrades by the soak time and by the thicker oxide. Lindsay et al. [110] found that the oxygen content in the ambient also affects the junction depth and the resistance (not shown in the figure). The literature values of resistance versus junction depth [109] are plotted in Fig. 7.22. This figure shows that several data points overlap even though their process parameters are not identical [109]. This happens because both junction depths and resistance do not depend uniquely on any one parameter e.g. the ramp-rate. They depend on implant energy, implant dose, ramp rate and soak time. If smaller energy or dose are used, shallow junctions with higher resistance are obtained. The same result is obtained with somewhat larger doses or energies but high ramp rate [109]. Agarwal et al. [109] have investigated the SIMS profiles in Si implanted with boron without removing the native oxide
224
C H A P T E R 7. FETS AND OTHER DEVICES
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Figure 7.21: SIMS profiles and resistance R s for spike and soak annealed boron implanted samples. The implantation was done at 0.5 keV with a dose of 1 x 1015 cm -2 through i nm and 4 nm oxides. The abruptness degrades by the soak in RTA and also by the thicker oxide. The abruptness (abbreviated as abrupt) is defined as the change in depth corresponding to the change in concentration from 1 x 1019 cm -3 to 1 x 1018 cm -3 and is measured in nm as shown [110].
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1000 E 9
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O0
I
t
I
20
40
60
80
I00
,
120
xj at 1x 1018 cm-3 (nm) Figure 7.22- Comparison of sheet resistance and junction depth data from various sources compiled by Agarwal et al. [109]. Despite the fact that different rates and ion implantation parameters were used, all the data from spike anneal fall in a rather narrow band with approximate 1Ix dependence [109].
225
7.8. U L T R A - S H A L L O W J U N C T I O N S 1021 --, 1020
%__
g 1019 ~ 10TM
r~
1017 ]
_ , J !
O0 10
~
20
1
30
---r-
40 50 60 Depth (nm)
-
. - -
70
-
.
. . . .
80
90
Figure 7.23: SIMS profiles of boron junctions after implantation (A - 1 keV B, 1 x 1015 cm -2 into crystalline Si; B - 4.5 keV BF2, 1 x 1015 cm -2 into GeF2 pre-amorphized Si) and after spike annealing (A-*C, B--+D; ll00~ 1 s) [60].
from the Si surface. Several doses and two energies, 0.5 keV and 0.2 keV, were used. The implanted wafers were spike annealed at 1050~ The SIMS profiles for the 0.2 keV implant with a dose of 3 x 10 TM cm -2 and for the 0.5 keV implant with a dose of 1.7 x 10 TM cm -2 were nearly identicM. It is therefore possible to avoid the ultra-fast ramp rates but modify the implant parameters to obtain the same results. In order to avoid non-uniformity and non-repeatability the ramp rates should not be too high. For future sub-100 nm devices sub-1 keV implants will be required. The discussion of this section shows that the implant energies below 0.5 keV are not desirable and may not be necessary. Similarly spike anneal with high ramp rates is required but too high ramp rates are not recommended. The ambient in which annealing is done also affects the junction depth and resistance. It is a challenging task to achieve an optimum design for sub-lO0 nm transistors by adjusting implant dose, energy, ramp rates, ambient and oxide layer thickness so that each of these parameters is utilised optimally. The design must ensure that the uniformity is maintained and the process is repeatable. Other methods of reducing TED are also being tried. TED can be reduced by amorphization prior to ion implantation using isoelectric ions [20]. The clustering of boron near the peak which makes the boron immobile is eliminated by the amorphization process. Pre-amorphization of the Si surface prior to boron implantation leads to a reduction of the channeling tail, thereby allowing for shallower, more abrupt junctions. In addition, it has been found that implanting BF2 instead of boron (at the same equivalent boron energy) results in shallower junctions after annealing, a result which is tentatively ascribed to the co-implanted fluorine. In an approach to combine these two benefits, pre-amorphization with GeF2 ions has been used to fabricate shallow p-type junctions. Fig. 7.23 shows boron concentration profiles after implantation and after spike anneMing (ll00~ 1
226
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
s). By changing from a 1 keV boron implant into crystalline Si to a 4.5 keV BF2 implant into GeF2-pre-amorphized Si, a significant reduction of the channeling tail is seen, as expected. A spectacular difference in junction depths is observed for these two samples after spike annealing: the junction depth Xj is decreased from 65 nm for the reference sample to 30 nm for the GeF2/BF2 sample. Changing the concentrations of co-implanted fluorine by using other implant variants (always with the same effective Ge and boron implant energies) leads to a proportional scMing of X j in between 30 and 65 nm. This suggests that the junction depth reduction is strongly related to the co-implanted F. Indeed, SIMS measurements after RTA show that going from BF2 implantation to GeF2/BF2 leads to a significantly stronger incorporation of F into the near surface region. This suggests that fluorine probably traps Si interstitiMs and reduces the driving force for TED. Alternatively, the reduced junction depth may result from a chemical interaction between F and B. Clearly, this subject needs further investigation. The sheet resistance Psh for the shallowest junction (Xg-30 nm) is 390 ~/sq. These junction parameters are among the best obtained until today using ion implantation and rapid thermal annealing, breaking through the trade-off curve between Xj and Psh that is generally observed for ptype junctions. It is expected that further optimization of the pre-amorphization and implantation conditions (e.g., < 1 keV B) together with more aggressive spike anneals will lead to additional improvements in junction performance. The approach of pre-amorphization with co-implanted fluorine (PAF) was used for forming extensions in a 0.13 #m PMOS process flow, featuring a 2.3 nm pure gate oxide. From electrical analysis it is found that the underdiffusion of the extension decreases with increasing fluorine concentration. For the implant/anneM variants shown in Fig. 7.23, the overall source/drain underdiffusion is reduced by 25 nm when using GeF2/BF2, consistent with the measured reduction in X j. Furthermore, the measured source/drain series resistance was ~ 500 f~#m, with a 10% improvement with the PAF approach. It can therefore be concluded that PAF is suitable for the fabrication of sub-100 nm PMOS transistors. One drawback, however, is that the co-implanted fluorine is observed to enhance the penetration of boron through the thin gate oxides, leading to undesired shifts in the threshold voltage. This implies that a successful implementation of PAF may require the utilisation of heavily nitrided gate oxides (or high-k dielectrics) to increase the resistance against boron penetration. Alternatively, the CMOS processing scheme could be modified to prevent the introduction of fluorine atoms into the gate electrode during extension implantation.
7.9 7.9.1
Application junctions Raised
of
SiGe
source and drain
to
ultrashallow
junctions
Recently several groups have used SiGe technology to improve ultrashallow junctions for deep submicron technology [102, 49, 50, 51, 24, 75, 23]. Raised
7.9. A P P L I C A T I O N OF SIGE TO U L T R A S H A L L O W J U N C T I O N S 20
A
v
E
. . . . . . . . . . . . . . . V --4-- Conventional at 0~ 18 \ . . o - . Conventional at -50~ - Sio.aeGeo.14at 0~ 16 , ' ~ " 'r Sio aeGeo14 at-50~ O
14
,
=. " ~ " V .
'
"
~
1
.
2
'o 1.16
W = 100 p,m .
9
,
0.2
o
O.3 Lg
(~m)
.
9
0.4
.
.~.
Sio.se_Geo.141,
0
m .
~ ... 0-9 . Sio.91Geo.oelOOnm 00nml~"~.,~,o~.~
1.22
E C~ 12
8
"conve'n~afSi .......
1.26 o~----~1.24
227
.
1.14
~ a +Ion[-50~176bLg
. w = I(X) ~m . . . . . . . . . . 0.2
o.3
0.4
d
]
1 o.s
Lg (l~m)
Figure 7.24: (a) Saturated transconductance gm versus effective gate length at different temperatures for conventional and Si0.s6Ge0.14 RSD devices, and (b) Ratio of values of ION at -50~ and at 100~ versus effective channel length for conventional and Si0.s6Ge0.14 RSD devices (Huang 2001 [49]). 9 2001IEEE source drain (RSD) junctions have received considerable attention. Ultrashallow junctions with solid-state diffusion from SiGe have been formed. Sub-70 nm CMOS devices have been fabricated using recessed junction selective SiGe source/drains. Raised (also known as elevated) source and drain MOSFETs allow fabrication of shallow junctions and thicker sacrificial layers for silicided contacts to the junctions [319, 224, 49, 51]. In RSD technology Sil_=Ge= offers many advantages. Like Si, Sil_=Ge= can be deposited selectively over the exposed source and drain areas but SiGe can be deposited at lower temperatures. Sil_=Ge= gives lower contact resistance and higher current drivability [49]. Huang et al. [49] fabricated the RSD p-MOSFETs using UHVCVD. The experiments confirmed that the use of Sil_=Ge= improves transconductance and decreases the contact resistance. The improvements increase as the channel length is reduced. Due to the shallow junction depths and lesser implantation damage both drain induced barrier lowering and leal~ge current decrease when channel length becomes small ,~ 100 nm (see Fig. 7.24(a)). The low temperature behaviour of the devices shown in Fig. 7.24(a) and Fig. 7.24(b) is also very good. Gannavaram et al. [102] have presented a new technology useful for sub-70 nm CMOS. They selectively deposited in-situ boron doped SiGe at 500~ in the source drain windows recessed to the required junction depth. The technology meets the Roadmap requirement. For 30 nm junctions the sheet resistivity was < 100 gt/sq, and contact resistivity was 1.5 • 10-s ~tcm2. Reverse leakage was less than 1% of the I o f / b u d g e t . The lateral abruptness was perfectly box shaped. Thermal integration was compatible with high-k gate dielectrics using gate-last CMOS process flow. A comparison of sheet resistance vs junction depth curves of their technology with other technologies is shown in Fig. 7.25. In the current technology, low energy ion implantation (< 5 keV) is used to
228
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S 1
"~1
I
I
I
1
I
I~
~ ~ ~
"""
",~
~o ,,m " " " - ..
4.1 I ~.1.~, t '
'
-
~
b.
In
I
~,,~gSO
70 n m " -.
~0~"~~
I
-'-._
t
" ~
~
. . . . . .
~
~ : . . ,,v " - ~ _
I
I
I
I
Higher C R/TA temp
I
I
RTA -limit -~ curve
a,;" :: p.(o&~ I - "
. . . . . . . .
--
_
"~
-
102o," :, ..I
,,~ __~_.~_~___~a___
~t ~
"-..
/
This w o r k
1
~
"~
-
"~'-~.~10~0 ~ ~ Vc
~..
-
3
-...-./o%,, ?. '-t
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
/
Figure 7.25" Compilation of best case junction RSH values for various junction formation techniques compared against future technology window (Gannavaram 2000 [102]). 9 2000IEEE form shallow junctions for nm channel-length regime. This results in degradation of current drivability [24]. The degradation occurs on two accounts: (1) source drain extension (SDE) overlap with gate is reduced and (2) carrier activation efficiency is degraded. To solve this problems Uchino et al. [24] have developed an advanced CMOS technology in which RSD windows and contact windows are formed over the field oxide. Ultrashallow junction formation occurs by solid-state diffusion from P doped SiGe and boron doped Si layers. Process steps for the raised source/drain n-MOSFET are shown in Figs. 7.26(a), 7.26(b) and 7.26(c). A cross-sectional SEM photograph of the n-MOSFET is shown in Fig. 7.26(d). Further details of the device are given in Tables 7.5(a) and 7.5(b). The junction depth was 25 nm and SDE resistance was 350 f~/sq for n-MOSFETs and 390 9t/sq for p-MOSFETs. Measurements showed excellent short channel characteristics. Drain-junction capacitance was reduced by 70 to 80%. A suitable overlap between SDE and gate was obtained and current drivability was high. 7.9.2
Poly-SiGeC
gate
It is advantageous to use n+-polycrystalline Si as the gate in n-MOSFETs and p+-polycrystalline Si as gate in p-MOSFETs in CMOS technology. Unfortunately boron from p+-polycrystalline gate penetrates through the gate oxide which results in changes in the threshold voltages. Polycrystalline SiGe gate is used because the workfunction of the gate can be adjusted by a few tenths of a volt by changing the Ge content. The sheet resistance of polycrystalline SiGe is lower than that of polycrystalline Si because grain size in the former is larger. However the problem of boron penetration and instability of threshold voltage
7.9. A P P L I C A T I O N OF SIGE T O U L T R A S H A L L O W J U N C T I O N S
229
Figure 7.26: Process steps for the raised source/drain n-MOSFET. (a)PolySi patterning and pocket implantation. (b) Selective p-doped SEG and SDE formation. (c) Tungsten local interconnection. (d) Cross-sectional SEM photograph of the finished n-MOSFET (Uchino 2001 [24]). 9 2001IEEE
230
C H A P T E R 7. F E T S A N D OTHER DEVICES
T~ble 7.5- (a) Device specifications and fabrication method. (b) Device purameters (Uchino 2001 [24]).
(a)
_
.|
,
Device
This work L
NMOS
i, ii ii
,i
.
l l llJIL
___
Drain area
0.35x10 pm
6.0xl 0 pm
S/D doping
Diffusion from P-doped SiGe
As i/i15 keV, 3x1014cm.2
Gate SiO2 thickness
4.6 nm
4.6 nm
i
PMOS
,
Cony.
ill
__
.
Drain area
0.40xl 0 pm
6.0xl 0 pm
SID doping
Diffusion from B-doped Si
BF2 i/i 10 keV, 5xl 014-cm.2
5.2 nm
4.0 nm
Gate SiO2 thickness |
i.
_ _
(b) Device
This work .
NMOS
,, .,,.,
Cony. , , .
Drain area
0.35x10 pm
6.0x10 pm
Drain capacitance
6.2 fF
19 fF
350 .Q/sq.
570 Q/sq.
Drain area
0.40x10 IJm
6.0x10 pm
Drain capacitance
11 fF
58 fF
Rext ,,,,,,,
PMOS
, |.
,
,,
, , , , ,
....
=
,.
...
Rext , . , , . . , . ,
390 .Q/sq. . . . . .
1.,
1060 .Q/sq
7.10. R E S O N A N T
231
TUNNELLING DIODES
persists. Chang et al. [136] fabricated p-MOS transistors in which a layer of polycrystalline SiGeC was introduced between the poly-Si gate and gate oxide. First n-Si was oxidized in dry oxygen at 900~ for 15 min, and a 80-90 A layer of silicon oxide was produced. Polycrystalline gates were deposited on top of the gate oxide by rapid thermal vapor deposition at 625 to 700~ After the growth of gate electrodes, 60 keV BF + was implanted to a dose of 5 x 1015 cm -2. Three types of samples were prepared. In one type, 400 nm of poly-Si gate was used. In the second type a layer of poly-SiGe was used between the gate oxide and the poly-Si gate. In the third type the SiGe layer was replaced by a SiGeC layer. The samples were annealed at 900~ for 40, 60 and 80 min and the threshold voltages of the devices were measured. The results are shown in Fig. 7.27. SIMS '
I
'
I
'
I
'
I
'
I
'
I
'
I
I 40
,
I 50
,
I 60
,
I 70
Oxide/Si
_
---<>---- O x i d e / S i G e / S i
>
6 -
~
Oxide/SiGeC/Si
e~0 o
>
4
O
2
0
, 0
I 10
,
I 20
,
I 30
,
,
I 80
A n n e a l i n g t i m e @ 900 C ( m i n )
Figure 7.27: Threshold voltages of the three devices are plotted as a function of annealing time (Chang 1999 [136]). measurements showed that boron diffused through SiGeC layer and segregated in the layer. Chang et al. [136] suggested that carbon reduces the potential of boron in the SiGeC layer and suppresses its outdiffusion into the oxide.
7.10 7.10.1
Resonant tunnelling diodes NDC
and
PVR
The principle of resonant carrier tunnelling has been known for a long time (see first edition of this book [1] for references). Applying a bias across a structure consisting of a quantum well and thin barriers surrounding it induces a small current by quantum mechanical tunnelling of the carriers through the barriers. The overall current through the device reaches a maximum whenever the energy of the injected carriers is in resonance with the energy of an eigen state of the
232
CHAPTER
7. F E T S A N D O T H E R D E V I C E S
quantum well. Thus I - V curves show sharp peaks, and every peak is followed by a region of Negative Differential Conductance (NDC). The current voltage curves of the diodes show maxima (known as peaks) and minima (known as valleys). The Peak to valley ratio, PVR, is an important figure of merit of the device. The devices, known as resonant tunnelling diodes (RTDs), are very useful for high-frequency detection and oscillations. If there is one quantum well with two barriers, the device is known as a double barrier or DB device. If there are two quantum wells and three barriers, the device is known as a three barrier (TB) device. Discrete energy levels in a double barrier quantum well structure were observed in 1974 and resonant tunnelling experiments in the 1012 Hz range were performed in 1984 [1]. Interest in negative resistance devices has grown steadily over the past several years. Most early work been has been done on tunnelling of electrons in GaAs/A1GaAs [1]. PVR of 30:1 at 300 K, frequency of oscillation exceeding 400 GHz and switching time of the order of picoseconds have been obtained [406]. These RTDs are likely to play an important role in submillimeter-wave analogue applications and as multiterminal high-speed logic devices. Several papers have also been published on GeSi strained layer RTDs. Work has been done on tunnelling of both holes and electrons. Because of several inherent difficulties, the performance of these diodes is still not as impressive as that of the RTDs based on III-V compound semiconductors. 7.10.2
Resonant
tunnelling
of holes in GeSi devices
Temperature effects Since the valence band offset in GeSi layers under biaxial compression is large, GeSi strained layers grown on Si(100) substrate are well suited for the study of resonant tunnelling of holes. As discussed earlier, strain removes the degeneracy of the heavy and the light hole bands. It is possible to adjust the strain in such a manner that only the heavy or the light holes are injected into the system. GeSi strained layer RTDs were first fabricated in 1988 by Liu et al. [407] and by Rhee et al. [412]. The structure of diodes fabricated by Liu et al. [407] consisted of a GeSi quantum well separated by Si barriers and grown on a Si(100) substrate. Rhee et al. [412] fabricated the diodes on relaxed buffer layers of different Ge concentrations. They were able to distribute the strain between the well and barriers in any desired manner. By changing Ge concentration in the buffer layer, the barrier or the quantum well or both can be strained. This work was followed by several papers published from 1989 through 1993 (see references [410, 408, 409, 416]). However, the best PVR obtained until recently was only 3 at 4.2 K (the value has improved recently, see Table 7.7 given later). Gennser et al. [413] made extensive measurements of I - V characteristics of GeSi hole RTDs over a large temperature range. They derived resonant energies from the observed characteristics and compared them with the theoretically predicted values. The characteristics remain practically independent of temper-
7.10. RESONANT TUNNELLING DIODES
233
ature up to 70 K. In this temperature range, interface scattering probably limits the performance. If this explanation is valid, it should be possible to increase the PVR by improving the quality of the interface. Two resonances at 150 meV and 300 meV were seen in the I - V curve. They were identified as being due to the lowest heavy hole (HH0) and light hole (LH0) states, respectively. An additional resonance due to second heavy hole state (HH1) was seen in the (dI/dV) - V curve. For any bias value a temperature-dependent current was observed above 70 K. Temperature-dependent currents can arise due to thermionic current or thermally assisted tunnelling. At any bias value well below the resonant state, the current density JrCs can be approximated by [413],
J~s = A~Tln
(
l+exp-(Er-EF,
c-e~eV)/kT
1 + e x p - ( E ~ - EF,~- (1 - a ) e V ) / k T
)
'
(7.2)
where the prefactor A~ depends oil the transmission coefficient and effective mass, V is the applied bias, Er is the energy of the resonant level, EF, c is the Fermi level of the contact and aeV is the energy difference between the emitter valence band edge and the bottom of the quantum well. If the activation energy r = ( E ~ - EF, c - ~eY) >> kT, Eq. (7.2) reduces to
J ~ - A~T 2 exp(-r
(7.3)
The thermionic current is given by, Jthermionic
--
A*T 2 exp(-r
(7.4)
where A* is the effective Richardson constant and r162 is the barrier height. The two equations are similar as far as the temperature dependence is concerned. Gennser et al. [413] were able to fit the currents observed at different temperatures with two thermally activated terms of the form given in Eq. (7.3) or Eq. (7.4) plus a temperature-independent part I0 due to a pure tunnelling component. The magnitude of the activation energy did not correspond to any reasonable value of the barrier heights and it was therefore concluded that the thermionic component was negligible. By extrapolating the activation energy to 0, values of resonant state energy with respect to the Fermi level in the cathode were extracted. By allowing for the temperature effect on the Fermi energy, resonant energies were determined. The resonant energies were also calculated by solving self-consistently the SchrSdinger equation separately for the light hole and the heavy hole in square well potentials. Table 7.6 shows that the measured and calculated energies are in good agreement. In the analysis no mixing of the heavy hole and light hole bands was assumed. Since tunnelling measurements under applied magnetic fields show considerable mixing of these states, the agreement is somewhat surprising. The mixing might have been masked by the uncertainties of the calculations, resolution of the experiment and the simplicity of tile model used. Gennser et al. [413] also studied relative contributions of different resonances and concluded that at high temperatures the PVR is reduced due to tunnelling through higher-order resonances.
234
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.6: Calculated and measured values of the resonant states in meV measured from the valence band edge of the well (see text) [413]. HH0 LHO HH1 LH1
Calculated 25 + 3.5 57 + 7 100 + 12.5 220 + 35
Measured 37 + 5 50 • 5 81 • 10 191 + 20
Effect of magnetic field Extensive theoretical and experimental investigations of hole tunnelling in the GeSi RTDs under applied magnetic field have been made [351, 408]. As the magnetic field is applied parallel to the interface, the path of the holes passing through the interface is deflected. This is equivalent to reduction in the kinetic energy in the tunnelling direction and therefore additional voltage is needed to obtain the tunnelling currents. Using WKB approximation, the shift in resonant peak position is given approximately as eB2(2s 2 + 2b2 + w2)/3m *, where s, b and w are the thicknesses of the spacer, barrier and well, respectively, and B is the applied magnetic field [351]. This relation is well satisfied by the experimental data [351]. For a magnetic field in a direction perpendicular to the interface, the results are more complicated and not well understood.
Noise in R T D s Noise behaviour of a RTD is very complex [415]. The diode produced more noise at 77 K in the resonant tunnelling mode than at room temperature as a bulk resistor. The flicker noise varied as 1 / f 2 rather than 1 / f commonly observed in other devices. The magnitude of the flicker noise depended on both the magnitude of the current and on the polarity.
7.10.3
Electron tunnelling in GeSi RTDs
Electron resonance tunnelling in the GeSi structures has been studied by Ismail et al. [414], Chiang et al. [409], Krstelj et al. [416] and more recently by Suda et al. [25] and by Paul et al. [26]. Ismail et al. [414] fabricated the device on a highquality Ge0.3Si0.7 relaxed n type doped buffer layer grown on Si(100) substrate. The tunnelling structure consisted of a 5 nm Si well sandwiched between two unstrained Ge0.3Si0.7 barriers. There were two 15 nm Si layers on both sides of this structure. A phosphorous doped 30 nm GeSi layer and a 4 nm Si cap layer were deposited on the top of the device. Current voltage characteristics were measured at room temperature and at 77 K. At room temperature the PVR was 1.2. At 77 K the PVR improved to 1.5. There was a finite current at vanishingly small voltage, which indicates that the Fermi level on both sides
7.10.
RESONANT
TUNNELLING
DIODES
235
of the tunnelling junction is within -., l k T of the position of the lowest sublevel in the well. The slopes close to zero bias for the two polarities were different, indicating that the RTD was asymmetrical. Circuit oscillations in the NDC regime were seen. The onset voltage for NDC was about 0.5 V, considerably higher than the theoretically estimated value of 0.1 V, which shows that the internal resistance of the device was high. RTDs with qualitatively similar structure have been fabricated and studied by Krstelj et al. [416]. Ge concentration in the relaxed buffer layer and in the barrier layers was x -- 0.35, the width of the well was 2 to 5 nm and that of the barriers, 4 to 7 nm. The characteristics of the diode were symmetrical. Two distinct peaks were observed in the current voltage characteristics at 150 K. As the temperature was lowered, the low-voltage peak disappeared below 50 K. At 4.2 K, the PVR had its largest value of 2. Krstelj et al. [416] suggested that the anomalous behaviour of the lowvoltage peak may be due to phonon-assisted tunnelling or quantization of the emitter states. At higher temperature both mechanisms can cause tunnelling. In the first case, the phonons are available only at the higher temperatures. In the second mechanism, higher states of the barrier are occupied at higher temperatures, from which tunnelling is possible at a lower voltage. Like the hole RTDs, the PVR is small in the electron RTDs. The performance of GeSi RTDs has not yet reached a level that can be exploited in any useful device. However, according to theoretical predictions, a high value of PVR in the range of 10 to 30 is possible at 77 K [409].
7.10.4
R e c e n t work
Recently several groups have reported improved SiGe resonant tunnelling diodes [26, 25, 2]. We have collected the PVR values obtained by different groups in Table 7.7. This Table shows that in the earlier data the highest value of PVR is about 2 and this value was obtained only at low temperatures. No NDC in hole devices has been observed above 77 K. Best value of PVR (>_ 7.6) at room temperature has been observed recently in electron devices by Suda et al. [25]. We discuss this work in detail in this section. Suda et al. [25] fabricated both DB and TB electron devices and compared their NDC performance. The devices were fabricated using gas-source MBE on a 0 . 8 - 1.2 flcm n-type Si(001) substrate. The Ge fraction x in the Sil_xGex barriers was 0.3. The structure, layer compositions and thicknesses are shown in Fig. 7.28(a). The SiGe barriers were unstrained and were grown on strain relaxed SiGe buffer layers. The buffer layers consisted of alternating Si0.8Ge0.2 and Si0.rGe0.3 layers as shown in the figure. The tensile strained Si layer was grown on top of the strain relaxed layers. A DB or a TB device was fabricated on this layer. Fig. 7.28(a) shows the structure of the TB device. The observed current voltage curves for both the DB and the TB devices are shown in Fig. 7.28(b). The performance of the TB device is very superior. The PVR of the first resonance is a record value of 7.6.
236
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
Table 7.7: Comparison of observed PVR values of Sil_xGex RTDs.
x
Carder
Number of barriers
0.21
hole
2
0.22
hole
3
0.4
hole
2
0.5 0.3
hole electron
2 2
0.35
electron
2
0.3
electron
3
4.2 77 10 > 100 4.2 77 15 77 300 4.2 > 220 300
0.3
electron
3
77
Temperature (K)
PVR
Ref. No.
2. 1.8 1.1 NO 2.1 1.6 1.5 1.5 1.2 2.0 NO > 7.6
a a b b c c d e e f f g
1.67
h
(a) Liu 1988 [407], (b)Xu 1992 [411], (c) Rhee 1988 [412], (d)Gennser 1991 [413], (e) Ismail 1991 [414], (f) grstelj 1993 [416], (g)Suda 2001 [25], (h) Paul 2001 [26].
7.11
Photodetectors, waveguide switch and laser
7.11.1
IR
photodetectors
We have given an exhaustive review of SiGe based photodetectors in the first edition of this book [1]. More recently Jutzi and Berroth [89] have written a good review of SiGe photodetectors for optical communication application. We discuss more recent work on the detectors [14, 89, 87, 88] in this section. Because of the indirect bandgap, the absorption coefficient in SiGe alloys is small and large thicknesses of the layers are required for efficient detection of light. However the maximum thickness of the layer is limited by the critical thickness. Li et al. [14] inserted the absorption layer between two mirrors which form a resonant-cavity. Incident light is reflected by the two mirrors and travels back and forth which increases the total amount of light absorbed and enhances the performance of the detector. The detector is known as a resonant-cavityenhanced (RCE) photodetector. The pattern of interdigitated contacts and the schematic cross section of the metal-semiconductor-metal (MSM) detector is shown in Fig. 7.29. The absorption region consists of Sil_xGex/Si MQWs. The MQWs consisted of twenty periods, each period contained Si0.70Ge0.30(6 nm)/Si(25 nm) layers. An optimized detector requires that RI -- R2e -~d where R1 and R2 are the reflectivity of the front and back mirrors [14]. To increase the
237
7.11. PHOTODETECTORS, WAVEGUIDE SWITCH AND LASER
C'O'nO i Layer
si 6~ x
t.
9
L
t
....
9
-
.
PVR = 1.3 HE,->HF~
PVR = 7.6
/
eV
=
P,= J
50 !"
I I si?,~o~ 30A I 1 " Layer
9
I Sil.xGexlSi RTD 70l" RoomTemperature
..... B Sio.?Geo.3 30 h B " Si 60 A (well) I" TripleBarrier BB SioTGeOS30 X BB" Structure C s,~o, ,w,,, j -
Strained
|
HEo'>H~
'%
O
~' HEr
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Strain Relief
~yer
,~./////////4[ Si epilayer1500A YI~ V / / / / / / / / / ~
(a)
V////////A
n-Si(O01) ~,......,, ~
u0
0.5
(b)
1
1.5 Voltage
2
(V)
Figure 7.28: (a) Structure of TB Si]_~Ge~ electron tunnelling RTD and the band lineups calculated using the model of Ref. [341] and (b) Typical I - V curves observed at RT from the DB and TB electron RTDs (Suda 2001 [25]).
Figure 7.29: (a) Pattern of interdigitated electrodes and (b) schematic cross section (along the dotted line in (a)) of the SiGe/Si RCE MSM photodetector by wafer bonding technique (Li 2002 [14]).
238
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
reflection coefficient, the bottom mirror is a SiO2/Si distributed Bragg reflector (DBR) and the top mirror is A1203/Si DBR. The device was fabricated by the "smart cut"" and bonding technique described earlier. The area of the active region was 100 x 100 #m 2. The simulated photoresponse of the detector is shown in Fig. 7.30(a). Refractive indices of 3.5 for Si and 4.0 for Ge were 0.30
(a)
0.25
~', r @
0.20
E KI
0.15
"~; E =
0.10
r
0
0.05 0.00 ....
L __
I .....
i
1300
1290
1310
Wavelength(nm)
4O
,~
.z-
35
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o
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30
o
25 l
1260
0
!
1270
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i 0
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.
i 1300
.
I 1310
i
l 1320
,
i 1330
,
i 1340
,
i 1350
, i360
Wavelength (nm)
Figure 7.30: (a) Simulated quantum efficiency of Si0.TGe0.3 of the SiGe/Si MQW RCE MSM photodetector and (b)Observed responsivity spectra of the same detector (Li 2002 [14]). used in the simulations. The refractive index of SiGe alloy was obtained by linear interpolation. The absorption coefficient of Si0.70Ge0.30 at 1300 nm was estimated to be 40 cm -1. The peak quantum efficiency at 1300 nm was about 25% and the FWHM of the responsivity was less than 1 nm. The breakdown voltage of the detector was 10 V and the dark current at 5 V was 230 nA. Fig. 7.30(b) shows the experimental responsivity of the detector. The figure shows a responsivity of 44 m A / W at 1314 nm and an FWHM of 6 nm. The measured quantum efficiency at 1314 nm was 4.2%, considerably lower than expected on the basis of the simulations. The discrepancy was attributed to the poor quality of the DBR due to inaccuracy in processing and scattering of light due to surface roughness. Nevertheless the detector fabricated by wafer
7.11. P H O T O D E T E C T O R S ,
WAVEGUIDE SWITCH AND LASER
239
bonding technique with DBR mirrors is a significant advance in the detector technology for application to 1.3 #m operation. Krapf et al. [27] have reported a Si/SiGe quantum well Infrared photodetector (QWIP) suitable for multispectral imaging. A QWIP was grown by MBE on a high resistivity n-type Si substrate. The device consisted of 20 periods of SiGe/Si QWs. Each period consisted a of boron (9.6 x 1011 cm -2) doped 30 /~ Si0.77Ge0.23 well and a 500/~ undoped Si barrier. A 300 A wide Si0.77Ge0.23 emitter p-doped to a concentration of 4 x 1018 cm -3 was grown on top of the QWs. Finally the whole structure was capped with heavily p-doped 5000/~ Si layers at the top and bottom. The photocurrent response of the detector was measured at 10 K. It showed peaks at 1300, 1800, and 2500 cm -1. A broad band at 4000 cm -1 was also observed. The first three peaks were assigned to HHI-~HH2 inter-subband transitions in the QWs, HH--.(SO+LH) intervalence band transitions in the SiGe emitter and H H ~ ( S O + L H ) transitions in the QWs. The device is capable of detecting at long, mid and short wavelength atmospheric windows. Luan et al. [141] have fabricated Ge photodetectors using 1 #m Ge epilayers grown by the two step method described in chapter 2. The external responsivities were 550 mA/W at 1.32 #m and 250 mA/W at 1.55-#m. The electron mobility in the Ge layers was 3500 cm2/V s. 7.11.2
Optical
waveguide
switch
Optical switches have many useful characteristics. They have small size, singlemode operation and they are independent of polarization. Li et al. [10] have given a list of references on the optical switches fabricated using SiGe materials. The switches rely on carrier induced refractive index changes. In the reflection type switch the reflecting interface must be precisely controlled. Li et al. [10] have fabricated an intersectional rib optical waveguide switch with a bow-tie electrode. These switches are better than those with straight electrodes. The switch is based on the totM internal reflection and the plasma dispersion effect of SiGe alloy. It is suitable for 1.3- and 1.5-#m operation. The schematic structure of the switch is shown in Fig. 7.31(a) and that of the waveguide in Fig. 7.31(b). The width of the rib is 2a)~, the inner rib height is 2bA and the etched depth of the rib is 2b(1 - r)A. Here A is the free space wavelength of light and r is the fractional height of side regions compared to the rib-center. The switch was fabricated on a p-type Si substrate. A lightly p-doped SiGe (~ 4% Ge) was grown on a 59-nm p-type Si buffer. The rib waveguide was formed by reactive ion etching. The n + injection region and the p+ collector were formed by phosphorus and boron ion implantation respectively. The chip was mounted on a copper heat sink to maintain the temperature constant during the measurements. 1.3- or 1.5-#m light from InGaAsP laser diodes was coupled into the input port 1 of the waveguide and light from the waveguide rib was collected by a lens and measured by an infrared image converter tube or an optical power meter and displayed on a video monitor. At zero injection current only port 4 shows the output signal. As the injection current increases to 85 mA for 1.3
240
C H A P T E R 7. F E T S A N D O T H E R D E V I C E S
2a~ (a)
no (b) f - ~ ~ ~ ~ . ~
In
-r)k
Si(100) substrate
Figure 7.31" (a) Schematic structure of a SiGe-Si intersectional rib optical waveguide switch with a bow tie electrode and (b) configuration of the waveguide (Li 2002 [10]). 92002 IEEE
#m light and 78 mA for 1.3 #m light the output light switches to port 3. This happens because when carriers are injected, the refractive index of SiGe layer decreases and total internal reflection takes place. The extinction ratio was larger than 38.5 dB and insertion loss was less than 1.70 dB. The refractive index can be changed and an optical waveguide can be constructed by applying stress to a localized stripe region in a semiconductor. The stress can be created by growing a stripe of different lattice constant on the semiconductor [193]. Rho et al. [78] have demonstrated the fabrication of such a waveguide by depositing a Si3N4 stressor stripe on a SiGe layer.
7.11.3
SiGe
QW
resonant-state
terahertz
laser
Currently quantum cascade lasers (QCLs) are based on III-V compound technology and operate at 10 #m. However it is difficult to build QCLs at longer wavelengths [6]. Attempts have also been made to fabricate QCL based on SiGe [84]. Altukhov et al. [6] have built a resonant-state laser (RSL) based on a SiGe quantum well. The laser structure, design and emission spectrum are shown in Fig. 7.32. The p-type Sil_xGex quantum wells were grown by MBE on a 5-mm thick n-type Si substrate. The SiGe layer was 5 doped to a concentration of 6 x 1011 cm -2. The Ge concentration in the well layers was 0.15. The layer thicknesses and sequence of layers are shown in Fig. 7.32(a). The two Si layers were 5-doped in the middle to a concentration of 4 x 1011 to 1012cm -2. The finished structure of the laser including contacts and emission of light is shown schematically in Fig. 7.32(b). Spectra of 4 samples were measured in the energy range 10-15.5 meV and at different applied voltages. Fig. 7.32(c) shows intense THz emission at 104 pm at 1000 V. The inset shows the spectrum at 1500 V. The modal structure of the emission was studied at 1000 V and 500 V. At the higher voltage structure was complex probably because several modes were excited. The authors suggested that it was laser emission from a population inversion in the QW due to the resonant states of boron.
7.11. P H O T O D E T E C T O R S , W A V E G UIDE S W I T C H A N D L A S E R
241
Figure 7.32: (a) Schematic view of the laser structure, (b) laser design and (c) spectrum of stimulated THz emission at 1000 V and in the inset at 1500 V (Altukhov 2001 [6]). 7.11.4
Miscellaneous
devices
Conventionally Thermoelectric (TE) cooling in solid-state is done by devices based on Bi2We3 coolers. They are used extensively in microelectronic and optoelectronic devices for cooling and for temperature stabilization [46]. Polycrystalline SiGe alloys are also used as thermoelectric materials. It has been shown recently that thermoelectric coolers fabricated using Si/Ge superlattices show very good performance. Interested readers may read papers by Koga et al. and by Fan et al. [127, 85, 45, 46] and earlier references given in these papers. Several other devices based on SiGe technology are discussed in the first edition of this book [1]. Notable among them are Bipolar Inversion Channel Field Effect Transistors (BICFETs) and Mixed Tunnelling Avalanche Transit Time (MITATT) diodes.