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An active R filter using CMOS transistor arrays
378
World Abstracts on Microelectronics and Reliability
mass-bonding to the copper 14- and 16-lead complementary-metal-oxide-semiconductor and diode-transistor-logic IC chips. The chips on the copper tape are then bonded to lead frames for dual in-line packages.
Dielectric isolation techniques for integrated circuits. J. R. BOSNELL. Microelectron. and Reliab. 15, 113 (1976). There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anistropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.
tungsten, and glass. Plasma-etching technology has made major strides during the past two years or so. These advances include new processes for treating particular materials, and new equipment that can achieve lrue run-torun reproducibility in the etching of semiconductor wafers. These recent developments are reviewed and explained in this article.
Development of bubble memory chip test system. YOSHIFUSA WADA, KOUSUKETAKAHASH!and SEUCHI SUGA. N E C Res. & Develop. No. 41. p. 61. (April 1976). This paper deals with an automatic bubble memory chip test system. The bubble memory chip test system was designed to check both overall operating margins of major-minor loop configuration (M/m) blocks and individual operating margins of elements in the block. The test system was composed of a peripheral drive unit, parameter control unit, data control unit, switch box unit and central control unit with a paper tape reader and an I / 0 typewriter unit. In this test system, based on the test programs, operating conditions and test data patterns are automatically set, and bubble memory chip operating margins are measured through read data error-checkings. Resultant operating margins were used for both chip sorting and chip design analysis.
A survey of plasma-etching processes. RICrtARD L. BERSIN.
Computer algorithm to determine MOS process-parameters. F. M. KLAASSEN,W. DE GROO'r and F. L. VAN DE MARK'I.
Solid-State Tech. 31 (May 1976). The use of plasma for etching metals, semiconductor materials and dielectrics in the manufacture of microelectronic devices is an established technology. The first plasma-etching processes were developed about ten years ago. Now plasma is used widely in the commercial processing of materials such as silicon, silicon oxide, silicon nitride, tantalum compounds.
Philips Res. Rep. 31, 84 (1976). By dividing the MOS process parameters into two groups, the current equations may be arranged such that relations result which are linear in the parameters. From this a rapid automatic routine can be developed to determine these parameters from leastsquares fit. Moreover, the procedure is closely related to the present measuring practice.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
Evaluation of technology options for LSI processing elemoats. PETER W. J. VERHOFSTADT. Proc. IEEE 64 (6), 842 (1976). A general overview of the semiconductor technologies available for the manufacture of microprocessors and bit slices is given. Both MOS as well as bipolar processes are covered. Advantages and disadvantages of PMOS, NMOS, CMOS, TTL, ECL and I2L are discussed. Several of the more special-purpose tecnologies are briefly mentioned. A comparison is done on the basis of performance, cost, and application, and suggestions are made as to which technology will service best which application. A general prediction is made as to which processes will survive as main stream technologies and what developments can be expected in the near future with respect to improvements. Applications are separated into cost-sensitive lowchip-count areas and high performance bit-slice-oriented approaches.
Test system checks microprocessors and LS1 memories. CHARLES COHEN. Electronics p. 17E (July 1976). A modular test system built around a flexible micropattern generator performs dynamic functional tests on both present and future microprocessors and memories made with largescale integrated circuits. Developed by Takeda Riken of Japan, the system is also suitable for engineering and production testing of other LSI circuits including those used in calculators, watches, and the read-only and randomaccess memories in communications systems. The tester can accommodate memories as large as 65,000 18-bit words, the company says.
MOS moves into higher-power
applications. MARVIN VANDER KooI and LARRY RAGLE. Electronics p. 98 (June 1976). V-groove structure enables family of field-effect transistors to handle up to 25 W with linear output and high impedance.
SYSTEMS
AND
EQUIPMENTS
Integrated microwave transistor amplifiers. R. S. PIiNG~LLY. Electronics & Power p. 449 (July 1976). In the last decade. microwave semiconductor devices have advanced from the fundamental study of their physical phenomenon to become an accepted building block in microwave systems. Simultaneous developments in circuit technology and techniques for design and measurement have permitted the new devices to be fully exploited; for instance, solid-state amplifiers can now be used to replace travelling-wave tubes in many low-noise and medium-power applications.
A low-power circuit block for digital telephone exchanges. D. KASPERKOVITZ and R. J. M. VERBEEK. Mieroeleetron. and Reliab. 15, 163 (1976). An integrated static 128 bit serial memory with logic circuitry at its input and transmission line drivers at its output is described. It works at a supply voltage of - 2 V ± 17~i~. Its power dissipation is 90 mW, and its maximum clock frequency is 40 MHz. Chip size is 3 x 4 m m 2.
Microprocessors and integrated electronic technology. GORDON E. MOORE. Proc. IEEE 64 (6), 837 (1976). The microprocessor has made it possible for a standard complex function to be employed in a broad range of applications that extends the applicability of large-scale integration (LSI) to many situations that could not support special chip designs. This in turn has freed the technology from previous restrictions to evolve in directions appropriate for microprocessors and associated LSI functions. The result is that many new variations of circuit design and process technology have arisen that lead toward more dense and higher performance integrated circuit structures.
An active R filter using CMOS transistor arrays. S. V. NAIMPALLY. Int. J. Electronics 40 (5), 513 (1976). A versatile state variable active R filter is described, which uses only
379
World Abstracts on Microelectronics and Reliability
to map the stepwise temperature distribution of a heated surface. From the color-digitized thermograms the chip temperature rise over the ambient air can be computed with the aid of thermocouple measurements. The color thermograms also help evaluate the thermal resistances of the chip and the ceramic carrier, which are used in the thermoelectric analogical analysis of steady-state heat flow from the chip to the surrounding air under free convection condition. The chip temperature rise as evaluated by the thermoelectric analysis checks reasonably well with the infrared and thermocouple measurements. These two methods have their respective advantages in determining the temperature of integrated-circuit chips.
resistors and CMOS transistor arrays as the circuit elements. The CMOS array can be used to produce either an integrator or an inverting amplifier depending on the power supply voltage. The design equations are very simple and with some modifications, the filter can be used to realize any biquadratic voltage transfer function in a straight-forward manner.
Eight-bit microprocessor aims at control applications. W. E. WICKES. Electronics p. 101 (June 1976). LSI chip uses single power supply, interfaces with any 8-bit bus-oriented TTL-compatible peripherals. Determination of temperature of integrated-circuit chips in hybrid packaging. ER-YUNG YU. IEEE Trans. Parts, Hybrids, and Packaying. PHP-12 (2), 139 (1976). This paper describes an infrared technique and an analogical method to determine the maximum temperature of a beam-leaded integrated-circuit chip, mounted on a ceramic carrier. The infrared technique employs a color thermogram camera 7. S E M I C O N D U C T O R
INTEGRATED
Processor family specialises in dedicated control. ALAN WEISSBERGER, JACK IRWIN and Soo NAM KIM. Electronics p. 84 (July 1976). Just one or two chips contain all the microcontroller elements needed in low-speed, highvolume applications like appliances or credit checkers. CIRCUITS,
The configuration-based approach for 3d impurities in palladium and platinum. GWYN WILLIAMS. Solid-State Commun. 19, 821 (1976). It is suggested that the magnitude and variation of the characteristic temperature associated with 1st transition series impurities in Pd and Pt could be interpreted within the framework of configurational phase stability criteria. Td-pyramids in silicon epitaxial layers. H. AHARONI. Vacuum 26 (4/5), 181 (1976). The external shapes of tripyramid defects are summarized and typical shapes, deviations from the typical, and the interactions between tripyramids and stacking faults are described. Two basic types of typical tri-pyramids were observed, one with a single peak, and the other with three peaks. The symmetry of the typical tri-pyramids is three-fold. The angle between the apexes of the three pyramids composing the tri-pyramid is 120". Each of the pyramids composing the tri-pyramid is a single crystal but with crystallographic orientation different from that of the rest of the layer. The deviations consist of amputated tri-pyramids, bi-pyramids and monopyramids, none of which are symmetrical. The layer surface nearest the tri-pyramide is not planar, but distorted. Dash etch was used to reveal stacking faults interacting concentrically with typical tri-pyramids. The dimensions of the tri-pyramid and the stacking fault are proportional to the epitaxial layer thickness. Photographs of interactions among tri-pyramids and stacking faults are obtained by using S.E.M. to obtain high resolution, which reveals finer details in higher magnifications. Traces of SiC or SiO 2 or other foreign materials, together with some basic mechanism, are probably responsible for tri-pyramid formation, They can be prevented by proper treatment of the silicon substrate prior to the layer growth. Photo-thermal probing of Si-SiO2 surface centres--ll. Experiment. R. F. PIERRET and B. B. ROESNER. Solid-State Electron. 19, 593 (1976). The results of photo-thermal probing measurements are presented and interpreted to characterize the Si SiO 2 surface center photoresponse and to provide information relevant to the evaluation of existing surface state models. Data is first presented to indisputably confirm the facts that surface center photoemission had indeed been observed and that the photoresponse could be isolated from competing relaxation mechanisms. The subsequent presentation is devoted primarily to an examination and analysis of photovoltage vs time data characterizing the surface center response. From the analysis it is concluded that two distinct types of surface centers are quasi-continuously distributed in energy over the central portion of the Si band gap, with both types of states
DEVICES
AND
MATERIALS
acting as if they were positioned right at the S-SiO 2 interface. The feature distinguishing the two types of states, referred to as A-states and B-states, is widely different photocapture cross section at any given band gap energy measured photocapture cross sections being on the order of 10-19cm2 and 10-2°cm 2 and 102 for A- and B-states, respectively. B-states, which exhibit the longer photorelaxation time constant, dominate the response in the upper portion of the band gap, while A-states dominate the response below approximately E v + 0.3 eV. Finally, the photocapture cross section of each type of state was found to increase systematically toward the band edges due to a Lucovsky-type energy dependence. Doped silicon oxide as diffusion source. A. CHECIELEWSKA and J. KOSZUR. Electron. Tech. 8 (2), 115 (1975). The paper describes a method of preparing doped silicon oxide layers using the reaction of tetraetoxysilane and phosphorus oxichloride oxidation at 400°C. The layers were examined as possible sources of phosphorus diffusion to silicon. A mathematical model of diffusion in Si-SiO 2 system has been developed. The results of computer calculations of impurity distribution in SiO2 layer have been compared with experimental data and the validity of the assumptions used in the model has been discussed.
On the mechanism of indirect band to band recombination i n germanium electron-hole drops. R. W. MARTIN. SolidState Commun. 19, 373 (1976). The line shape of all three recombination lines of electron-hole drops has been analyzed. The appropriate transition matrix element for the TA-line was found to depend linearly on the momentum of the hole only. The TO-matrix element can be visualized as a mixture of the matrix elements for LA- and TAphonons. Influence of low lifetime regions on recombination in high lifetime regions of semiconductors. B. JAYANT BALIGA and MANUEL L. TORREt
World Abstracts on Microelectronics and Reliability
mass-bonding to the copper 14- and 16-lead complementary-metal-oxide-semiconductor and diode-transistor-logic IC chips. The chips on the copper tape are then bonded to lead frames for dual in-line packages.
Dielectric isolation techniques for integrated circuits. J. R. BOSNELL. Microelectron. and Reliab. 15, 113 (1976). There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anistropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.
tungsten, and glass. Plasma-etching technology has made major strides during the past two years or so. These advances include new processes for treating particular materials, and new equipment that can achieve lrue run-torun reproducibility in the etching of semiconductor wafers. These recent developments are reviewed and explained in this article.
Development of bubble memory chip test system. YOSHIFUSA WADA, KOUSUKETAKAHASH!and SEUCHI SUGA. N E C Res. & Develop. No. 41. p. 61. (April 1976). This paper deals with an automatic bubble memory chip test system. The bubble memory chip test system was designed to check both overall operating margins of major-minor loop configuration (M/m) blocks and individual operating margins of elements in the block. The test system was composed of a peripheral drive unit, parameter control unit, data control unit, switch box unit and central control unit with a paper tape reader and an I / 0 typewriter unit. In this test system, based on the test programs, operating conditions and test data patterns are automatically set, and bubble memory chip operating margins are measured through read data error-checkings. Resultant operating margins were used for both chip sorting and chip design analysis.
A survey of plasma-etching processes. RICrtARD L. BERSIN.
Computer algorithm to determine MOS process-parameters. F. M. KLAASSEN,W. DE GROO'r and F. L. VAN DE MARK'I.
Solid-State Tech. 31 (May 1976). The use of plasma for etching metals, semiconductor materials and dielectrics in the manufacture of microelectronic devices is an established technology. The first plasma-etching processes were developed about ten years ago. Now plasma is used widely in the commercial processing of materials such as silicon, silicon oxide, silicon nitride, tantalum compounds.
Philips Res. Rep. 31, 84 (1976). By dividing the MOS process parameters into two groups, the current equations may be arranged such that relations result which are linear in the parameters. From this a rapid automatic routine can be developed to determine these parameters from leastsquares fit. Moreover, the procedure is closely related to the present measuring practice.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
Evaluation of technology options for LSI processing elemoats. PETER W. J. VERHOFSTADT. Proc. IEEE 64 (6), 842 (1976). A general overview of the semiconductor technologies available for the manufacture of microprocessors and bit slices is given. Both MOS as well as bipolar processes are covered. Advantages and disadvantages of PMOS, NMOS, CMOS, TTL, ECL and I2L are discussed. Several of the more special-purpose tecnologies are briefly mentioned. A comparison is done on the basis of performance, cost, and application, and suggestions are made as to which technology will service best which application. A general prediction is made as to which processes will survive as main stream technologies and what developments can be expected in the near future with respect to improvements. Applications are separated into cost-sensitive lowchip-count areas and high performance bit-slice-oriented approaches.
Test system checks microprocessors and LS1 memories. CHARLES COHEN. Electronics p. 17E (July 1976). A modular test system built around a flexible micropattern generator performs dynamic functional tests on both present and future microprocessors and memories made with largescale integrated circuits. Developed by Takeda Riken of Japan, the system is also suitable for engineering and production testing of other LSI circuits including those used in calculators, watches, and the read-only and randomaccess memories in communications systems. The tester can accommodate memories as large as 65,000 18-bit words, the company says.
MOS moves into higher-power
applications. MARVIN VANDER KooI and LARRY RAGLE. Electronics p. 98 (June 1976). V-groove structure enables family of field-effect transistors to handle up to 25 W with linear output and high impedance.
SYSTEMS
AND
EQUIPMENTS
Integrated microwave transistor amplifiers. R. S. PIiNG~LLY. Electronics & Power p. 449 (July 1976). In the last decade. microwave semiconductor devices have advanced from the fundamental study of their physical phenomenon to become an accepted building block in microwave systems. Simultaneous developments in circuit technology and techniques for design and measurement have permitted the new devices to be fully exploited; for instance, solid-state amplifiers can now be used to replace travelling-wave tubes in many low-noise and medium-power applications.
A low-power circuit block for digital telephone exchanges. D. KASPERKOVITZ and R. J. M. VERBEEK. Mieroeleetron. and Reliab. 15, 163 (1976). An integrated static 128 bit serial memory with logic circuitry at its input and transmission line drivers at its output is described. It works at a supply voltage of - 2 V ± 17~i~. Its power dissipation is 90 mW, and its maximum clock frequency is 40 MHz. Chip size is 3 x 4 m m 2.
Microprocessors and integrated electronic technology. GORDON E. MOORE. Proc. IEEE 64 (6), 837 (1976). The microprocessor has made it possible for a standard complex function to be employed in a broad range of applications that extends the applicability of large-scale integration (LSI) to many situations that could not support special chip designs. This in turn has freed the technology from previous restrictions to evolve in directions appropriate for microprocessors and associated LSI functions. The result is that many new variations of circuit design and process technology have arisen that lead toward more dense and higher performance integrated circuit structures.
An active R filter using CMOS transistor arrays. S. V. NAIMPALLY. Int. J. Electronics 40 (5), 513 (1976). A versatile state variable active R filter is described, which uses only
379
World Abstracts on Microelectronics and Reliability
to map the stepwise temperature distribution of a heated surface. From the color-digitized thermograms the chip temperature rise over the ambient air can be computed with the aid of thermocouple measurements. The color thermograms also help evaluate the thermal resistances of the chip and the ceramic carrier, which are used in the thermoelectric analogical analysis of steady-state heat flow from the chip to the surrounding air under free convection condition. The chip temperature rise as evaluated by the thermoelectric analysis checks reasonably well with the infrared and thermocouple measurements. These two methods have their respective advantages in determining the temperature of integrated-circuit chips.
resistors and CMOS transistor arrays as the circuit elements. The CMOS array can be used to produce either an integrator or an inverting amplifier depending on the power supply voltage. The design equations are very simple and with some modifications, the filter can be used to realize any biquadratic voltage transfer function in a straight-forward manner.
Eight-bit microprocessor aims at control applications. W. E. WICKES. Electronics p. 101 (June 1976). LSI chip uses single power supply, interfaces with any 8-bit bus-oriented TTL-compatible peripherals. Determination of temperature of integrated-circuit chips in hybrid packaging. ER-YUNG YU. IEEE Trans. Parts, Hybrids, and Packaying. PHP-12 (2), 139 (1976). This paper describes an infrared technique and an analogical method to determine the maximum temperature of a beam-leaded integrated-circuit chip, mounted on a ceramic carrier. The infrared technique employs a color thermogram camera 7. S E M I C O N D U C T O R
INTEGRATED
Processor family specialises in dedicated control. ALAN WEISSBERGER, JACK IRWIN and Soo NAM KIM. Electronics p. 84 (July 1976). Just one or two chips contain all the microcontroller elements needed in low-speed, highvolume applications like appliances or credit checkers. CIRCUITS,
The configuration-based approach for 3d impurities in palladium and platinum. GWYN WILLIAMS. Solid-State Commun. 19, 821 (1976). It is suggested that the magnitude and variation of the characteristic temperature associated with 1st transition series impurities in Pd and Pt could be interpreted within the framework of configurational phase stability criteria. Td-pyramids in silicon epitaxial layers. H. AHARONI. Vacuum 26 (4/5), 181 (1976). The external shapes of tripyramid defects are summarized and typical shapes, deviations from the typical, and the interactions between tripyramids and stacking faults are described. Two basic types of typical tri-pyramids were observed, one with a single peak, and the other with three peaks. The symmetry of the typical tri-pyramids is three-fold. The angle between the apexes of the three pyramids composing the tri-pyramid is 120". Each of the pyramids composing the tri-pyramid is a single crystal but with crystallographic orientation different from that of the rest of the layer. The deviations consist of amputated tri-pyramids, bi-pyramids and monopyramids, none of which are symmetrical. The layer surface nearest the tri-pyramide is not planar, but distorted. Dash etch was used to reveal stacking faults interacting concentrically with typical tri-pyramids. The dimensions of the tri-pyramid and the stacking fault are proportional to the epitaxial layer thickness. Photographs of interactions among tri-pyramids and stacking faults are obtained by using S.E.M. to obtain high resolution, which reveals finer details in higher magnifications. Traces of SiC or SiO 2 or other foreign materials, together with some basic mechanism, are probably responsible for tri-pyramid formation, They can be prevented by proper treatment of the silicon substrate prior to the layer growth. Photo-thermal probing of Si-SiO2 surface centres--ll. Experiment. R. F. PIERRET and B. B. ROESNER. Solid-State Electron. 19, 593 (1976). The results of photo-thermal probing measurements are presented and interpreted to characterize the Si SiO 2 surface center photoresponse and to provide information relevant to the evaluation of existing surface state models. Data is first presented to indisputably confirm the facts that surface center photoemission had indeed been observed and that the photoresponse could be isolated from competing relaxation mechanisms. The subsequent presentation is devoted primarily to an examination and analysis of photovoltage vs time data characterizing the surface center response. From the analysis it is concluded that two distinct types of surface centers are quasi-continuously distributed in energy over the central portion of the Si band gap, with both types of states
DEVICES
AND
MATERIALS
acting as if they were positioned right at the S-SiO 2 interface. The feature distinguishing the two types of states, referred to as A-states and B-states, is widely different photocapture cross section at any given band gap energy measured photocapture cross sections being on the order of 10-19cm2 and 10-2°cm 2 and 102 for A- and B-states, respectively. B-states, which exhibit the longer photorelaxation time constant, dominate the response in the upper portion of the band gap, while A-states dominate the response below approximately E v + 0.3 eV. Finally, the photocapture cross section of each type of state was found to increase systematically toward the band edges due to a Lucovsky-type energy dependence. Doped silicon oxide as diffusion source. A. CHECIELEWSKA and J. KOSZUR. Electron. Tech. 8 (2), 115 (1975). The paper describes a method of preparing doped silicon oxide layers using the reaction of tetraetoxysilane and phosphorus oxichloride oxidation at 400°C. The layers were examined as possible sources of phosphorus diffusion to silicon. A mathematical model of diffusion in Si-SiO 2 system has been developed. The results of computer calculations of impurity distribution in SiO2 layer have been compared with experimental data and the validity of the assumptions used in the model has been discussed.
On the mechanism of indirect band to band recombination i n germanium electron-hole drops. R. W. MARTIN. SolidState Commun. 19, 373 (1976). The line shape of all three recombination lines of electron-hole drops has been analyzed. The appropriate transition matrix element for the TA-line was found to depend linearly on the momentum of the hole only. The TO-matrix element can be visualized as a mixture of the matrix elements for LA- and TAphonons. Influence of low lifetime regions on recombination in high lifetime regions of semiconductors. B. JAYANT BALIGA and MANUEL L. TORREt