- Email: [email protected]
An electronic interface for microcomputer-based flow cytometry: design, operation and performance characteristics
Journal of Microcomputer Applications (1991) 14, 327-341
An electronic interface for microcomputer-based flow cytometry: design, operation and performance characteristics James A. Dvorak*, Courtney P. Muddt, Vojin K. Dvorak1 and William H. Schuette$ *Laboratory of Parasitic Diseases, National Institute of Allergy and Infectious Diseases; TApplied Clinical Engineering Section, Biomedical Engineering and Instrumentation Program, Division of Research Resources, National Institutes of Health, Bethesda, MD 20892; $6204 Singleton Place, Bethesda, MD 20817; and $Electromagnetic Signatures Department, David Taylor Research Center, Bethesda, MD 20084. USA
An inexpensive electronic interface for the acquisition of asynchronous flow cytometry data using a commercially available microcomputer and A/D converter is described. In the design of this interface, the major objectives were to minimize the amount of custom hardware necessary between the computer and flow cytometer and to maximize usable sensitivity and resolution by implementing a gated integrator and trigger hold-off approach to acquire the asynchronous data pulses from the cytometer. The major error sources which can occur during data acquisition are identified and their effects on system performance are shown. A simple protocol is described to minimize the effects of these errors on the acquired data. The influence of computer-processor clock speed on data acquisition rates is also documented.
1.
Introduction
Flow cytometry involves the collection, processing, storage, and analysis of asynchronous analogue signals generated by particles interacting with a light beam or electronic circuitry [l]. Although flow cytometers of various designs are available commercially, the electronics used to interface the cytometer per se, which generates the analogue signals, to the computer used for data processing have either not been well documented in the scientific literature, are complex and expensive, or have design aspects which could adversely influence the data being collected. In this report, the design, operation, and performance characteristics of a simple, inexpensive, but highly versatile and sensitive electronic system to interface a microcomputer with a flow cytometer for four-parameter asynchronous data collection and analysis are described. The major attributes of the electronic interface are described in sufficient detail to allow its construction and use in new flow cytometer designs or as a replacement interface for existing flow cytometers.
2.
Hardware requirements
It is assumed that the illumination, fluidics, optical, sensor, and signal preamplifier subsystems of the flow cytometer are functional and analogue signals are present at the output of the sensor preamplifiers. Minimum computer requirements include an MS DOS-compatible, Intel 80X86-based microcomputer with 640 kbytes of DRAM, an 321 0745-7138/91/040327+
15 $03.00/O
0 1991 Academic Press Limited
328
J. A. Dvorak et al.
80X87 numeric coprocessor,
floppy disc drive, an enhanced graphic adapter (EGA) or video graphic array (VGA) display, and a MetraByte Model DAS-8 or DAS-16 (MetraByte Corp., Taunton, MA) analogue-to-digital (A/D) converter card (or equivalent). An oscilloscope, which is normally present to align the optical and mechanical components of the flow cytometer, is used to adjust the electronic interface between the flow cytometer and the computer.
3.
Interface
design considerations
and objectives
The electronic interface contains analogue amplifier and integration circuits as well as digital control circuits. The electronic interface was designed to be compact, have a minimum of adjustments, low fabrication cost, ease of use and service, and the capability of being integrated into new systems or added to existing systems. To accomplish these objectives, many of the signal-processing tasks which are generally handled external to the computer were transferred to the microcomputer. The primary objective was to increase the useable sensitivity, repeatability, and resolution of the overall flow cytometer system. This objective took precedence over system throughput speed. However, with the proper selection of computer hardware, the complete system performs at throughput rates equivalent to commercial instrumentation. The analogue signals from the sensor preamplifiers contain the information concerning light scatter by the particle, fluorescence intensity of the particle, etc. As the timing of the particles passing through the laser beam is random or asynchronous, it is not possible to predict when the analogue pulses from the flow cytometer sensor preamplifiers will be present. Conversely, the microcomputer with its internal clock and A/D converter, is a synchronous device. The role of the electronic interface is to amplify, condition, and link these asynchronous or randomly occurring analogue pulses from the flow cytometer to the synchronously-based system in the microcomputer for conversion and storage. Two approaches can be used to acquire asynchronous analogue signals from a flow cytometer: (1) peak sense and hold of the analogue pulse; and (2) gated integration of the area under the analogue pulse. Using the peak sense and hold approach, the peak heights of the analogue pulses are measured and used to calculate the information concerning cell size, fluorescence amplitude, etc. However, various assumptions must be made concerning the relationship between the height of the pulse and its shape. In addition, a potentially serious drawback of this approach is its dependence upon particle flow rate. At high flow rates, the analogue amplifiers may not completely return to their initial conditions or baseline values before the occurrence of another pulse. If the amplifiers have not returned to baseline when a subsequent pulse occurs, the peak height will be the sum of the new analogue pulse height and the baseline shift or initial conditions left on the amplifiers from the previous pulse. Furthermore, noisy signals will create a high degree of uncertainty in the actual peak measurement leading to decreased resolution and a large coefficient of variation (i.e. the standard deviation divided by the mean; c.v.) of the peak. In order to avoid these problems, the gated integrator approach involving an analogue comparator was used to detect when a preselected analogue signal exceeds some userdefined threshold. The comparator ‘gates’ or turns on four independent analogue integrators which electronically integrate the areas under the analogue pulses. The integration time is set to be longer than the slowest analogue pulse expected. At the end
Microcomputer interface for flow cytometry
329
of the integration period, the integrators are turned off and hold their integrated values which are then read by the computer. When data conversion is complete, the integrators are reset to zero. The gated integrator approach has three distinct advantages over the peak sense and hold approach. First, since an actual measurement of the area under the pulse is made, no assumptions are necessary concerning the relationship between pulse height and shape. Second, integration is inherently a filtering process, so that the noise component in the actual analogue voltages converted into data by the computer is lower. And, third, after data conversion, the integrators are electronically reset to zero so that initial conditions are repeatable from measurement to measurement. One disadvantage of the gated integrator is that the throughput or measurement rate is slower since the entire analogue pulse must be measured and the integrators reset. Consequently, actual measurement times tend to be about two times longer than with the peak sense and hold approach. However, as one design objective was maximum sensitivity, gated integrators were used in the interface.
4.
Electronic
interface
description
The implementation of the gated integrator in the interface is depicted functionally in Fig. 1. The analogue portion of the interface contains four identical, adjustable-gain amplifiers and four identical gated integrating amplifiers. However, for clarity only the trigger channel is shown. The digital portion consists of the analogue comparator, flipflops to control the gating of the integrators and ‘handshaking’ with the computer, monostable multivibrators (one shots) to set the integration and reset periods for the integrators, and trigger hold-off logic to prevent the integrators from performing partial
Data received
?
Reset CO%?)
Q
?R +S
t----II
Data ready (FFII
Data ready
Q t+
I
I
I
I
bR ?S
Data received (FF2)
C_ 0
’
I
Trigger hold-off logic
Threshold
Trigger channel analogue
Offset
Non-trig. channel Trigger channel integral Trigger channel monitor
Figure 1. Block diagram of the major components of the interface. FFI, FF2 = R-S type flip-flops; OSl, OS2 = monostable multivibrators (one shots); Al = inverting amplifier; A2 = integrator; A3 = comparator; Sl, S2 = analogue switches; Cl = integrating capacitor.
330
.J. A. Dvorak et al.
Data received
One data
acquisition
cycle
_j
Reset
(02) Data (FFI)
ready
T2
.Y
Interface
control
Computer control
A
L-.-_ L
I
Data cleared (FF2) ;,aaple
Analogue
window
input
Integrator output Comparator output
I
L
L Time
in ps
Figure 2. Logic timing diagram for a typical data-acquisition cycle of the interface. Tl = Time between circuit enabling and actual acquisition of next analogue pulse; T2 = time required for A/D conversion and acquisition. The other abbreviations are as indicated for Fig. 1.
or incomplete integration of analogue pulses which may be present immediately after the reset of the integrators. The logic timing diagram for the interface, which uses two digital I/O lines present on the A/D converter card, is shown in Fig. 2 and, in conjunction with components identified in Fig. 1, depicts a typical data-acquisition cycle. At the onset of data acquisition, computer software instructs a data-received pulse to be sent to the interface to reset the integrators. The data-received pulse triggers the one-shot OS2 which generates a sufficiently long pulse (10 us) to completely reset the integrators to zero. At this point, the computer and interface operate independently. In addition, the interface is ‘armed’ and able to acquire data. As a particle enters the laser beam, the analogue signal from the user-selected trigger channel rises out of the noise and exceeds the threshold set by the operator on analogue comparator A3. The comparator changes state and sets flip-flop FF2 which triggers one-shot OSl. The output of OSl, the sample window, turns on the four gated integrating amplifiers which then integrate the four analogue pulses. The output pulse width of OS1 is set by the operator for an integration period of 10-35 us. This adjustment allows the operator to match the sample window to the analogue pulse. At the end of the sample window, S 1 is turned off, the integrators stop integrating, and hold their integrated values. Simultaneously, flip-flop FFl is set and sends a data-ready pulse to the computer signalling it to resume control and direct its internal A/D converter to read the outputs of the four integrators. The time, T2, required for these conversions is influenced not only by the conversion time of the A/D converter, but also the clock speed of the computer and amount of code which must be executed per cycle. Immediately after reading the A/D converter, computer software sends a data-received pulse to the
Microcomputer interface for flow cytometry
331
electronic interface causing the interface and computer to again operate independently. The interface resets the integrators clearing the previous data, detects the next analogue pulse used as the trigger, integrates the user-selected channels, holds the values, and sets the data-ready line. The computer processes and stores the data on the A/D converter and updates the real-time display. If the flow rate of particles is sufficiently high, the interface accomplishes its tasks in less time than is required for the computer to accomplish its tasks. Consequently, when the computer completes its processing and checks the data-ready line, new data will always be ready for conversion. Setting the actual measured data rate (conversions/s) involves increasing the particle flow rate at the cytometer until the percentage of unrecorded events exceeds an acceptable user-defined level. A unique feature of the interface is the inclusion of a trigger hold-off circuit to prevent the acquisition of pulses present in the system when the integrators are reset. After reading the voltages presented by the A/D converter, the computer sends a ‘datareceived’ pulse to OS2 to reset the integrators and start the cycle anew. Logic gates in the reset circuitry delay or hold-off the resetting of FF2 which ‘rearms’ the system to acquire a pulse if the comparator indicates that an analogue voltage above threshold is present at the time of reset. This feature prevents the system from partially integrating analogue pulses which may already be present when the reset is completed.
5. Error analysis interface
and optimization
of the electronic
In a flow cytometry data-collecting system, optical and/or electronic offset errors are present which lead to non-linear behaviour or poor resolution. A protocol utilizing an oscilloscope was developed for all system alignment functions. The horizontal amplifier of the oscilloscope is triggered by the rising edge of the sample window pulse. The signal to be adjusted is connected to a vertical channel of the oscilloscope. When data collection begins, the analogue and/or integrator signals appearing on the oscilloscope are used to optimize alignment of the optical and mechanical components of the flow cytometer. In addition, in conjunction with adjustments present on the electronic interface, they are used to minimize the effects of errors in the analogue signals. For the gated integrators used in this system, the output is given by = -(l/RC)J;e,,dt qouq = the measured output voltage, l/RC = the conversion constant of the integrator, ecin)= the input voltage, and r = time. As there are four analogue channels, any mismatch in the R and C values will produce variations in the measured ecout)even if all of the ecin)are the same. This mismatch in the integrator time constants arises from several sources. For example, precision resistors are readily available but precision capacitors are not. In addition, the ‘on’ resistance of the analogue switch, Sl, is part of the ‘R'value and for the DG201CJ switches used can vary from 100 to 125 ohms [2]. The effect of this variation could be minimized by making the resistor value large with respect to R(,,). For a given time constant, however, large values of R imply small values for C. If C is too small, the bias current drawn into the input of the op-amp A2 will reduce the charge on
where%“I)
332
J. A. Dvorak et al.
C and lower the value of ecout).Therefore, a 500-ohm trimpot in series with a 1.8-K ohm resistor was used to balance the four integrators. During initial calibration, a single test pulse is fed to all four integrators and the trimpots adjusted until all four outputs are the same. If all aspects of the interface are properly adjusted, oscilloscope traces and a histogram similar to Fig. 3(a) should result. The sample window triggers at the beginning of the analogue pulse indicating a properly set threshold. The initial and final integrator output slopes are zero indicating an absence of offset and sufficient sample window time for complete integration. However, interface adjustment errors can occur and a simple means of determining their presence and correcting them must be available. Major electronic sources of error in data collection including: (1) improperly set threshold; (2) improper sample window length; and (3) D.C. offsets present in the analogue inputs were identified and means were provided to correct them. The consequences of an improperly set threshold are shown in Fig. 3(b). Integration begins at some non-zero time value so that an integral from t, to t is obtained. Because a threshold detection scheme is used, it is impossible to set t, exactly to zero since that would assume a pulse could be detected while it is still in the noise level. This error is minimized by setting the threshold as close as possible to the noise level. Since the sample window is monitored in order to adjust the turn-off time t,, it is also used to set the threshold. If the threshold is too high, the sample window opens after the initial rise of the analogue pulse. As the threshold is lowered closer to the noise level, the leading edge of the sample window moves closer to the start of the analogue pulse. When the threshold is set too low, noise triggers the sample window and it loses synchronization with the analogue pulse and appears randomly on the oscilloscope screen. The use of an analogue delay line between the threshold detector and integrator could effect a ‘pre-trigger’ response facilitating a more robust threshold-detection scheme. However, with the signal-to-noise ratios commonly encountered in this system, the improvement in the integrated value produced by such a delay was calculated to be less than 1% which is significantly lower than the overall system noise for biological samples of 3-9%. Consequently, it was judged not to be a cost-effective feature to add to the interface. The consequences of an improperly set sample window length are similar to an improperly set threshold. As shown in equation (l), the output value e(outJis a valid measure of the integral of e(,,, only if t is sufficiently long to allow e(,,, to return to baseline before the integration is stopped. Therefore, it is necessary to monitor the sample window (output of OSl) triggered on the analogue signal ecinJtogether with ecin, and adjust the window to ensure that t is large enough to completely integrate e(,,,). If ecin)contains a D.C. offset, the integrator will integrate the offset as well as the analogue pulse. D.C. offset is not a function of time. Therefore, the output now consists of two terms, i.e. the desired signal and an error term. Since the D.C. offset can be positive or negative, the error also can be positive or negative. This error manifests itself in the form of offsets in the channel axis of the histograms [Fig. 3(c) and (d)]. To compensate for this error, D.C. offset nulling capability was added to all four analogue input adjustable-gain amplifiers. To correctly set this adjustment, the integrator outputs are monitored and adjusted for a zero slope on the integrator output at the beginning and end of the sample window period. The degree of repeatibility of the adjustable-gain amplifiers is dependent mainly upon
Microcomputer interface for flow cytometry
333
the amount of mechanical backlash present in the turns counter for R2. In this implementation, the A/D converter is configured to read analogue voltages in the 0 to + 10 V range resulting in a resolution of 244 mV. The 12-bit data are scaled to 8 bits for display, analysis and storage. With fluorescent beads, amplifier gain can be readjusted to repeatedly display a single-scaled 8-bit channel. The total combined error due to temperature drift in the amplifiers and gain resistors over a 10°C range together with the integrator output droop during A/D conversion is approximately 2.5 mV (1 bit of the 12bit A/D converter range). One of the reasons for choosing the gated integrator to acquire the signals is the ability to control the re-initialization or reset of the integrators to repeatable values. In using high speed, solid-state analogue switches to accomplish the gating, a small error introduced by these switches was discovered when the integrators were reset back to zero. During reset, the output of the integrators does not go to zero but to some value between 0 and 75 mV depending upon the initial conditions on the integrators at reset. A value of this magnitude could represent an offset of up to 30 channels (1Zbit range). This variable reset level was traced to a charge-coupled effect in the solid-state switches. When this charge-coupled effect was nulled out [2], the reset values on the integrators was f3mV.
6.
Performance
characteristics
As stated previously, one of the experimental objectives was to develop a system capable of a high degree of repeatability. To determine system gain repeatability, serial samples of fluorescence beads were assayed. During the first run, with the interface properly adjusted, the gain was set to centre the histogram on the channel axis and the gain setting recorded. The setting was then moved to a random value and subsequently reestablished with the gain value set apriori. The absolute difference between the runs was f 1 display channel (data not shown). The effect of the trigger hold-off circuitry is shown in Fig. 4. The experimental conditions were the same as described in the study of gain repeatability but in this case, for one of the two runs the trigger hold-off circuitry was disabled. When the circuit is disabled, if an analogue pulse is present when FF2 is reset, the integrators will immediately begin integrating the remainder of the pulse. When this situation occurs, the integrated value will always be less than the full value. These partial values tend to distort or skew the distribution toward lower channel numbers. The trigger hold-off circuitry prevents these partial integrations by delaying the reset of FF2 if the analogue comparator output is high, i.e. if an analogue pulse is present. As soon as the comparator goes low (analogue pulse is absent), FF2 is reset and the next pulse will be collected. With the trigger hold-off circuitry, particles could be assayed by the flow cytometer at a much higher rate without observing the ‘skewness’ shown in Fig. 4. The data collection rate and total number of particles collected were identical for both histograms. Although the interface can be used with any 80X86-based computer, the clock speed of the microcomputer is an important consideration because it directly influences the data collection rate. As shown in Fig. 5, at computer clock speeds from 8 to 20 MHz, there is a linear relationship between clock speed and the number of events/s which can be collected. This increase is due primarily to the inverse relationship between computer clock speed and the amount of time required for the computer to execute a fixed number
334
J. A. Dvorak et al.
of program instructions. It is important to emphasize that microprocessor clock speed affects only the speed at which data are collected and has no effect on the quality of the data. The data-collection rate is also influenced by the number of histograms collected, and the use of a real-time display as shown in Fig. 6. At 20 MHz, there is about a 20% improvement in collection speed when the real-time display is disabled reflecting the time required for display updating which is significant even for an assembly routine. The difference between using and disabling the real-time display becomes negligible as the (Q) IOOC 59
I 750
500
250 II7 1 178 L 5 E c
0
1
Ii
.
75c
500
64
128 Channel
number
192
256
( O167 1
3-
3-
251 3224 I
I-
z
c
z t
(d) 1000 17 1
750
5oc
25C
JL
137
A 1k
1
-
64
128 Channel
192
2 6
number
Figure 3. Oscilloscope traces and histogram of fluorescent beads (0+33*0.03 pm diameter, Cat. # 17153, Polysciences, Warrington, PA). On the oscilloscope traces the sample window is indicated by w, the normal analogue signal baseline by a double arrow, the analogue signal by a, and the integrated signal by i. (a) Properly adjusted electronic interface. Note the linear relationship between peaks of ‘singlet’ (59), ‘doublet’ (117) and ‘triplet’ (178) beads. (b) Improperly set threshold which appears as a ‘blank’ between the normal analogue signal baseline and the beginning of the analogue signal and as a non-zero slope in the integrator output. Note the decrease in amplitude of the ‘singlet’ peak and the non-linear relationship between the three peaks. (c). Positive 4-V D.C. offset present in the analogue signal appearing as an ‘upshift’ in the position of the analogue signal baseline, a non-linear slope at the beginning and end of the integrator output, and a large steady-state integrator output value. (d) Negative 1-V D.C. offset present in the analogue signal appearing as a ‘downshift’ in the position of the analogue signal baseline. The integrated signal has beginning and ending negative components resulting in a marked decrease in the amplitude of the ‘singlet’ peak and non-linearity between the three peaks.
336
J. A. Dvorak et al.
computer clock speed is decreased to 8 MHz irnplying that program execution speed has become the dominant variable. The linear increase in time required to collect an increasing number of histograms reflects additive conversion times of a multiplexing A/D converter. Only a single A/D converter is present on the A/D converter card; consecutive readings which require about 12 us each are accomplished through a multiplexing protocol on the A/D board. As the A/D conversions are handled serially,
\
:
0
64
Peak=162 Cv. = 1.96%
-Peak=160 cv =3.83%
128 Channel
192
256
number
Figure 4. Graphic representation of the effect of a trigger hold-off circuit on collected data. The sample is as described in Fig. 3. The histogram represented by the dotted line contains a low amplitude ‘tail’ resulting from partially integrated analogue pulses which were present when the integrator was reset. The histogram represented by the solid line was collected under identical conditions except that the trigger hold-off circuit was enabled. Note the symmetric shape of the histogram. The data-collection rate and the total number of particles collected were identical for both histograms. - w/Trigger hold-off, w/o trigger hold-OF, collection rate = 2000 s-r; n = 10,000 events.
IO Computer
15 clock
speed
(MHz)
Figure 5. Graphic representation of the linear relationship between the clock speed of the microcomputer processor and the number of events which can be collected.
Microcomputer interface for flow cytometry
337
MHz 20 I 1 16 1 IO 16
2
3
Number of channels coiiected
Figure 6. Graphic representation of the influence of both real-time data display and the number of channels collected on data collection rate at various microcomputer processor clock speeds (circles = 20 MHz, triangles = 16 MHz, squares = 10 MHz, inverted triangles = 8 MHz). At each clock speed (shown on the right ordinate) the open symbols represent the number of events acquired/channel (shown on the left ordinate) with the real-time display disabled. The filled symbols represent the number of events acquired/channel with the real-time display enabled.
A/D conversion time is the sum of individual A/D conversions. Although this might be considered a limitation of the system, that is not the case. The system exhibits a ‘dead time’ range of 50 to 100 ps which is similar to commercially available systems. Consequently, it is easily capable of collecting data at rates generally considered optimal in flow cytometry [3]. Although it might appear that throughput efficiency could be significantly improved by increasing the speed of the A/D converter, this is not the case. Post-acquisition software procedures are the real time-consuming aspects of the data-acquisition cycle. Therefore, increasing the A/D data-conversion speed has a negligible impact on the data-acquisition rate. In fact, the added program code often required to operate commercially-available high-speed A/D converter boards cancels out the benefits of a high-speed A/D converter in this application. However, it has a marked impact upon overall system cost. The A/D converter used in this system can be obtained commercially for under $400 (DAM) or $1000 (DAS-16) whereas higher-speed A/D converters average about $3,000.
the total
7.
Data collection
software
Although commercially-available data-collection programs are available which could be used to operate the electronic interface and A/D converter, custom data-collection and analysis programs were developed which contain all of the routines commonly available to flow cytometer systems. The programs are written in Pascal with time-sensitive portions of the code (e.g. the procedures to read and process data from the A/D converter, and real-time display of histogram development during data collection)
338
J. A. Dvorak et al.
written in assembly. The code segment of the data-collection program occupies about 27 kbytes of memory. A flow diagram summarizing the data-collection program is shown in the Appendix. The program is divided into subroutines which can be accessed by a single key stroke from the main menu. Once the program is instructed to collect data, it monitors the status of the data-ready line from the electronic interface. When the data-ready line goes high, indicating valid data are present at the outputs of the integrators, the program scans the A/D converter channels in the sequence specified by the operator, scales the 12bit data values to g-bits for display, stores the g-bit data in memory, and updates the real-time display on the monitor. Data are stored in DRAM as a series of 32-kbyte blocks consisting of four g-bit fields. Each field contains the channel number of an event in the corresponding histogram. Each block is identified by a 32-bit pointer stored in a sequential array. About 150,000 four-parameter events can be stored in DRAM. Data are stored on disc as a binary file consisting of a direct memory map of the 32-kbyte blocks. A second file, written in ASCII, with the same name but a different extension, containing the number of histograms, number of counts, identification of any mathematical transforms performed on the histograms, labels and comments is also stored on disc at the same time. This twofile system eliminates the problems associated with header blocks when converting or importing the data to other programs. One unique aspect of the data-collection program is that many functions which normally require hardware are implemented in software, resulting in substantial cost savings as well as increased reliability and stability. For example, the software can perform an exponential transform of the analogue values making up a histogram [4] and display the results of the transform in real time. This transform simulates an infinite series of non-linear amplifiers [5] and obviates the need for and the restrictions of logarithmic and exponential amplifiers. In addition, it is possible to minimize the overlap between any two analogue signals without additional electronics. The process is done in real time using previously described algorithms [6]. The ability to calculate the C.V. of the peak is provided in the collection program. However, if a histogram has been transformed in any way, a software switch prohibits calculating the C.V.for a peak in the histogram. This process obviates the need for the operator to remember which histograms were transformed and insures that a fallacious C.V.is not calculated. There are no restrictions as to the number of times the integral present on any one analogue channel can be used or the sequence in which the analogue channels can be used to generate histograms. These attributes are software-selectable and do not require hardware or cabling modifications. Four histograms representing any combination of four analogue channels can be collected and displayed. As a safety measure to protect against computer lock-up, a loop of user-defined time duration is included in the data-acquisition software. The length of time required to execute the loop under normal conditions is sufficient for new data to be present on the integrators. If the digital I/O line from the interface does not go high indicating new data are present, a data-received pulse is sent to the interface to reset the integrators. This routine operates until either valid data reappear at the inputs of the interface and collection resumes or the operator intervenes and manually terminates data collection. The same routine can also be used to optimize the flow cytometer to the computer
Microcomputer interface for flow cytometry
339
processor. As stated previously, microcomputers containing Intel 80X86 processors operate over the range of 6 to 33 MHz and, consequently, the time required for the execution of program instructions also varies. By increasing or decreasing the time prior to a forced reset, the operating characteristics of the processor can be ‘customized’ for most efficient data collection.
8.
Collections
The microcomputer-based flow cytometer data-collection system described here has been in daily use for over 3 years. The ease with which new operators have learned to use the system and the speed, accuracy and reproducibility of the system confirm the original premise that an 80X86-based microcomputer and commercially available A/D board together with a relatively simple interface can be easily assembled to provide a versatile, highly sensitive and cost-effective data-collection system for flow cytometry.
Notes The cost of components for the electronic interface described in this report is approximately $600. Complete working drawings for non-commercial construction of the electronic interface are available from J. A. Dvorak. Questions regarding software should be addressed to V. K. Dvorak.
References 1. H. M. Shapiro 1985. Practical Flow Cytometry. New York: Alan R. Liss, Inc., pp. 182-251. 2. Anon. 1987. Inters2 Component Data Catalog. Cupertino, California: Intersil Inc., pp. 8-109. 3. Anon. 1988.Fluorescent Microbeah Standards. Research Triangle Park, North Carolina: Flow Cytometry Standards Corp., p 14. 4. J. A. Dvorak & S. M. Banks 1988. Modified Box-Cox transform for modulating the dynamic range of flow cytometry data. Cytometry, 10, 8 1l-8 13. 5. Anon. 1976. Non-linear Circuits Handbook. Norwood, Massachusetts: Analog Devices, Inc., pp. 186-201. 6. M. R. Loken, D. Stout & L. A. Herzenberg 1979. Lymphoid-cell analysis and sorting. In Flow Cytometry and Sorting (M. R. Melamed, P. F. Mullaney & M. L. Mendelsohn, eds). New York: John Wiley and Sons, pp. 505528.
James A. Dvorak, PhD is a group-leader in the Biochemistry and Physiology Section of the Laboratory of Parasitic Diseases, National Institute of Allergy and Infectious Diseases, US National Institutes of Health, where he has worked for over 20 years. He specializes in the development and use of biophysical methods for studies of human pathogens.
340
J. A. Dvorak et al. Courtnev P. Mudd. PhD is a staff research en gineer in the Applied Clinical’Engineering Section of the Clinical Center, US National Institutes of Health. Prior to joining the Applied Clinical Engineering Section, he was a Commissioned Officer in the US Public Health Service. His main research interests are in the areas _ of. calorimetry, blood . flow, . pulmonary air flow, temperature control and measurement, and lowlevel signal processing.
Vojin K. Dvorak is an independent programmer specializing in highspeed scientific data collection and analysis. In addition to his development of software for flow cytometry, he has developed image processing, morphometry, and solid-modelling software for biomedical areas as diverse as electron microscopy and clinical surgery.
William H. Schuette is the Technical Director for Ship Electromagnetic Signatures at the David Taylor Research Center, Carderock, Maryland. His department measures and analyses ship electromagnetic signatures. Prior to his present position, he was the Chief of the Applied Clinical Engineering Section at the US National Institutes of Health where his research interests included video image analysis and flow cytometry.
Microcomputer
interface for flow cytometry
Appendix
SPECTRUM
ENTER
DRIVE
DISPLAY
Flow diagram
of the program
n
developed
C.V.
41 STATlSllCS
for flow cytometry
data collection
341
An electronic interface for microcomputer-based flow cytometry: design, operation and performance characteristics James A. Dvorak*, Courtney P. Muddt, Vojin K. Dvorak1 and William H. Schuette$ *Laboratory of Parasitic Diseases, National Institute of Allergy and Infectious Diseases; TApplied Clinical Engineering Section, Biomedical Engineering and Instrumentation Program, Division of Research Resources, National Institutes of Health, Bethesda, MD 20892; $6204 Singleton Place, Bethesda, MD 20817; and $Electromagnetic Signatures Department, David Taylor Research Center, Bethesda, MD 20084. USA
An inexpensive electronic interface for the acquisition of asynchronous flow cytometry data using a commercially available microcomputer and A/D converter is described. In the design of this interface, the major objectives were to minimize the amount of custom hardware necessary between the computer and flow cytometer and to maximize usable sensitivity and resolution by implementing a gated integrator and trigger hold-off approach to acquire the asynchronous data pulses from the cytometer. The major error sources which can occur during data acquisition are identified and their effects on system performance are shown. A simple protocol is described to minimize the effects of these errors on the acquired data. The influence of computer-processor clock speed on data acquisition rates is also documented.
1.
Introduction
Flow cytometry involves the collection, processing, storage, and analysis of asynchronous analogue signals generated by particles interacting with a light beam or electronic circuitry [l]. Although flow cytometers of various designs are available commercially, the electronics used to interface the cytometer per se, which generates the analogue signals, to the computer used for data processing have either not been well documented in the scientific literature, are complex and expensive, or have design aspects which could adversely influence the data being collected. In this report, the design, operation, and performance characteristics of a simple, inexpensive, but highly versatile and sensitive electronic system to interface a microcomputer with a flow cytometer for four-parameter asynchronous data collection and analysis are described. The major attributes of the electronic interface are described in sufficient detail to allow its construction and use in new flow cytometer designs or as a replacement interface for existing flow cytometers.
2.
Hardware requirements
It is assumed that the illumination, fluidics, optical, sensor, and signal preamplifier subsystems of the flow cytometer are functional and analogue signals are present at the output of the sensor preamplifiers. Minimum computer requirements include an MS DOS-compatible, Intel 80X86-based microcomputer with 640 kbytes of DRAM, an 321 0745-7138/91/040327+
15 $03.00/O
0 1991 Academic Press Limited
328
J. A. Dvorak et al.
80X87 numeric coprocessor,
floppy disc drive, an enhanced graphic adapter (EGA) or video graphic array (VGA) display, and a MetraByte Model DAS-8 or DAS-16 (MetraByte Corp., Taunton, MA) analogue-to-digital (A/D) converter card (or equivalent). An oscilloscope, which is normally present to align the optical and mechanical components of the flow cytometer, is used to adjust the electronic interface between the flow cytometer and the computer.
3.
Interface
design considerations
and objectives
The electronic interface contains analogue amplifier and integration circuits as well as digital control circuits. The electronic interface was designed to be compact, have a minimum of adjustments, low fabrication cost, ease of use and service, and the capability of being integrated into new systems or added to existing systems. To accomplish these objectives, many of the signal-processing tasks which are generally handled external to the computer were transferred to the microcomputer. The primary objective was to increase the useable sensitivity, repeatability, and resolution of the overall flow cytometer system. This objective took precedence over system throughput speed. However, with the proper selection of computer hardware, the complete system performs at throughput rates equivalent to commercial instrumentation. The analogue signals from the sensor preamplifiers contain the information concerning light scatter by the particle, fluorescence intensity of the particle, etc. As the timing of the particles passing through the laser beam is random or asynchronous, it is not possible to predict when the analogue pulses from the flow cytometer sensor preamplifiers will be present. Conversely, the microcomputer with its internal clock and A/D converter, is a synchronous device. The role of the electronic interface is to amplify, condition, and link these asynchronous or randomly occurring analogue pulses from the flow cytometer to the synchronously-based system in the microcomputer for conversion and storage. Two approaches can be used to acquire asynchronous analogue signals from a flow cytometer: (1) peak sense and hold of the analogue pulse; and (2) gated integration of the area under the analogue pulse. Using the peak sense and hold approach, the peak heights of the analogue pulses are measured and used to calculate the information concerning cell size, fluorescence amplitude, etc. However, various assumptions must be made concerning the relationship between the height of the pulse and its shape. In addition, a potentially serious drawback of this approach is its dependence upon particle flow rate. At high flow rates, the analogue amplifiers may not completely return to their initial conditions or baseline values before the occurrence of another pulse. If the amplifiers have not returned to baseline when a subsequent pulse occurs, the peak height will be the sum of the new analogue pulse height and the baseline shift or initial conditions left on the amplifiers from the previous pulse. Furthermore, noisy signals will create a high degree of uncertainty in the actual peak measurement leading to decreased resolution and a large coefficient of variation (i.e. the standard deviation divided by the mean; c.v.) of the peak. In order to avoid these problems, the gated integrator approach involving an analogue comparator was used to detect when a preselected analogue signal exceeds some userdefined threshold. The comparator ‘gates’ or turns on four independent analogue integrators which electronically integrate the areas under the analogue pulses. The integration time is set to be longer than the slowest analogue pulse expected. At the end
Microcomputer interface for flow cytometry
329
of the integration period, the integrators are turned off and hold their integrated values which are then read by the computer. When data conversion is complete, the integrators are reset to zero. The gated integrator approach has three distinct advantages over the peak sense and hold approach. First, since an actual measurement of the area under the pulse is made, no assumptions are necessary concerning the relationship between pulse height and shape. Second, integration is inherently a filtering process, so that the noise component in the actual analogue voltages converted into data by the computer is lower. And, third, after data conversion, the integrators are electronically reset to zero so that initial conditions are repeatable from measurement to measurement. One disadvantage of the gated integrator is that the throughput or measurement rate is slower since the entire analogue pulse must be measured and the integrators reset. Consequently, actual measurement times tend to be about two times longer than with the peak sense and hold approach. However, as one design objective was maximum sensitivity, gated integrators were used in the interface.
4.
Electronic
interface
description
The implementation of the gated integrator in the interface is depicted functionally in Fig. 1. The analogue portion of the interface contains four identical, adjustable-gain amplifiers and four identical gated integrating amplifiers. However, for clarity only the trigger channel is shown. The digital portion consists of the analogue comparator, flipflops to control the gating of the integrators and ‘handshaking’ with the computer, monostable multivibrators (one shots) to set the integration and reset periods for the integrators, and trigger hold-off logic to prevent the integrators from performing partial
Data received
?
Reset CO%?)
Q
?R +S
t----II
Data ready (FFII
Data ready
Q t+
I
I
I
I
bR ?S
Data received (FF2)
C_ 0
’
I
Trigger hold-off logic
Threshold
Trigger channel analogue
Offset
Non-trig. channel Trigger channel integral Trigger channel monitor
Figure 1. Block diagram of the major components of the interface. FFI, FF2 = R-S type flip-flops; OSl, OS2 = monostable multivibrators (one shots); Al = inverting amplifier; A2 = integrator; A3 = comparator; Sl, S2 = analogue switches; Cl = integrating capacitor.
330
.J. A. Dvorak et al.
Data received
One data
acquisition
cycle
_j
Reset
(02) Data (FFI)
ready
T2
.Y
Interface
control
Computer control
A
L-.-_ L
I
Data cleared (FF2) ;,aaple
Analogue
window
input
Integrator output Comparator output
I
L
L Time
in ps
Figure 2. Logic timing diagram for a typical data-acquisition cycle of the interface. Tl = Time between circuit enabling and actual acquisition of next analogue pulse; T2 = time required for A/D conversion and acquisition. The other abbreviations are as indicated for Fig. 1.
or incomplete integration of analogue pulses which may be present immediately after the reset of the integrators. The logic timing diagram for the interface, which uses two digital I/O lines present on the A/D converter card, is shown in Fig. 2 and, in conjunction with components identified in Fig. 1, depicts a typical data-acquisition cycle. At the onset of data acquisition, computer software instructs a data-received pulse to be sent to the interface to reset the integrators. The data-received pulse triggers the one-shot OS2 which generates a sufficiently long pulse (10 us) to completely reset the integrators to zero. At this point, the computer and interface operate independently. In addition, the interface is ‘armed’ and able to acquire data. As a particle enters the laser beam, the analogue signal from the user-selected trigger channel rises out of the noise and exceeds the threshold set by the operator on analogue comparator A3. The comparator changes state and sets flip-flop FF2 which triggers one-shot OSl. The output of OSl, the sample window, turns on the four gated integrating amplifiers which then integrate the four analogue pulses. The output pulse width of OS1 is set by the operator for an integration period of 10-35 us. This adjustment allows the operator to match the sample window to the analogue pulse. At the end of the sample window, S 1 is turned off, the integrators stop integrating, and hold their integrated values. Simultaneously, flip-flop FFl is set and sends a data-ready pulse to the computer signalling it to resume control and direct its internal A/D converter to read the outputs of the four integrators. The time, T2, required for these conversions is influenced not only by the conversion time of the A/D converter, but also the clock speed of the computer and amount of code which must be executed per cycle. Immediately after reading the A/D converter, computer software sends a data-received pulse to the
Microcomputer interface for flow cytometry
331
electronic interface causing the interface and computer to again operate independently. The interface resets the integrators clearing the previous data, detects the next analogue pulse used as the trigger, integrates the user-selected channels, holds the values, and sets the data-ready line. The computer processes and stores the data on the A/D converter and updates the real-time display. If the flow rate of particles is sufficiently high, the interface accomplishes its tasks in less time than is required for the computer to accomplish its tasks. Consequently, when the computer completes its processing and checks the data-ready line, new data will always be ready for conversion. Setting the actual measured data rate (conversions/s) involves increasing the particle flow rate at the cytometer until the percentage of unrecorded events exceeds an acceptable user-defined level. A unique feature of the interface is the inclusion of a trigger hold-off circuit to prevent the acquisition of pulses present in the system when the integrators are reset. After reading the voltages presented by the A/D converter, the computer sends a ‘datareceived’ pulse to OS2 to reset the integrators and start the cycle anew. Logic gates in the reset circuitry delay or hold-off the resetting of FF2 which ‘rearms’ the system to acquire a pulse if the comparator indicates that an analogue voltage above threshold is present at the time of reset. This feature prevents the system from partially integrating analogue pulses which may already be present when the reset is completed.
5. Error analysis interface
and optimization
of the electronic
In a flow cytometry data-collecting system, optical and/or electronic offset errors are present which lead to non-linear behaviour or poor resolution. A protocol utilizing an oscilloscope was developed for all system alignment functions. The horizontal amplifier of the oscilloscope is triggered by the rising edge of the sample window pulse. The signal to be adjusted is connected to a vertical channel of the oscilloscope. When data collection begins, the analogue and/or integrator signals appearing on the oscilloscope are used to optimize alignment of the optical and mechanical components of the flow cytometer. In addition, in conjunction with adjustments present on the electronic interface, they are used to minimize the effects of errors in the analogue signals. For the gated integrators used in this system, the output is given by = -(l/RC)J;e,,dt qouq = the measured output voltage, l/RC = the conversion constant of the integrator, ecin)= the input voltage, and r = time. As there are four analogue channels, any mismatch in the R and C values will produce variations in the measured ecout)even if all of the ecin)are the same. This mismatch in the integrator time constants arises from several sources. For example, precision resistors are readily available but precision capacitors are not. In addition, the ‘on’ resistance of the analogue switch, Sl, is part of the ‘R'value and for the DG201CJ switches used can vary from 100 to 125 ohms [2]. The effect of this variation could be minimized by making the resistor value large with respect to R(,,). For a given time constant, however, large values of R imply small values for C. If C is too small, the bias current drawn into the input of the op-amp A2 will reduce the charge on
where%“I)
332
J. A. Dvorak et al.
C and lower the value of ecout).Therefore, a 500-ohm trimpot in series with a 1.8-K ohm resistor was used to balance the four integrators. During initial calibration, a single test pulse is fed to all four integrators and the trimpots adjusted until all four outputs are the same. If all aspects of the interface are properly adjusted, oscilloscope traces and a histogram similar to Fig. 3(a) should result. The sample window triggers at the beginning of the analogue pulse indicating a properly set threshold. The initial and final integrator output slopes are zero indicating an absence of offset and sufficient sample window time for complete integration. However, interface adjustment errors can occur and a simple means of determining their presence and correcting them must be available. Major electronic sources of error in data collection including: (1) improperly set threshold; (2) improper sample window length; and (3) D.C. offsets present in the analogue inputs were identified and means were provided to correct them. The consequences of an improperly set threshold are shown in Fig. 3(b). Integration begins at some non-zero time value so that an integral from t, to t is obtained. Because a threshold detection scheme is used, it is impossible to set t, exactly to zero since that would assume a pulse could be detected while it is still in the noise level. This error is minimized by setting the threshold as close as possible to the noise level. Since the sample window is monitored in order to adjust the turn-off time t,, it is also used to set the threshold. If the threshold is too high, the sample window opens after the initial rise of the analogue pulse. As the threshold is lowered closer to the noise level, the leading edge of the sample window moves closer to the start of the analogue pulse. When the threshold is set too low, noise triggers the sample window and it loses synchronization with the analogue pulse and appears randomly on the oscilloscope screen. The use of an analogue delay line between the threshold detector and integrator could effect a ‘pre-trigger’ response facilitating a more robust threshold-detection scheme. However, with the signal-to-noise ratios commonly encountered in this system, the improvement in the integrated value produced by such a delay was calculated to be less than 1% which is significantly lower than the overall system noise for biological samples of 3-9%. Consequently, it was judged not to be a cost-effective feature to add to the interface. The consequences of an improperly set sample window length are similar to an improperly set threshold. As shown in equation (l), the output value e(outJis a valid measure of the integral of e(,,, only if t is sufficiently long to allow e(,,, to return to baseline before the integration is stopped. Therefore, it is necessary to monitor the sample window (output of OSl) triggered on the analogue signal ecinJtogether with ecin, and adjust the window to ensure that t is large enough to completely integrate e(,,,). If ecin)contains a D.C. offset, the integrator will integrate the offset as well as the analogue pulse. D.C. offset is not a function of time. Therefore, the output now consists of two terms, i.e. the desired signal and an error term. Since the D.C. offset can be positive or negative, the error also can be positive or negative. This error manifests itself in the form of offsets in the channel axis of the histograms [Fig. 3(c) and (d)]. To compensate for this error, D.C. offset nulling capability was added to all four analogue input adjustable-gain amplifiers. To correctly set this adjustment, the integrator outputs are monitored and adjusted for a zero slope on the integrator output at the beginning and end of the sample window period. The degree of repeatibility of the adjustable-gain amplifiers is dependent mainly upon
Microcomputer interface for flow cytometry
333
the amount of mechanical backlash present in the turns counter for R2. In this implementation, the A/D converter is configured to read analogue voltages in the 0 to + 10 V range resulting in a resolution of 244 mV. The 12-bit data are scaled to 8 bits for display, analysis and storage. With fluorescent beads, amplifier gain can be readjusted to repeatedly display a single-scaled 8-bit channel. The total combined error due to temperature drift in the amplifiers and gain resistors over a 10°C range together with the integrator output droop during A/D conversion is approximately 2.5 mV (1 bit of the 12bit A/D converter range). One of the reasons for choosing the gated integrator to acquire the signals is the ability to control the re-initialization or reset of the integrators to repeatable values. In using high speed, solid-state analogue switches to accomplish the gating, a small error introduced by these switches was discovered when the integrators were reset back to zero. During reset, the output of the integrators does not go to zero but to some value between 0 and 75 mV depending upon the initial conditions on the integrators at reset. A value of this magnitude could represent an offset of up to 30 channels (1Zbit range). This variable reset level was traced to a charge-coupled effect in the solid-state switches. When this charge-coupled effect was nulled out [2], the reset values on the integrators was f3mV.
6.
Performance
characteristics
As stated previously, one of the experimental objectives was to develop a system capable of a high degree of repeatability. To determine system gain repeatability, serial samples of fluorescence beads were assayed. During the first run, with the interface properly adjusted, the gain was set to centre the histogram on the channel axis and the gain setting recorded. The setting was then moved to a random value and subsequently reestablished with the gain value set apriori. The absolute difference between the runs was f 1 display channel (data not shown). The effect of the trigger hold-off circuitry is shown in Fig. 4. The experimental conditions were the same as described in the study of gain repeatability but in this case, for one of the two runs the trigger hold-off circuitry was disabled. When the circuit is disabled, if an analogue pulse is present when FF2 is reset, the integrators will immediately begin integrating the remainder of the pulse. When this situation occurs, the integrated value will always be less than the full value. These partial values tend to distort or skew the distribution toward lower channel numbers. The trigger hold-off circuitry prevents these partial integrations by delaying the reset of FF2 if the analogue comparator output is high, i.e. if an analogue pulse is present. As soon as the comparator goes low (analogue pulse is absent), FF2 is reset and the next pulse will be collected. With the trigger hold-off circuitry, particles could be assayed by the flow cytometer at a much higher rate without observing the ‘skewness’ shown in Fig. 4. The data collection rate and total number of particles collected were identical for both histograms. Although the interface can be used with any 80X86-based computer, the clock speed of the microcomputer is an important consideration because it directly influences the data collection rate. As shown in Fig. 5, at computer clock speeds from 8 to 20 MHz, there is a linear relationship between clock speed and the number of events/s which can be collected. This increase is due primarily to the inverse relationship between computer clock speed and the amount of time required for the computer to execute a fixed number
334
J. A. Dvorak et al.
of program instructions. It is important to emphasize that microprocessor clock speed affects only the speed at which data are collected and has no effect on the quality of the data. The data-collection rate is also influenced by the number of histograms collected, and the use of a real-time display as shown in Fig. 6. At 20 MHz, there is about a 20% improvement in collection speed when the real-time display is disabled reflecting the time required for display updating which is significant even for an assembly routine. The difference between using and disabling the real-time display becomes negligible as the (Q) IOOC 59
I 750
500
250 II7 1 178 L 5 E c
0
1
Ii
.
75c
500
64
128 Channel
number
192
256
( O167 1
3-
3-
251 3224 I
I-
z
c
z t
(d) 1000 17 1
750
5oc
25C
JL
137
A 1k
1
-
64
128 Channel
192
2 6
number
Figure 3. Oscilloscope traces and histogram of fluorescent beads (0+33*0.03 pm diameter, Cat. # 17153, Polysciences, Warrington, PA). On the oscilloscope traces the sample window is indicated by w, the normal analogue signal baseline by a double arrow, the analogue signal by a, and the integrated signal by i. (a) Properly adjusted electronic interface. Note the linear relationship between peaks of ‘singlet’ (59), ‘doublet’ (117) and ‘triplet’ (178) beads. (b) Improperly set threshold which appears as a ‘blank’ between the normal analogue signal baseline and the beginning of the analogue signal and as a non-zero slope in the integrator output. Note the decrease in amplitude of the ‘singlet’ peak and the non-linear relationship between the three peaks. (c). Positive 4-V D.C. offset present in the analogue signal appearing as an ‘upshift’ in the position of the analogue signal baseline, a non-linear slope at the beginning and end of the integrator output, and a large steady-state integrator output value. (d) Negative 1-V D.C. offset present in the analogue signal appearing as a ‘downshift’ in the position of the analogue signal baseline. The integrated signal has beginning and ending negative components resulting in a marked decrease in the amplitude of the ‘singlet’ peak and non-linearity between the three peaks.
336
J. A. Dvorak et al.
computer clock speed is decreased to 8 MHz irnplying that program execution speed has become the dominant variable. The linear increase in time required to collect an increasing number of histograms reflects additive conversion times of a multiplexing A/D converter. Only a single A/D converter is present on the A/D converter card; consecutive readings which require about 12 us each are accomplished through a multiplexing protocol on the A/D board. As the A/D conversions are handled serially,
\
:
0
64
Peak=162 Cv. = 1.96%
-Peak=160 cv =3.83%
128 Channel
192
256
number
Figure 4. Graphic representation of the effect of a trigger hold-off circuit on collected data. The sample is as described in Fig. 3. The histogram represented by the dotted line contains a low amplitude ‘tail’ resulting from partially integrated analogue pulses which were present when the integrator was reset. The histogram represented by the solid line was collected under identical conditions except that the trigger hold-off circuit was enabled. Note the symmetric shape of the histogram. The data-collection rate and the total number of particles collected were identical for both histograms. - w/Trigger hold-off, w/o trigger hold-OF, collection rate = 2000 s-r; n = 10,000 events.
IO Computer
15 clock
speed
(MHz)
Figure 5. Graphic representation of the linear relationship between the clock speed of the microcomputer processor and the number of events which can be collected.
Microcomputer interface for flow cytometry
337
MHz 20 I 1 16 1 IO 16
2
3
Number of channels coiiected
Figure 6. Graphic representation of the influence of both real-time data display and the number of channels collected on data collection rate at various microcomputer processor clock speeds (circles = 20 MHz, triangles = 16 MHz, squares = 10 MHz, inverted triangles = 8 MHz). At each clock speed (shown on the right ordinate) the open symbols represent the number of events acquired/channel (shown on the left ordinate) with the real-time display disabled. The filled symbols represent the number of events acquired/channel with the real-time display enabled.
A/D conversion time is the sum of individual A/D conversions. Although this might be considered a limitation of the system, that is not the case. The system exhibits a ‘dead time’ range of 50 to 100 ps which is similar to commercially available systems. Consequently, it is easily capable of collecting data at rates generally considered optimal in flow cytometry [3]. Although it might appear that throughput efficiency could be significantly improved by increasing the speed of the A/D converter, this is not the case. Post-acquisition software procedures are the real time-consuming aspects of the data-acquisition cycle. Therefore, increasing the A/D data-conversion speed has a negligible impact on the data-acquisition rate. In fact, the added program code often required to operate commercially-available high-speed A/D converter boards cancels out the benefits of a high-speed A/D converter in this application. However, it has a marked impact upon overall system cost. The A/D converter used in this system can be obtained commercially for under $400 (DAM) or $1000 (DAS-16) whereas higher-speed A/D converters average about $3,000.
the total
7.
Data collection
software
Although commercially-available data-collection programs are available which could be used to operate the electronic interface and A/D converter, custom data-collection and analysis programs were developed which contain all of the routines commonly available to flow cytometer systems. The programs are written in Pascal with time-sensitive portions of the code (e.g. the procedures to read and process data from the A/D converter, and real-time display of histogram development during data collection)
338
J. A. Dvorak et al.
written in assembly. The code segment of the data-collection program occupies about 27 kbytes of memory. A flow diagram summarizing the data-collection program is shown in the Appendix. The program is divided into subroutines which can be accessed by a single key stroke from the main menu. Once the program is instructed to collect data, it monitors the status of the data-ready line from the electronic interface. When the data-ready line goes high, indicating valid data are present at the outputs of the integrators, the program scans the A/D converter channels in the sequence specified by the operator, scales the 12bit data values to g-bits for display, stores the g-bit data in memory, and updates the real-time display on the monitor. Data are stored in DRAM as a series of 32-kbyte blocks consisting of four g-bit fields. Each field contains the channel number of an event in the corresponding histogram. Each block is identified by a 32-bit pointer stored in a sequential array. About 150,000 four-parameter events can be stored in DRAM. Data are stored on disc as a binary file consisting of a direct memory map of the 32-kbyte blocks. A second file, written in ASCII, with the same name but a different extension, containing the number of histograms, number of counts, identification of any mathematical transforms performed on the histograms, labels and comments is also stored on disc at the same time. This twofile system eliminates the problems associated with header blocks when converting or importing the data to other programs. One unique aspect of the data-collection program is that many functions which normally require hardware are implemented in software, resulting in substantial cost savings as well as increased reliability and stability. For example, the software can perform an exponential transform of the analogue values making up a histogram [4] and display the results of the transform in real time. This transform simulates an infinite series of non-linear amplifiers [5] and obviates the need for and the restrictions of logarithmic and exponential amplifiers. In addition, it is possible to minimize the overlap between any two analogue signals without additional electronics. The process is done in real time using previously described algorithms [6]. The ability to calculate the C.V. of the peak is provided in the collection program. However, if a histogram has been transformed in any way, a software switch prohibits calculating the C.V.for a peak in the histogram. This process obviates the need for the operator to remember which histograms were transformed and insures that a fallacious C.V.is not calculated. There are no restrictions as to the number of times the integral present on any one analogue channel can be used or the sequence in which the analogue channels can be used to generate histograms. These attributes are software-selectable and do not require hardware or cabling modifications. Four histograms representing any combination of four analogue channels can be collected and displayed. As a safety measure to protect against computer lock-up, a loop of user-defined time duration is included in the data-acquisition software. The length of time required to execute the loop under normal conditions is sufficient for new data to be present on the integrators. If the digital I/O line from the interface does not go high indicating new data are present, a data-received pulse is sent to the interface to reset the integrators. This routine operates until either valid data reappear at the inputs of the interface and collection resumes or the operator intervenes and manually terminates data collection. The same routine can also be used to optimize the flow cytometer to the computer
Microcomputer interface for flow cytometry
339
processor. As stated previously, microcomputers containing Intel 80X86 processors operate over the range of 6 to 33 MHz and, consequently, the time required for the execution of program instructions also varies. By increasing or decreasing the time prior to a forced reset, the operating characteristics of the processor can be ‘customized’ for most efficient data collection.
8.
Collections
The microcomputer-based flow cytometer data-collection system described here has been in daily use for over 3 years. The ease with which new operators have learned to use the system and the speed, accuracy and reproducibility of the system confirm the original premise that an 80X86-based microcomputer and commercially available A/D board together with a relatively simple interface can be easily assembled to provide a versatile, highly sensitive and cost-effective data-collection system for flow cytometry.
Notes The cost of components for the electronic interface described in this report is approximately $600. Complete working drawings for non-commercial construction of the electronic interface are available from J. A. Dvorak. Questions regarding software should be addressed to V. K. Dvorak.
References 1. H. M. Shapiro 1985. Practical Flow Cytometry. New York: Alan R. Liss, Inc., pp. 182-251. 2. Anon. 1987. Inters2 Component Data Catalog. Cupertino, California: Intersil Inc., pp. 8-109. 3. Anon. 1988.Fluorescent Microbeah Standards. Research Triangle Park, North Carolina: Flow Cytometry Standards Corp., p 14. 4. J. A. Dvorak & S. M. Banks 1988. Modified Box-Cox transform for modulating the dynamic range of flow cytometry data. Cytometry, 10, 8 1l-8 13. 5. Anon. 1976. Non-linear Circuits Handbook. Norwood, Massachusetts: Analog Devices, Inc., pp. 186-201. 6. M. R. Loken, D. Stout & L. A. Herzenberg 1979. Lymphoid-cell analysis and sorting. In Flow Cytometry and Sorting (M. R. Melamed, P. F. Mullaney & M. L. Mendelsohn, eds). New York: John Wiley and Sons, pp. 505528.
James A. Dvorak, PhD is a group-leader in the Biochemistry and Physiology Section of the Laboratory of Parasitic Diseases, National Institute of Allergy and Infectious Diseases, US National Institutes of Health, where he has worked for over 20 years. He specializes in the development and use of biophysical methods for studies of human pathogens.
340
J. A. Dvorak et al. Courtnev P. Mudd. PhD is a staff research en gineer in the Applied Clinical’Engineering Section of the Clinical Center, US National Institutes of Health. Prior to joining the Applied Clinical Engineering Section, he was a Commissioned Officer in the US Public Health Service. His main research interests are in the areas _ of. calorimetry, blood . flow, . pulmonary air flow, temperature control and measurement, and lowlevel signal processing.
Vojin K. Dvorak is an independent programmer specializing in highspeed scientific data collection and analysis. In addition to his development of software for flow cytometry, he has developed image processing, morphometry, and solid-modelling software for biomedical areas as diverse as electron microscopy and clinical surgery.
William H. Schuette is the Technical Director for Ship Electromagnetic Signatures at the David Taylor Research Center, Carderock, Maryland. His department measures and analyses ship electromagnetic signatures. Prior to his present position, he was the Chief of the Applied Clinical Engineering Section at the US National Institutes of Health where his research interests included video image analysis and flow cytometry.
Microcomputer
interface for flow cytometry
Appendix
SPECTRUM
ENTER
DRIVE
DISPLAY
Flow diagram
of the program
n
developed
C.V.
41 STATlSllCS
for flow cytometry
data collection
341