An enhanced reverse blocking MMC with DC fault handling capability for HVDC applications

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An enhanced reverse blocking MMC with DC fault handling capability for HVDC applications Xiaofeng Yang a,∗ , Yao Xue a , Bowei Chen a , Zhiqin Lin a , Yajie Mu a , Trillion Q. Zheng a , Seiki Igarashi b , Yan Li c a

School of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China Fuji Electric Co., Ltd., Tokyo 141-0032, Japan c China Electric Power Research Institute, Beijing 100192, China b

a r t i c l e

i n f o

Article history: Received 28 July 2016 Received in revised form 20 July 2017 Accepted 31 August 2017 Available online xxx Keywords: HVDC transmission Modular multilevel converter (MMC) Reverse blocking DC fault handling Submodule (SM)

a b s t r a c t This paper presents an enhanced reverse blocking modular multilevel converter (ERBMMC) topology, which features with reverse blocking IGBT based submodules (RBSMs) and current limit modules (CLMs), in order to improve the DC fault handling capability for HVDC applications. Based on analysis of the configuration and fundamental operation principles, the DC pole-to-pole fault has been taken into consideration for further studying the DC fault handling mechanism and the key components parameter selection guideline of ERBMMC. To validate the feasibilities and effectiveness of proposed topology and fault theory, extensive simulation results are demonstrated. It is concluded that ERBMMC is able to effectively extinguish the fault current arc under DC fault condition. In addition, CLMs plays an important role in further accelerating fault current attenuation. What is more, ERBMMC adopts the original control and modulation strategies under the normal operation condition, thus it further reduces the complicity of industry design. © 2017 Elsevier B.V. All rights reserved.

1. Introduction With the ever-increasing energy demand and common concerns for environmental problems, renewable energy source is considered as an effective alternative to traditional fossil fuels. The next-generation electric power system, known as the smart grid [1–3] and/or energy internet (EI) [4,5], will shift from over reliance on fossil energy to various low carbon renewable energy resources, such as solar and wind power [6]. However, such renewable energy usually scatters far away from the center of power consumers. As the cost-effective long-distance energy transportation system, voltage source converter (VSC) based high voltage direct current (HVDC) systems is one of the feasible solutions for integrating the large-scale renewable energy into the existing grids [7]. Some key issues, especially scalability, modular construction, redundant operation ability and fault management behavior, must be taken into account for industrial implementation [8,9]. Therefore, a variety of multilevel converter topologies has been investigated for improving the voltage levels and system capacity

∗ Corresponding author. Fax: +86 10 51684029. E-mail addresses: [email protected], [email protected] (X. Yang).

of the VSCs [10,11]. Among different topologies, the most promising concept regarding modular multilevel converter (MMC) has emerged as a breakthrough technology for HVDC transmission system in which the DC link voltage is in the range of a few hundred kilovolts [12–14]. Compared with the traditional multilevel converters, MMC shows inherent salient features such as high modularity, better harmonic spectra, lower switching frequency, very high efficiency, and significantly reduced filtering components size, etc. In last decade, MMC was attracting the interest of both academia and industry [15–20]. There are several successful commercialized MMC-HVDC projects, which includes the Trans Bay Cable Project by Siemens, Nanhui project by China EPRI, Nan’ao three-terminal MMC-HVDC project by China Southern Power Grid, Zhoushan five-terminal MMC-HVDC project by State Grid of China, and Xiamen bipolar MMC-HVDC project, etc. [21] However, due to the high maintenance cost at the long-distance HVDC transmission system, reliability has become one of the most important challenges for MMCs [22,23]. So it is obviously vital to limit the fault currents for protecting MMCs from serious short circuit faults. Unfortunately, the classical half bridge submodule (HBSM) based MMCs would be destroyed if no proper protection scheme is employed, even if the semiconductor devices are turned off timely [24]. Therefore several protection schemes have been

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2

UDC 2

SMa1

SMb1

SMc1

SMa2

SMb2

SMc2 +

SMan

SMbn

SMcn

LMPa

LMPb

LMPc

La

iPa

b iNa

DCN

La

iPc

La

iNb

La

c iNc

LMNa

LMNb

LMNc

SMa(n+1)

SMb(n+1)

SMc(n+1)

SMa(n+2)

SMb(n+2)

SMc(n+2)

SMa(2n)

SMb(2n)

SMc(2n)

Rlim

TL2

CLM La

a

O

UDC 2

iPb

- TL1

Usa

isa

Ls

isb

Ls Usb

isc

Ls

Usc

La

iSM X1 + USM R - sr X2

T1

D1

Cs

+

TsT2

UC

CSM T3

RBSM

Fig. 1. ERBMMC configuration with current limiter module.

proposed to deal with the DC link short circuit faults, which has been accepted in some existing MMC-HVDC transmission projects [25]. It is common practice to parallel-connected thyristors across the AC port of MMC submodule (SM) [26,27]. Since the freewheeling diodes cannot withstand high inrush current, MMC will be blocked soon once a fault occurs, then short circuit current would be bypassed through the triggered thyristors to protect the freewheeling diodes during DC link faults. However, the short circuit fault current cannot be extinguished naturally due to the diode freewheeling effects [28]. The utilization of solid-state HVDC circuit breaker (HVDC-CB) is seemed as one of the better solutions for fault ride-through protection of MMC-HVDC system. But since there is no natural current zero crossing in DC systems, the availability of HVDC-CB with high voltage large current is limited because of its immaturity and high cost [29,30]. Another alternative approach is adopting the modified MMC topologies with DC faults handling capability, which includes full bridge submodule (FBSM), clamp double submodule (CDSM) and hybrid MMC (HMMC). A considerable amount of studies have been carried out on this topic [28,31]. Different from HBSM-MMC, the FBSM-MMC can cut off fault current in any direction by blocking all the IGBTs. But under the same voltage levels, the number of power devices required in FBSM-MMC is twice compared with HBSM-MMC, this resulting in extra power loss and high initial investment [27]. CDSM-MMC is able to extinguish the DC arc inherently by blocking the IGBTs. Furthermore, CDSM represents an exact equivalent of two HBSMs in normal operation and can reduce the number of power devices compared with the FBSM. However, CDSM shows different connection forms during normal operation and fault blocking period, which means a certain degree of coupling in structure, thus increasing the control complexity [32]. Qin and Ilves etc. proposed a simplified FBSM topology with the name of unipolar full bridge submodule (UFBSM)

for further reducing IGBT device purpose [33,34]. Besides the efforts on various submodule circuits, the hybrid MMC topologies, which consists of the HBSMs and the abovementioned fault ride-through submodules, were proposed and studied for reducing the total amount of power devices [35,36]. But HMMCs also use the FBSMs or CDSMs to limit DC link fault current, and voltage balance becomes relatively complex compared with HBSM-MMC. Reverse blocking IGBTs has symmetrical blocking voltage characteristic, and it is especially suitable for multilevel converter with low switching frequency application [37]. In order to improve the DC fault handling capability, this paper presents an enhanced reverse blocking MMC (ERBMMC) topology, which consists of the improved reverse blocking IGBT based half-bridge submodules (RBSMs) and the current limit modules (CLMs). Fundamental operation principles and detailed fault handling mechanism are all within the scope of study. This paper is organized as follows. Section 2 presents and analyzes the structural characteristics and operation principles of ERBMMC topology. In Section 3, the fault current handling mechanism together with key components parameter design considerations are discussed in detail. To validate the feasibilities and effectiveness of proposed topology and theory, extensive simulation results are demonstrated in Section 4. Finally, Section 5 reports the main conclusions. 2. Basic operation principles of the ERBMMC 2.1. Topologies analysis Fig. 1 illustrates a general circuit configuration of the threephase ERBMMC topology, which is comprised of three-phase legs and each leg contains a stack of 2n identical SMs, two CLMs and two leg inductors (La ). The modular structure provides the flexi-

Please cite this article in press as: X. Yang, et al., An enhanced reverse blocking MMC with DC fault handling capability for HVDC applications, Electr. Power Syst. Res. (2017), http://dx.doi.org/10.1016/j.epsr.2017.08.040

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- TL1

TL2

Rlim

- TL1

iNj = iCj −

SM

+

+

+

TL2

Rlim

- TL1

TL2

R

bility to scale the power and voltage levels by adding more SMs. For the convenience of discussion, each phase leg is further divided into the upper arm and lower arm. Different from the conventional HBSMs, the RBSMs and CLMs are employed as the basic building blocks of ERBMMC. Shown as Fig. 1, two anti-paralleled RB-IGBTs (T2 and T3 ) are used as the lower switches of RBSM. And a bypass circuit, consisting of auxiliary thyristor Ts , auxiliary capacitor Cs and varistor Rsr , is parallel connected with the RB-IGBTs. In normal operation, T2 and T1 operate with complementary switching states, while T3 is triggered all the time and plays the role of free-wheeling diode during normal operation. Therefore, the control techniques including modulation and voltage balancing adopted for ERBMMC can be directly transplanted from the conventional HBSM-MMCs. Taking into account for accelerating the fault current attenuation, the addition of CLMs is another prominent feature of the proposed ERBMMC topology. Note that the current limiting resistor Rlim is parallel connected with two anti-paralleled RB-IGBTs (TL1 and TL2 ). In normal operation, both TL1 and TL2 are triggered all the time and the current path is shown as Fig. 2(a) and (b). Thus Rlim is bypassed all the time in normal operation mode. Once fault current is detected, both the RBSMs and CLMs enter fault protection mode by blocking the control signals of IGBTs (T1 , T2 , T3 , TL1 and TL2 ). Then the fault current starts to charge Cs through Ts and Rlim , while Rsr is designed to prevent the possible overvoltage shoots across Cs , thus it further avoids the potential damage of the main switching devices. Generally, Rsr is not activated until the voltage of Cs exceeds its threshold value. So the function of Rsr will not be considered in the following for simplifying the analysis, but this does not affect the correctness of the theory. The auxiliary capacitor merely causes a slight increase in cost while no extra loss during normal operation. The switching states of RBSMs and CLMs are listed in Table 1. UC is the capacitor voltage of CSM and Uclamp is the clamp voltage across T2 and T3 .

(2)

1 IDC + iZj 3

iCj =

Fig. 2. Current path of CLMs: (a) normal operation iSM > 0; (b) normal operation iSM < 0; (c) fault blocking operation.

1 i 2 sj

3

(3)

where the arm currents iPj and iNj , flowing through both the upper and lower arms, consist of half the AC output current isj and the common-mode current iCj , which is composed of the DC component IDC /3 and the circulating component iZj . The former one refers to the active power for charging and discharging the RBSMs capacitors; while the latter one indicates the reactive power which results in the RBSMs capacitors voltage ripples. The output voltage of each RBSM equals to its capacitor voltage UC,jk when the RBSM is activated, or zero when it is deactivated. Here, number k is from 1 to 2n. The output voltage waveforms at the AC side of ERBMMC are synthesized by employing multiple modulation techniques. Thus the resulting AC and DC voltages can be determined by uPj =

diPj UDC − uj − La 2 dt

(4)

uNj =

diNj UDC + uj − La 2 dt

(5)

uj =

uNj − uPj 2

−

La dij 2 dt

UDC = uPj + uNj + 2La

(6)

diCj dt

(7)

where uj is the AC output voltage, UDC is the rated DC link voltage. uPj and uNj denote the upper and lower arm voltages, respectively, which are also expressed as uPj =

n 

USM,jk

(8)

k=1

uNj =

2n 

USM,jk

(9)

k=n+1

Under DC pole-to-pole short circuit fault condition, UDC will drop to zero if ERBMMC operates according to the abovementioned rules before system blocking. Then activated RBSMs capacitors will be continuously discharged in series, which generated the short circuit current. This will directly lead to the capacitors overdischarged for that no active power exchange works in ERBMMC.

2.2. Operation principles of ERBMMC

3. DC fault handling mechanisms analysis

Considering the operation principles of three phases identical, taking phase-j (j = a, b, c) as an example to carry out the analysis. Analysis conclusions also apply to three-phase conditions. The analysis is under the following assumptions:

ERBMMC uses the floating capacitor technology rather than concentrated capacitor structure, which helps to suppress the fault discharge current if DC link fault occurs in the ERBMMC-HVDC system. However, the DC fault current generally comprises the discharge currents of the switched RBSMs capacitors as well as the AC networks contribution. It requires to take reasonable means for improving the DC fault handling capability of ERBMMC. Typical DC link faults includes pole-to-pole fault, pole-to-ground fault and broken-line fault. The DC pole-to-pole fault is regarded as one of the most representative and serious fault types. Therefore, this scenario is selected for the DC fault handling mechanism theory analysis. Once DC pole-to-pole fault occurs, the DC link voltage collapses to zero and a large inrush current would be generated. Then ERBMMC will enter RBSMs discharging stage immediately until the system blocking is enabled, which is similar as the conventional MMC equivalent model as presented in Ref. [38]. This paper thus avoids its detailed explanation and focus on the DC fault handling mechanism analysis of ERBMMC after system blocking.

1) Three-phase AC voltages and currents are pure sinusoidal and symmetrical. 2) AC output current isj is distributed equally between the upper and the lower arm. 3) Ignoring the switching losses of the power devices. These conditions are not necessary for ERBMMC but they are generally fulfilled with good approximation. The AC terminals of ERBMMC are connected to the AC gird Usj through Ls . According to the reference direction shown in Fig. 1, the output currents of ERBMMC in normal operation mode are expressed as iPj = iCj +

1 i 2 sj

(1)

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4 Table 1 Switching states of RBSM and CLM. Operation modes

Operation states

Normal operation

Discharging Charging Bypass Blocking Blocking Charging

Fault protection System starting

T1 X1+ USM X2

D1

Cs

UC

CSM

+

Ts T2

RBSM

T3

T2

T3

Ts

TL1

TL2

1 0 0 0 0 0/1

0 0 1 0 0 0/1

1 1 1 0 0 0/1

1 1 1 1 1 0

1 1 1 0 0 0/1

1 1 1 0 0 0/1

T1 X1+

Cs +Ucs

USM - Ts X2

CLM

T1

T2

D1

UC

if (0+ )

= if (0− )

= I0

where I0 is the initial fault current of blocking stage, Rf is the short circuit point resistance, Rk and Lk are the equivalent resistance and inductance distributed on the transmission cables between the fault point and ERBMMC. According to Kirchhoff’s voltage law (KVL), the following differential equation is deduced Req ducs 1 d2 ucs + ucs = 0 + Leq Cseq Leq dt dt

Under blocking stage, the fault current starts to charge the auxiliary capacitors Cs through Ts and Rlim . Then the equivalent leg auxiliary capacitors voltage increases quickly for providing the inverse voltage uinv = 2n × Ucs , which helps to extinguish the fault current. Fig. 4(b) depicts the simplified equivalent circuit of such case. the second-order oscillation discharging circuit is reconstructed with the equivalent series resistance Req , equivalent inductance Leq and equivalent leg auxiliary capacitance Cseq , which is regarded as a series of 2n auxiliary capacitor Cs for each leg. The initial condition and circuit parameters are predefined as =0

(12)

Cseq = 3Cs /2n

T3

(10)

= ucs (01 −)

UC UC 0 UC Uclamp –

2

The possible current paths of RBSMs and CLMs after all IGBTs are blocked are shown as Figs. 3 and 2 (c) respectively. When current is positive as shown in Fig. 3(a), RBSM capacitor is charged through the anti-paralleled diode D1 and the fault current is limited because the RBSM capacitor voltage UC is used to provide the inverse voltage so that leads to the diodes reverse cutoff. Otherwise, RBSM is bypassed as shown in Fig. 3(b) when iSM < 0. The bypass circuit goes to work and Cs is charged by the fault current through Ts . Cs is generally very small compared with the CSM . Thus Ucs will increase quickly for providing sufficient reverse voltage to block the fault current and cut off the arc path at the fault point. It should be noted that Rlim plays a significant role in accelerating the fault current attenuation during the blocking stage. Without considering the system redundancy, it is assumed that the 2n numbers of RBSMs are series-connected in each phase leg for simplifying analysis. As noticed from the above analysis, after trigger pulse of all IGBTs are disabled under blocking stage, the current path of ERBMMC is illustrated as Fig. 4. In such case, both the auxiliary capacitors Cs and current limiting resistors Rlim are involved in fault current attenuation process. Assuming the auxiliary capacitor voltages are equal for simplified purpose, the equivalent capacitor of both the upper and lower arms are expressed as

ucs (0+ )

<0 >0 – >0 <0 >0

Leq = La + Lk ⎪ 3 ⎪ ⎪ ⎩

CSM

3.1. DC fault handling mechanism



USM

⎧ 2 ⎪ Req = Rlim + Rf + Rk ⎪ ⎪ 3 ⎨

Fig. 3. Current path of RBSMs under blocking stage. (a) iSM > 0; (b) iSM < 0.

C seq1 = C seq2 = C S /n

iSM

(11)

(13)

Submitting the initial conditions, the charging current and voltage of the equivalent leg auxiliary capacitors Cseq are expressed as

 ω0 I0 sin ωt − ˇ ω

(14)

2nI0 sin(ωt) 3ωCs

(15)

t

if = −e−  t

ucs = e− 

where  is the fault current decay time constant, ω0 and ω are the natural angular frequency and system angular frequency, respectively. ˇ is the initial current phase angle. All these four variables are defined as

⎧ ⎪  ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ω ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ω0 ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ˇ ⎪ ⎪ ⎩

=

4La + 6Lk 2Rlim + 3Rf + 3Rk

=

2n − (2La + 3Lk ) Cs

= =



2Rlim + 3Rf + 3Rk 4La + 6Lk

(16)

2n (2La + 3Lk ) Cs



arctan



2

8n (2La + 3Lk )

Cs 2Rlim + 3Rf + 3Rk

−1 2

3.2. Parameter consideration of ERBMMC Eqs. (14) and (15) indicate that the fault current if value is affected directly by the initial fault current I0 as well as the equivalent resistance Req and the auxiliary capacitance Cs . Fig. 5 reveals the relationship between fault current with the system equivalent resistor and the auxiliary capacitors. Both the auxiliary capacitor Cs and equivalent resistance, especially Rlim , are involved in fault current attenuation process. In addition, it should be noted that Req plays an important role in accelerating the fault current attenuation during the fault blocking stage. Because the auxiliary capacitors are charged in series by the inrush fault current during the blocking stage. Then auxiliary capacitor voltage reaches its peak value as the current decays to zero.

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Fig. 4. Current path of ERBMMC under blocking stage. (a) Charging loop; (b) simplified equivalent circuit.

Fig. 5. Fault current curves: (a) fault current vs. Req ; (b) fault current vs. Cs .

According to (15), the peak blocking voltage across T2 and T3 is expressed as (17) ˇ

Uclamp = ucs, peak = e− ω

2nI0 sin ˇ 3ωCs

(17)

The voltage stress across Cs is illustrated as Fig. 6. It shows that the clamping voltage is related to the auxiliary capacitance Cs , equivalent resistance Req and equivalent inductance Leq . The larger inductance value means more inductive energy will be transformed to the electric field energy, which inevitably results in higher capacitor voltage. Moreover, the smaller auxiliary capacitance, equivalent resistance Req and large initial fault current I0 , the greater auxiliary capacitor voltage. Therefore, Cs value is determined by two specific parameters, i.e. the voltage limit for IGBTs (UT,max ) and the optimized blocking voltage (Ucs, min ). The latter one helps for eliminating the AC feeding energy path. Therefore, Cs should meet Ucs,min ≤ ucs,peak ≤ UT,max

(18)

3.3. AC feeding phenomenon Except the abovementioned DC fault current path, there is still possible existing AC feeding path along which the AC-side current contribution into the DC fault. The AC feeding paths are generally created by forcing the fault current flow among different phase legs. To simplify the analysis, the analysis hereinafter taking phase-a and phase-b for example. After system blocking enabled, the fault

current starts to charge the auxiliary capacitor Cs of each phase leg, which generates the so called inverse voltage uinv . If uinv is less than the AC line-to-line voltage ULm , the AC-side energy will also involve in Cs charging, the corresponding AC feeding loop is illustrated in Fig. 7. It should be noted that the new AC feeding current path is formed with 2n number of bypass modules in series between the upper arm of phase-a and the lower arm of phase-b respectively. Together with the DC charging loop shown as Fig. 4, the AC feeding loop helps to establish enough inverse blocking voltage. The existence of AC feeding current loop introduces extra DC link current, which may be harmful for the DC breaker arc extinguishing process. Thus, it is reasonable to avoid such a situation for further improving the system reliability.

3.4. Fault management The operation stages are monitored all the time. Both DC link voltage and currents are sent back to the central control system, and then DC fault state is judged by comparing them with their threshold values. Fig. 8 shows the DC fault protection process of the ERBMMC system. Setting the DC protection action threshold of DC current is Ith,sc , which is generally set to be two or three times the size of rated DC link current. If IDC < Ith,sc , ERBMMC works under normal operation condition. While IDC > Ith,sc , it indicates the abnormal DC link current incensement because short circuit fault occurs in DC line,

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Fig. 6. Voltage stress curve of bypass circuit: (a) voltage vs. Cs and Leq ; (b) voltage vs. Cs and Req .

Table 2 Simulation parameters of ERBMMC system.

Fig. 7. AC feeding phenomenon of ERBMMC under blocking stage.

Normal operation mode Determining whether DC fault occur DC Fault occur˛ No IDC>Ith,sc Yes Blocking all IGBTs and starting bypass switches (fault protection mode) Determining whether fault current is arc extinguished Arc distinguished˛ No IDC
DC fault occur˛ IDC>Ith,sc Yes AC breaker tripped The system completely outage Fig. 8. Specific flowchart of DC fault protection.

System parameters

Value

AC line-to-line voltage DC link voltage RBSM capacitor voltage RBSM capacitance Leg inductance Short circuit resistance (Rf ) Auxiliary capacitance (Cs ) Cable distribution inductance (Lk ) Cable distribution resistance (Rk )

7.2 kV 16.0 kV 2.0 kV 8.2 mF 3.5 mH 5.0 m 0.15 ␮F 1.0 mH 0.15 

then the system will immediately block all the trigger pulses for the ERBMMC to enter the fault blocking stage to clear the fault current. In addition, setting the protection returning threshold current as Ith,1 in fault protection mode. Generally, Ith,1 is set to be a little greater than zero. If IDC > Ith,1 , it indicates that the DC fault current if is not completely cleared and ERBMMC still maintained in fault protection mode. While if IDC < Ith,1 , it means the fault current arc has been extinguished. As for the nonpermanent DC link short circuit fault, it is expected that the insulation on the short circuit point should be restored and then restart the power transmission as soon as possible. So the IGBTs will be triggered for testing which type fault happens. If the fault is cleared then, the nonpermanent fault is identified, which is followed with unblocking all the IGBTs, the ERBMMC will be restarted. But if the permanent fault is identified, both the AC breakers and DC breakers are tripped to achieve fault isolation after fault clearance. Moreover, the fault clearance time during the protection is generally very short (may less than 1 ms), which can protect the main power devices from the thermal overstress.

4. Verifications of ERBMMC To verify the feasibility of the proposed ERBMMC and the fault handling theory, a full switched simulation model has been performed under Matlab/Simulink environment. The modulation method adopted in this simulation is the carrier phase-shifted sinusoidal pulse width modulation methods. Table 2 summarizes the simulation parameters of ERBMMC system. Since this paper mainly concerns the DC fault handling capability of the proposed topology, simulation results of a nine-level ERBMMC are enough for improving the simulation efficiency. It should be noted that although the selected model capacity parameters are small, the results obtained from this model will also be applicable to high power ERBMMC-HVDC system with arbitrary levels.

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3.0 2,3

20 15 10 5 0 -5 0.16

2.0 1.0 0

0.18

0.20 Time (s)

0.22

0.

-1.0 0.16

0.18

0.20 Time (s) (a)

0.22

0.

0.18

0.20 Time (s)

0.22

0.

(a) 0.8 0.6 0.4 0.2 0 -0.20.16

7

2.4 2.2 2.0 1.8 0.18

0.20 Time (s) (b)

0.22

8

0.

Usa Usb Usc

4 0

1.6 0.16

Fig. 10. Simulation results of RBSMs: (a) voltage stress of T2 andT3 ; (b) RBSM capacitor voltages of phase-a.

-4 -8 0.16

0.18

0.20 Time (s)

0.22

0.

(c) 0.8

isa isb isc

0.4 0 -0.4 -0.8 0.16

0.18

0.20 Time (s)

0.22

0.

Fig. 9. Simulation results of ERBMMC DC-side and AC-side performance: (a) DC link voltage; (b) fault current; (c) grid voltages; (d) grid currents.

as the reasonable blocking measures are timely, the grid input currents reduce quickly to zero while the grid voltages have not been significantly affected. Then the AC power transmission will be interrupted once DC fault occurs. It also shows that the short circuit fault energy mainly comes from the DC fault loop shown as Fig. 4 rather than the AC feeding loop of Fig. 7. Fig. 10 describes the performance of RBSMs during the DC poleto-pole fault. It can be seen from Fig. 10(a) that ucs is directly superimposed on the lower switches T2 and T3 once fault protection mode is enabled. Therefore, it is important to select the appropriate auxiliary capacitance Cs to ensure the system reliability of ERBMMC. Attention should also be paid to the RBSM capacitor voltages shown as Fig. 10(b). Since all IGBTs are blocked in time, the RBSM capacitor voltages will remain its initial value before failure and then keep almost constant, which is the reasonable condition for ERBMMC restarting after the nonpermanent fault is cleared as soon as possible.

4.1. DC fault handling performance From the abovementioned analysis, it is concluded that the RBSM capacitors discharging stage duration time mainly depends on the fault detection and protection execute system response speed. Thus the fault detection technique is a crucial issue in fault management, however, it is out of scope of this paper. Take the permanent pole-to-pole DC fault scenario for example and the fault point locates at about 10 km away from ERBMMC. Moreover, assuming fault occurs at 0.2 s and 0.1 ms later ERBMMC goes into blocking stage. The simulation results are shown in Figs. 9 and 10. From t = 0 s to 0.2 s, the ERBMMC works in normal operation mode. Once DC pole-to-pole fault occurs, the DC link voltage UDC drops to zero immediately and thus interrupts the power transmission, shown as Fig. 9(a). This will be accompanied by an inrush short circuit current at the fault point, as seen in Fig. 9(b). It is further supposed that it takes 0.1 ms for blocking all the trigger pulses for the ERBMMC for clearing the fault currents. According to the DC fault handling mechanism theory in Section 3, both the auxiliary capacitors Cs in the bypass circuits and CLMs were activated for quickly providing the inverse voltage, which helps to extinguish the fault current arc in time. Fig. 9(c) and (d) illustrates the grid voltages and currents during DC fault. As long

4.2. Parameter effect According to the theory analysis in Section 3, fault current starts to charge the auxiliary capacitors Cs through Ts and Rlim under fault blocking stage. As a result, the voltage across the series-connected Cs increases quickly for providing the inverse voltage to suppress the fault current. Shown as Fig. 11(a), the fault current damping time constant is proportional to Cs and it decreases rapidly according to (14). Fig. 11(b) shows the relationship between the auxiliary capacitor voltage ucs and Cs . It is also concluded that, the AC feeding loop will be generated if the so called inverse voltage uinv is less than the AC line-to-line voltage ULm . According to (17), the ucs, peak is reduced significantly with the incensement of Cs . The larger Cs may lead to more serious AC-side energy feeding the fault point, which should be avoided in practical engineering. Fig. 11(c) and (d) describes the relationship of fault current with auxiliary capacitor voltage ucs and current limiting resistor Rlim . It indicates that the addition of Rlim will accelerate the fault current attenuation. But the decreased fault current will further lead to inevitable reduction of the peak auxiliary capacitor voltage ucs .

Please cite this article in press as: X. Yang, et al., An enhanced reverse blocking MMC with DC fault handling capability for HVDC applications, Electr. Power Syst. Res. (2017), http://dx.doi.org/10.1016/j.epsr.2017.08.040

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of the bypass circuit voltage stress with the auxiliary capacitor, the leg inductors and the system equivalent resistor were presented. It is obviously that once DC fault occurs, both the bypass circuits and CLMs were activated for quickly providing the inverse voltage, which helps to extinguish the fault current arc in time. Moreover, as a better cost-effective solution, the proposed ERBMMC reduced the consistency requirement of the trigger pulses by employing the bypass circuits, which greatly enhances the reliability and availability of the MMC-HVDC system. What is more, the ERBMMC adopts the same original modulation strategies under the normal operation condition, thus it further reduced the complexity of industry design. This paper showed that the proposed ERBMMC topology provided the desired dynamic performance and fault management capabilities for the future MMC-HVDC system applications.

Acknowledgements This work was supported in part by the National Key Research and Development Program of China with grant No. 2016YFE0131700, in part by the Open Fund of State Key Laboratory of Operation and Control of Renewable Energy & Storage Systems, and in part by the National Natural Science Foundation of China with grant No. 51577010.

References

Fig. 11. Parameters effect simulation: (a) DC fault current vs Cs ; (b) auxiliary capacitor voltage vs Cs ; (c) DC fault current vs Rlim ; (d) auxiliary capacitor voltage vs Rlim.

5. Conclusions This paper investigated an enhanced reverse blocking modular multilevel converter (ERBMMC) topology for improving the HVDC system resiliency to DC side faults. Unlike the conventional MMCs, RBSMs and CLMs were employed as the basic building blocks, thus it further enhanced the DC fault handling capabilities. Based on the analysis of structural characteristics and operation principles, the fault protection mechanism of ERBMMC was revealed in detail. In addition, the relationships of the fault current with the auxiliary capacitors and system equivalent resistor, as well as the relations

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Please cite this article in press as: X. Yang, et al., An enhanced reverse blocking MMC with DC fault handling capability for HVDC applications, Electr. Power Syst. Res. (2017), http://dx.doi.org/10.1016/j.epsr.2017.08.040