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DC fault current limiting effect of MMC submodule capacitors
Electrical Power and Energy Systems 115 (2020) 105444
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DC fault current limiting effect of MMC submodule capacitors a
a,⁎
a,⁎
a
b
Xiaoqian Li , Biao Zhao , Yingdong Wei , Xiaorong Xie , Yinghong Hu , Dewu Shu a b c
c
T
The Department of Electrical Engineering, Tsinghua University, Beijing 100084, China The North China Electric Power Research Institute, Beijing 100045, China The Department of Electrical Engineering, Shanghai Jiaotong University, Shanghai 200240, China
ARTICLE INFO
ABSTRACT
Keywords: DC fault Fault current limiting (FCL) Modular multilevel converter (MMC) Submodule (SM) capacitor
DC short-circuit fault is a crucial issue in DC grids because the DC fault current increases rapidly with accompanying high fault energy. Limiting the DC fault current is a promising solution to simplify the design of the DC breaker and DC protection. The majority of existing DC fault current limiting (FCL) approaches relies on extra devices, such as DC line inductors. However, the control ability of modular multilevel converters (MMCs) is not optimized. In this study, the submodule (SM) capacitor dynamics during the short DC fault procedure was considered a new control objective, and its effect on the limiting DC fault current was analyzed and revealed. The complex time-varying DC fault transient circuit was comprehensively represented by introducing two base circuit structures and one duty cycle index D. The averaged circuit model was proposed on the basis of the state–space averaging method, which can intuitively show the relation between SM capacitor and DC fault current. The analytical expressions of the DC fault current was given, which can guide the design of the DC FCL control of MMC. The duty cycle index D can represent the discharge of SM capacitors, and the increasing speed of the DC fault current declines with the decrease in D. Accordingly, a feasible FCL control strategy was proposed by choosing D as a tool for affecting and controlling the DC fault current. The proposed FCL control strategy can evidently reduce dc fault current, and avoid the drawbacks of the conventional block or bypass approaches. The simulation results validated the effectiveness of the proposed analysis method and corresponding conclusions.
1. Introduction MODULAR multilevel converter (MMC) is a competitive candidate for high-voltage direct current (HVDC) systems that use voltage source converters (VSCs) because of its advantages, such as modular design, ease of implementing considerable levels, low switching frequency, and low harmonics [1–5]. The multiple MMCs that form a mesh connection make the HVDC grid more flexible, reliable, and economical than pointto-point VSC–HVDCs; this type of grid also shows remarkable potential in large-scale renewable power integration and high-power and highvoltage application fields [6,7]. The DC short-circuit fault is a critical issue that must be solved in the HVDC grid [8–13] because the DC fault current can increase to a high level in a short time with high fault energy. For safety, isolating the DC fault current (tens of kA) rapidly (within a few milliseconds) and dissipating the fault energy (thousands of MJ) are required, thereby causing remarkable challenges to the design of the DC breaker and DC protection. Therefore, limiting the DC fault current is crucial in solving the DC fault issue in the HVDC grid (see Fig. 1).
⁎
The use of an extra DC inductor in the DC line is a commonly used fault current limiting (FCL) approach [14,15]. When a DC fault occurs, the DC inductor can effectively reduce the increasing speed of the fault current. However, using the DC inductor has an adverse effect on the MMC controller’s dynamics and stability. Another approach is by adopting additional FCL devices. A superconducting fault current limiter is proposed in [16] to limit the fault current by changing its operation from the superconducting state to the normal state as soon as a large current is detected. A current limiting HVDC circuit breaker is proposed in [17] to select the number of inductor branches flexibly and implement the FCL function. A multilevel nonsuperconducting fault current limiter is proposed in [18] which can control the highlevel fault current by inserting different resistances in the circuit with low power losses. A capacitor-based nonsuperconducting fault current limiter is proposed in [19] which is based on transferring electrical energy to a capacitor during fault occurrence and can be used after fault removal. These devices provide new ideas for FCL, but their reliability needs further testing. Moreover, the performance of existing FCL approaches is unsatisfactory and their extra cost and power loss is
Corresponding authors. E-mail addresses: [email protected] (B. Zhao), [email protected] (Y. Wei), [email protected] (D. Shu).
https://doi.org/10.1016/j.ijepes.2019.105444 Received 1 November 2018; Received in revised form 20 June 2019; Accepted 25 July 2019 Available online 23 August 2019 0142-0615/ © 2019 Elsevier Ltd. All rights reserved.
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Nomenclature N idc idc (t ) uc u c (t ) D D′ Ls Ldc Rs Rf Cd
Ts Ts
Le Re Ce Ts x(t) x (t ) A Idc Udc δ ω0 ωr γ
number of submodules per arm DC fault current averaged DC fault current submodule capacitor voltage averaged submodule capacitor voltage duty cycle of Base Circuit 1 per switching period duty cycle of Base Circuit 2 per switching period arm inductance DC line inductor arm resistance fault resistance capacitance per submodule
high. Alternatively, the FCL function can be realized without additional cost and power loss by developing the control potential of MMC because MMC, as the main source and supplier of the DC fault current and fault energy, can affect the DC fault current, wherein few studies have recognized this capability. A connection exists between submodule (SM) capacitors and the DC fault current [20,21]. At the initial stage of the DC fault, the DC fault current is dominated by the discharging current of SM capacitors, and the fault energy comes from the discharging energy released by SM capacitors. Therefore, SM capacitors can be chosen as a new control object for the purpose of limiting the fault current. Few approaches involving SM capacitor discharge have been proposed. One conventional approach is to block MMC by turning off all insulated gate bipolar transistors (IGBTs) to stop the SM capacitor discharge completely. Although the DC fault is not completely interrupted due to the freewheeling effect of diodes, the DC fault current is reduced [22]. However, one critical drawback is that the blocking action forces IGBTs to turn off the high fault current immediately and directly, resulting in the overvoltage of arm inductors and DC lines and causing isolation challenges, which may have an adverse impact on the service life of IGBTs and arm inductors. Another approach is to bypass the MMC, which can be realized by using its own IGBTs [8] or double thyristor switches [10]. The bypass action is effective in mitigating the increase in DC fault current and letting it decay gradually. However, the AC system and MMC arms will be exposed to a large AC current because bypassing the MMC transforms DC fault into a balanced AC short circuit [22]. Moreover, the DC voltage is forced to become zero, thereby
Ts
equivalent inductance of the DC fault circuit equivalent resistance of the DC fault circuit equivalent capacitance of the DC fault circuit switching period state vector average of state vector x(t) averaged matrix DC current before DC fault occurs DC voltage before DC fault occurs attenuation coefficient resonance angular frequency oscillation angular frequency oscillation angle
possibly leading to the undesirable cascading DC voltage drop of other converters. These block and bypass actions are just two available approaches for MMC FCL control. However, these approaches have inevitable drawbacks. Notably, aside from these two approaches, other options with superior MMC performance exist in limiting the fault current. To find and design optimal FCL control approaches, the analytical relations between the DC fault current and SM capacitors should be examined comprehensively. Some important research has been done on the analysis and calculation of the DC fault current [20–24]. In [23], a mathematical approximation of the DC fault current of MMC without converter blocking was proposed by using theoretical analysis and numerical calculation. A generic DC fault current calculation method for DC grids was proposed in [24], wherein the fault current in every branch could be calculated based on the combination of the simplified equivalent model of MMC and the pre-fault and faulted matrices. These analysis and calculation methods are effective and practical. However, the majority of methods are built on the premise that the control of MMC remains the same as normal operations even when DC fault occurs. If the extra FCL control is introduced in MMC, then SM capacitors will exhibit different behaviors, which may be beyond the scope of these analytical methods. This study aims to reveal the connection between SM capacitors and the DC fault current theoretically and provide mathematical support for the design of FCL control. First, two independent base circuit structures and a new variable (duty cycle of the capacitor insertion state in each switching period) are defined comprehensively to represent the varying DC fault transient circuit structure caused by the continuous insertion and bypass of SM capacitors. Second, on the basis of the state–space averaging method, state equations of the DC fault transient circuit are proposed. Accordingly, analytical expressions of the DC fault current and SM capacitor voltage are derived to further analyze of the effect of using SM capacitors on the DC fault current. The rest of this paper is organized as follows: Section 2 presents the analysis of the relations between SM capacitors and DC fault current. Furthermore, the state–space averaging model, averaged circuit model, and time–domain expression of the DC fault current are given. To verify the validation of the proposed analytical expressions, Section 3 presents the simulation results. Finally, Section 4 discusses the conclusions. 2. Analytical relations between SM capacitors and the DC fault current The MMC should continuously operate in the HVDC grid [13,14] and wait for the DC breaker to isolate and clear the DC fault current. Therefore, the structure of the DC fault transient circuit constantly changes because SM capacitors are continuously switched between the insert and bypass states under the MMC control. The time-varying
Fig. 1. Typical circuit diagram of MMC and DC breakers in the HVDC grid. 2
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circuit structure is a main challenge to analyze and model the DC fault transient. To solve this problem, the state–space averaging method is adopted in this study. Two independent base circuit structures and a new variable are introduced to represent the time-varying circuit structure and the dynamics of SM capacitors generally. The state equations of the DC fault transient circuit are proposed and solved in the time domain. The equivalent averaged circuit model is also given. The relation between SM capacitors and the DC fault current are analyzed accordingly.
Le 0 d idc (t ) = 0 Ce dt uc (t )
A2
dx (t ) dt
K
i dc (t ) . u c (t )
Re 0 0 0
(4)
x (t )
Compared with the converter switching process, the DC fault transient process is slow. Hence, the DC fault current and capacitor voltage are modeled by obtaining the average in an interval of length Ts (one switching period). The average of the state vector x(t) can be expressed as
x (t )
2.1. Two independent base circuit structures and the duty cycle
Ts
=
1 Ts
t + Ts t
x ( )d .
(5)
Fig. 3 shows how the state vector x(t) and its average evolve over one switching period. The averaged matrix A is
Theoretically, the number of SM capacitors inserted in one phase unit varies from 0 to 2 N, and contains various combinations. To represent the different time-varying combinations in a unified way, the following independent circuit structures can be chosen as the base:
R e 2ND
A = DA1 + D A2 =
(a) Base Circuit 1: all SM capacitors are inserted. (b) Base Circuit 2: all SM capacitors are bypassed.
D 2N
,
0
(6)
where D′ = 1 − D is satisfied. The state–space averaged model of the DC fault transient circuit can be obtained as follows:
Fig. 2 shows the actual circuit structure and its equivalent two base circuits. Notably, Base Circuits 1 and 2 are mathematically defined to help represent the DC fault transient circuit structure although they may not necessarily appear in real operation. A variable D is defined as the duty cycle of Base Circuit 1 in each switching period. D represents the discharging of SM capacitors. Therefore, by regulating D within the range [0, 1], the time-varying circuit structures can be simplified. For instance, when D = 0.5 is satisfied, 50% of all capacitors are inserted, and the circuit state corresponds to normal operation in steady state. When D = 0 is satisfied, no capacitors are inserted, which corresponds to the bypass action mentioned in Introduction. Notably, the range of D is theoretically defined as [0, 1], thereby comprehensively representing all the possibilities of the complex time-varying DC fault circuit by the two base circuits. To obtain the FCL function, D should be chosen from the range of [0, 0.5].
Le 0 d 0 Ce dt K
i dc (t )
Ts
u c (t )
Ts
Re 2ND
=
D 2N
d x (t ) Ts dt
0 A
i dc (t )
Ts
u c (t )
Ts
x (t ) Ts
. (7)
2.3. Time domain expressions According to the state–space averaged model in Eq. (7), the second order differential equation of the averaged DC fault current can be obtained as follows:
d 2 i dc (t ) dt
Ts
+
Re d i dc (t ) Le dt
Ts
+
D2 i dc (t ) Le Ce
Ts
= 0,
(8)
2.2. State–Space averaged model In the DC fault transient circuit, the state vector x(t) contained two state variables, namely, DC fault current idc (inductor current) and SM capacitor voltage uc. For simplicity, the voltage of all SM capacitors is assumed balanced because the DC fault transient is very short (within a few milliseconds). The state vector x(t) can be obtained as follows:
x (t ) =
idc (t ) . uc (t )
(1)
During the first subinterval, when MMC is in Base Circuit 1 and all capacitors are inserted, the converter is reduced to a linear circuit (R-LC) that can be described by the following state equations:
Le 0 d idc (t ) = 0 Ce dt uc (t ) dx (t ) dt
K
R e 2N 1 2N A1
0
i dc (t ) , u c (t ) x (t )
(2)
where Le is the equivalent inductance, Re refers to the equivalent resistance, and Ce denotes the equivalent capacitance, which can be obtained as follows:
Le = Re =
2L s 3 2Rs 3
Ce =
+ Ldc + Rf . 3Cd 2N
(3)
During the second subinterval, with MMC in Base Circuit 2, the converter is reduced to another linear circuit (R-L) whose state equations are
Fig. 2. Structure and its equivalent of the two base circuits considered in the FCL control strategy. 3
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Fig. 4 shows that the decreased D results in the increase in capacitance and decrease in both the capacitor voltage and DC fault current. The principles are presented as follows. From the perspective of the definition of D, the reduced D indicates that the discharging process of SM capacitors in each switching period is shortened. Thus, fewer capacitors are inserted in the circuit and less energy in capacitors is released. From the perspective of the averaged circuit, the equivalent capacitance is increased as the capacitor voltage is decreased when D is reduced. The contribution of SM capacitors in MMC to the DC fault current then reduces as the DC fault current is consequently reduced. In this section, the analytical expressions of the DC fault current and SM capacitor voltage are formulated under varying D values. The averaged circuit related to different D values is also proposed. The duty cycle D can represent the discharging of SM capacitors. Therefore, the proposed expressions and the averaged circuit can be used to analyze the FCL effect of SM capacitors in a comprehensive manner to provide a mathematical foundation for the design of an optimal FCL control strategy. D is a good tool for controlling the DC fault current.
Fig. 3. State vector and its average evolve over one switching period.
and the initial condition can be expressed as follows:
i dc (0 + ) d i dc (0 + ) Ts dt
Ts
=
= Idc
2DUdc Re Idc , Le
(9)
where Idc and Udc denote the DC current and DC voltage before the DC fault occurs. The characteristic roots are obtained as follows:
p1,2 =
Re ± 2Le
Re 2Le
2
D2 . Le Ce
3. Simulation results To verify the proposed analytical expressions, the MMC system rated at 200 MVA/ ± 160 kV is simulated by using PSCAD/EMTDC. Fig. 5 shows the configuration of the simulated system. Three MMCs share the same parameters listed in Appendix B. The DC circuit breaker (DCCB) adopts the ABB hybrid DC circuit breaker, which is composed of a load commutation switch, an ultrafast disconnector, and a main breaker with hundreds of IGBTs and surge arresters [25]. In the steady state, MMC1 controls the DC voltage, whereas MMC2 and MMC3 control the active power. P2 = P3 = 85 MW and P1 = 170 MW are satisfied.
(10)
To solve Eq. (8), different cases under varying D values are discussed as follows. (1) Underdamped Case: when D >
Re 2 Le / Ce
In this case, the characteristic roots are complex conjugate with a negative real part that can be expressed as
p1,2 =
(11)
± j r.
By solving Eq. (8) under the initial condition of Eq. (9), the time–domain averaged expressions of the DC fault current and SM capacitor voltage can be obtained as
i dc (t ) u c (t )
Ts
Ts
=
t
= Ae
A 2N
Le Ce
e
sin(
rt
t sin(
+ )
rt
+
+ )
3.1. Feasible control strategy to regulate D A feasible control strategy for the duty cycle D is proposed. D is approximately equivalent to the DC modulation index. According to its definition, D denotes the ratio of the sum of two arm voltages in one phase unit and the pole-to-pole DC voltage that is expressed as
, (12)
where parameters are expressed as
A= = arctan
(
=
Idc sin 2 r Le Idc 4DUdc R e Idc
0
)
Re 2Le
r
=
=
D= D2 Le Ce
2 0
= arctan
2 r
2udc (t )
* udc ,
j= a, b, c,
(14)
where ujp and ujn denote the voltage of the upper and lower arms in the phase unit j, respectively; udc is the pole-to-pole DC voltage; and udc* refers to the DC modulation index, that is, the DC component of the arm reference voltage per unit. Under normal operation, D = udc* = 0.5 is generally satisfied. Notably, Eq. (14) is satisfied on the premise that AC components of ujp and ujn cancel each other. However, the control of D inevitably leads to the appearance of the DC offset in the arm reference voltage. Therefore, a dynamic limiter is proposed to guarantee the symmetry of
.
( )
ujp (t ) + ujn (t )
(13)
(2) Overdamped Case and Critically Damped Case As the resistance in the circuit is significantly small, the underdamped case appears frequently. The overdamped and critically damped cases are very rare. The Appendix A shows the deduction of the time–domain averaged expressions of the DC fault current and SM capacitor voltage in the overdamped and critically damped cases. 2.4. Averaged circuit model According to the state–space averaged model, the circuits can be reconstructed to be equivalent to Eq. (7). Fig. 4 shows the averaged circuit model. Compared with Fig. 2, the capacitor in the averaged circuit model becomes variable and controllable. Both the capacitance and voltage of the capacitor are directly related to the duty cycle D. The averaged circuit provides a clear and intuitive way to observe and analyze the effect of the SM capacitor on the DC fault current.
Fig. 4. Averaged circuit model during DC fault transient when FCL control is considered. 4
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Fig. 5. Configuration of the simulated system.
ensure normal operation. At t = 0.8 s, DC fault occurs in DC line 2. After DC fault is detected, MMCs perform the FCL function by changing the setting value of D. Notably, DCCBs are set to not operate in this condition because the characteristic of DC fault current is considered rather than the protection procedure. Section 3.3 presents the coordination of DCCBs and MMC FCL control. As FCL control is activated only after fault detection, the majority of existing fault detection approaches, such as methods based on voltage across DC reactor [15], DC voltage derivative [28], DC current derivative [29], travelling wave [30], and DC reactor voltage change rate [31], can be used in this study. The generated fault detection signal is shared by MMCs and the DCCB. Fig. 8 shows the comparison of simulation and calculation results of MMC1. The DC fault current and the sum of SM capacitor voltages in the upper arm of phase a are demonstrated. After fault detection, MMC1 sets a different duty cycle D with the step by using 0.1 within the range of [0, 1]. For comparison, the simulation results are also included (green line with the × mark) when MMC adopting block is operational. Fig. 8(a) and 8(b) show that the fault detection delay is set to 0 and 1 ms, respectively. When D ∈ [0, 0.5] is satisfied, the DC fault current is limited (shaded
Fig. 6. Control diagram of the simulated MMC.
the AC components of ujp and ujn. The upper and lower limit can be obtained as follows: * u max * umin =
= min ( 2D , 1) max ( 2D
1, 0 )
.
(15)
Fig. 6 shows the control diagram of the simulated MMC. The DC modulation index (udc*) is equivalent to D and shared by six arms. The AC reference voltages (ua*, ub*, uc*) use the results of conventional P/ Q/Udc and current controls. D is then attached to AC reference voltages and processed by the dynamic limiter to generate reference arm voltages (uap*, uan*, ubp*, ubn*, ucp*, ucn*) for modulation. A carrier phaseshifted sinusoidal PWM scheme is used [26]. The switching frequency for each switching device is 300 Hz. Notably, the control strategy presented in this study is a feasible solution. D is manipulated in an open-loop manner. Untreated AC reference voltages are inevitably influenced by the dynamic limiter. In fact, D can be controlled automatically in the closed-loop manner to achieve the online FCL function, and AC reference voltages can be actively limited in the controllable range [27]. The FCL control strategy with good dynamic performance that considers the interactions between DC fault and AC grid will be presented in a future study. To verify the validity of the proposed D control strategy, Fig. 7(a) shows the waveforms of the upper and lower arm reference voltages when D = 0.2, 0.5, 0.8. Fig. 7(b) shows the corresponding amplitude–frequency characteristic of the upper arm reference. The DC component of the arm reference voltage can accurately track the set value of D because the dynamic limiter can effectively guarantee that AC components of both arm references cancel each other. Fig. 7(b) shows that other undesired harmonics (second- and third-order harmonics) are not high although the amplitude of fundamental frequency component of the arm reference voltage is inevitably changed with the varying of D. 3.2. Accuracy of the proposed analytical expressions To verify the proposed transient analytical expressions, calculation results are compared with simulation results under the pole-to-pole DC fault. Before t = 0.8 s, MMC is in the steady state, and D = 0.5 is set to
Fig. 7. Waveforms of upper and lower arm reference voltages when D varies. 5
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Fig. 8. Comparison of simulation and calculation results of MMC1 under varying D.
area). Otherwise, the DC fault current is increased. The FCL effect of the blocking action is close to the FCL effect when D is in the range of [0.1, 0.2]. Fig. 8(a) and 8(b) present that the analytical and simulation results agree well regardless of fault detection delay, thereby validating the accuracy of the proposed analytical expressions.
currents is mild. The overvoltage of the arm inductor (80.95 kV) and DC line (428.12 kV) is also acceptable. Fig. 9(c) and 10(c) present that MMC is bypassed during 0.801–0.803 s, which corresponds to D = 0.0. In this case, the FCL effect is the most remarkable because DC fault is transformed into AC fault. The DC fault current stops increasing immediately and decays slowly. Compared with the no-action case, the DC fault current peak is reduced by 54%, whereas the AC fault current peak is increased by 70%. In addition, the DC voltage is forced to zero, which may result in the change of DC voltages of other converters and lead to an undesirable impact on the protection and recovery of the HVDC grid. Fig. 9(d) and 10(d) show the results when MMC is blocked during 0.801–0.806 s. Six MMC arms become rectifier bridges, and the antiparallel diodes provide the path for the AC fault current to feed into the DC side continuously. Compared with the no-action case, the DC current peak is reduced by 43%, but the overvoltage of the arm inductor is significantly increased by 27%, thus causing an isolation challenge. Fig. 9(b) and 10(b) show the case when the proposed MMC FCL control is activated and D = 0.2 is set during 0.801–0.803 s. Compared with the three approaches, the proposed FCL control can significantly reduce the DC fault current (by 33% compared with no-action) and avoid the undesired overcurrent (bypass action), overvoltage (block action), and zero-voltage (bypass action) problems, thereby indicating that the use of the proposed FCL control strategy and the appropriate selection of the D value can achieve superior FCL effect.
3.3. Comparison of the FCL effect and other protection approaches To show the effect of the proposed FCL control, the simulation results of the proposed FCL control and three approaches (no action, bypass action, and block action) are compared. At t = 0.8 s, DC fault occurs in DC line 2. At t = 0.801 s, DC fault is detected, MMCs starts the FCL control as DCCB3 and DCCB4 interrupt and isolate the fault current. At t = 0.803 s, DC line 2 is isolated and MMC1 stops the FCL control. MMC1 and MMC3 resume power transmission (P1 = P3 = 85 MW, and P2 = 0). The recovery of fault lines is beyond the scope of this study and thus excluded from this paper. Figs. 9 and 10 show the simulation results of MMC1 and DCCB3, respectively. Fig. 9 shows the waveforms of MMC1 DC current, arm reference voltages of phase a, three upper arm, three-phase AC, and DCCB3 currents (load commutation switch current, IGBT current of the main DC breaker, and surge arrester current). Fig. 10 presents the waveforms of MMC1 DC voltage, and the upper and lower arm voltages of phase a. Table 1 lists the peak value of the DC current, AC current, arm current, arm inductor voltage, and DC voltage. Fig. 9(a) and 10(a) show that MMC remains unchanged after DC fault and maintains its continuous operation under the normal steadystate control strategy. In this case, D = 0.5 is constantly satisfied. The DC fault current is thereby not limited and reaches the peak (3.05 kA) at t = 0.803 s. The overcurrent in the arm (1.50 kA) and AC (1.45 kA)
4. Conclusions This study proposes an analytical analysis method for the DC fault transient circuit, in which the SM capacitor dynamics are controllable 6
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Fig. 9. Comparison of the simulation results under different protection approaches: waveforms of the DC current, DCCB currents, arm reference voltages, arm currents, and AC currents.
and considered as the new control object.
(c) Analytical expressions of the DC fault current and SM capacitor voltage are obtained to guide the design of DC FCL control of MMC. (d) The effect of the SM capacitor on the DC FCL control is concluded. The duty cycle D can represent the discharge of SM capacitors and is a good tool for affecting and controlling the DC fault current. The increasing speed of the DC fault current declines with the decrease in D. The DC fault current may decay when D tends toward zero. (e) A feasible control strategy is proposed to regulate D. By appropriately choosing the value of D, the proposed strategy can significantly reduce the DC fault current and avoid the drawbacks of
(a) Two base circuits (all capacitors are either inserted or bypassed) and one duty cycle index (D, approximately equivalent to the DC modulation index) are defined to represent the complex timevarying DC fault transient circuit structure comprehensively. (b) The state equations of the DC fault circuit are obtained based on the state–space averaging method, and the averaged circuit model is established to show the relationship between the SM capacitor and DC fault current intuitively. 7
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Fig. 10. Comparison of the simulation results under different protection approaches: waveforms of the DC line and arm inductor voltages. Table 1 Comparison of the FCL Effect of Several Protection Approaches. Approach
DC current peak (kA)
Arm current peak (kA)
AC current peak (kA)
Arm inductor voltage peak (kV)
DC voltage peak (kV)
DC voltage valley (kV)
No action (D = 0.5) Bypass (D = 0.0) Block Proposed FCL (D = 0.2) Proposed FCL (D = 0.1)
3.05 1.41 1.73 2.05 1.72
1.50 1.67 1.73 1.41 1.52
1.45 2.46 1.73 1.48 1.95
80.95 76.97 102.48 79.14 77.13
428.12 423.86 465.50 428.60 428.42
247.78 0.00 25.61 83.49 41.79
the conventional block approach (severe overvoltage on arm inductors and IGBTs directly turning off the high fault current) and the bypass approach (significantly large AC current and zero DC voltage).
Acknowledgements This work was supported by the National Natural Science Foundation of China (51807105), the Science and Technology Project of State Grid of China (52018K170028), and the Power Electronics Science and Education Development Program of Delta Group (DREG2018007).
Declaration of Competing Interest The authors declared that there is no conflict of interest. Appendix A (1) Overdamped Case: when D <
Re 2 Le / Ce
In this case, the characteristic roots are expressed as
p1,2 =
2 0
2
±
=
(A1)
± | r |.
Similarly, the DC fault current and SM capacitor voltage are obtained as follows:
u c (t )
Ts
=
i dc (t ) Ts = A1 e p1 t + A2 e p2 t 1 [A1 (p1 Le + R e ) e p1 t + A2 (p2 Le 2ND
+ R e ) e p2 t ]
,
(A2)
where the parameters are expressed as follows:
A1 = A2 =
2 | r | L e Idc + 4DUdc 4 | r | Le
Re Idc
2 | r | Le Idc 4DUdc + Re Idc 4 | r | Le
2DUdc Re
Idc
2DUdc Re
. (A3)
Notably, when D = 0 is satisfied, the DC fault current differential equation changes from second to first order. Fig. 4 shows that the averaged circuit also becomes a first-order circuit (R-L). Hence, the characteristic roots and corresponding parameters are expressed as follows:
p1 = 0, p2 = 2 . 0 = 0 A1 = 0, A2 = Idc
(A4)
Accordingly, the DC fault current and SM capacitor voltage are obtained as follows:
i dc (t )
Ts
uc (t )
= Idc e Ts
=
Udc N
2 t
.
(A5)
8
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(2) Critically Damped Case: when D =
Re 2 L e / Ce
In this case, the characteristic roots are are expressed as
p1 = p2 =
(A6)
.
The time–domain averaged expressions of the DC fault current and SM capacitor voltage are obtained as follows:
i dc (t ) u c (t )
Ts
=
Ts
1 2ND
= (A3 + A 4 t ) e
(2DU
dc
+
4DUdc
t Re Idc
2
)
t e
t
,
(A7)
where the parameters are expressed as follows:
A4 =
A3 = Idc 4DUdc Re Idc 2Le
2DUdc . Le
(A8)
Appendix B See Table B1 Table B1 MMC Parameters Used in the Calculation and Simulation. Parameter
Value
Rated MMC output ac voltage Rated capacity of MMC Rated dc-link voltage of MMC Number of SMs of each arm Inductance of each arm Capacitance of each SM Dc line inductor
166 kV 200 MVA ± 160 kV 133 0.1 H (11%) 5000 μF 0.3 H
current limiter in MMC-MTDC. J Eng. 2017;13:1307–11. [17] Li S, Zhang J, Xu J, Zhao C. A new topology for current limiting HVDC circuit breaker. Int J Electr Power Energy Syst 2019;104:933–42. [18] Nazari-Heris Morteza, Nourmohamadi Hesam, Sabahi Mehran, Abapour Mehdi. Multilevel nonsuperconducting fault current limiter: analysis and practical feasibility. IEEE Trans Power Electron 2018;32(8):6059–68. [19] Nourmohamadi Hesam, Nazari-Heris Morteza, Sabahi Mehran, Abapour Mehdi. A novel structure for bridge-type fault current limiter: capacitor-based nonsuperconducting FCL. IEEE Trans Power Electron 2018;33(4):3044–51. [20] Bin LI, Jiawei HE, Jie T, Yadong FE, Yunlong DO. DC fault analysis for modular multilevel converter-based system. J Modern Power Syst Clean Energy 2016;5(2):275–82. [21] Cwikowski O, Wood A, Miller A, Barnes M, Shuttleworth R. Operating DC Circuit Breakers with MMC. IEEE Trans Power Del 2018;33(1):260–70. [22] Wang S, Li C, Adeuyi OD, Li G, Ugalde-Loo CE, Liang J. Coordination of MMCs with hybrid DC circuit breakers for HVDC grid protection. IEEE Trans Power Del 2019;34(1):11–22. [23] Wang Y, Yuan Z, Fu J, Li Y, Zhao Y. A feasible coordination protection strategy for MMC-MTDC systems under DC faults. Int J Electr Power Energy Syst 2017;90:103–11. [24] Li C, Zhao C, Xu J, Ji Y, Zhang F. A pole-to-pole short-circuit fault current calculation method for DC grids. IEEE Trans Power Syst 2017;32(6):4943–53. [25] Callavik M, Blomberg A, Hafner J, Jacobson B. The hybrid HVDC breaker: an innovation breakthrough enabling reliable HVDC grids. ABB Grid Syst., Z¨urich, Switzerland: Tech. Paper; 2012. [26] Solas E, Abad G, Andoni Barrena J, Aurtenetxea S, Carcar A, Zajac L. Modular multilevel converter with different submodule concepts—Part I: capacitor voltage balancing method. IEEE Trans Ind Electron 2013;60(10):4525–35. [27] Li R, Xu L, Yao L, Williams BW. Active control of DC fault currents in DC solid-state transformers during ride-through operation of multi-terminal HVDC systems. IEEE Trans Energy Convers 2016;31(4):1336–46. [28] Sneath J, Rajapakse AD. Fault detection and interruption in an earthed HVDC grid using ROCOV and hybrid DC breakers. IEEE Trans Power Del 2014;PP. [29] Marvik JI, D'Arco S, Sharifabadi K. Protection scheme for multi-terminal radial vsc hvdc system without communication between terminals. CIGRE 2015:1–10. [30] Wang J, Berggren B, Linden K, Pan J. Multi-terminal DC system line protection requirement and high speed protection solutions. Proc CIGRE 2015:1–9. [31] Li R, Xu L, Yao L. DC fault detection and location in meshed multiterminal HVDC systems based on DC reactor voltage change rate. IEEE Trans Power Del 2017;32(3):1516–26.
References [1] Debnath S, Qin JC, Bahrani B, Saeedifard M, Barbosa P. Operation, control, and applications of the modular multilevel converter: a review. IEEE Trans Power Electron 2015;30(1):37–53. [2] Xue Y, Xu Z. On the bipolar MMC-HVDC topology suitable for bulk power overhead line transmission: configuration, control, and DC fault analysis. IEEE Trans Power Del 2014;29(6):2420–9. [3] Marquardt R. Modular multilevel converter: an universal concept for HVDC networks and extended DC-bus-applications. Proc. int. power electron. conf. 2010. p. 502–7. [4] Bärnklau H, Gensior A, Rudolph J. A model-based control scheme for modular multilevel converters. IEEE Trans Ind Electron 2013;60(12):5359–75. [5] Song Q, Liu W, Li X, Rao H, Xu S, Li L, et al. A steady-state analysis method for a modular multilevel converter. IEEE Trans Power Electron 2013;28(8):3702–13. [6] Chuanyue L, Xiaobo H, Jingli G, Jun L. The dc grid reliability and cost evaluation with Zhoushan five-terminal HVDC case study. Proc. 2015 50th Int. Univ. Power Eng. Conf. 2015. p. 1–6. [7] Rao H. Architecture of nan’ao multi-terminal VSC-HVDC system and its multifunctional control. CSEE J Power Energy Syst 2015;1:9–18. [8] Cwikowski O, Wickramasinghe HR, Konstantinou G, Pou J, Barnes M, Shuttleworth R. Modular Multilevel Converter DC Fault Protection. IEEE Trans Power Del 2018;33(1):291–300. [9] Li B, Li Y, He J. A DC fault handling method of the MMC-based DC system. Int J Electr Power Energy Syst 2017;93:39–50. [10] Xi Li, Song Q, Liu W, Rao H, Xu S, Li L. Protection of nonpermanent faults on DC overhead lines in MMC-based HVDC systems. IEEE Trans Power Del 2013;28(1):483–90. [11] Franck CM. HVDC circuit breakers: a review identifying future research needs. IEEE Trans Power Del 2015;26(2):998–1007. [12] Marquardt R. Modular multilevel converter topologies with DC-short circuit current limitation. Proc. IEEE. int. conf. on power electron. and ECCE. 2011. p. 1425–31. [13] Li R, Xu L, Holliday D, Page F, Finney SJ, Williams BW. Continuous operation of radial multiterminal HVDC systems under DC fault. IEEE Trans Power Del 2016;31:351–61. [14] Wang Yizhen, Wen Weijie, Zhang Chong, Chen Zhengguang, Wang Chengshan. Reactor sizing criterion for the continuous operation of meshed HB-MMC-based MTDC system under DC faults. IEEE Trans Ind Appl 2018;54(5):5408–16. [15] Li C, Gole AM, Zhao C. A fast DC fault detection method using DC reactor voltages in HVdc grids. IEEE Trans Power Del 2018;33(5):2254–64. [16] Lv C, Tai N, Jin Z, Zheng X. Research on application of superconducting fault
9
Contents lists available at ScienceDirect
Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes
DC fault current limiting effect of MMC submodule capacitors a
a,⁎
a,⁎
a
b
Xiaoqian Li , Biao Zhao , Yingdong Wei , Xiaorong Xie , Yinghong Hu , Dewu Shu a b c
c
T
The Department of Electrical Engineering, Tsinghua University, Beijing 100084, China The North China Electric Power Research Institute, Beijing 100045, China The Department of Electrical Engineering, Shanghai Jiaotong University, Shanghai 200240, China
ARTICLE INFO
ABSTRACT
Keywords: DC fault Fault current limiting (FCL) Modular multilevel converter (MMC) Submodule (SM) capacitor
DC short-circuit fault is a crucial issue in DC grids because the DC fault current increases rapidly with accompanying high fault energy. Limiting the DC fault current is a promising solution to simplify the design of the DC breaker and DC protection. The majority of existing DC fault current limiting (FCL) approaches relies on extra devices, such as DC line inductors. However, the control ability of modular multilevel converters (MMCs) is not optimized. In this study, the submodule (SM) capacitor dynamics during the short DC fault procedure was considered a new control objective, and its effect on the limiting DC fault current was analyzed and revealed. The complex time-varying DC fault transient circuit was comprehensively represented by introducing two base circuit structures and one duty cycle index D. The averaged circuit model was proposed on the basis of the state–space averaging method, which can intuitively show the relation between SM capacitor and DC fault current. The analytical expressions of the DC fault current was given, which can guide the design of the DC FCL control of MMC. The duty cycle index D can represent the discharge of SM capacitors, and the increasing speed of the DC fault current declines with the decrease in D. Accordingly, a feasible FCL control strategy was proposed by choosing D as a tool for affecting and controlling the DC fault current. The proposed FCL control strategy can evidently reduce dc fault current, and avoid the drawbacks of the conventional block or bypass approaches. The simulation results validated the effectiveness of the proposed analysis method and corresponding conclusions.
1. Introduction MODULAR multilevel converter (MMC) is a competitive candidate for high-voltage direct current (HVDC) systems that use voltage source converters (VSCs) because of its advantages, such as modular design, ease of implementing considerable levels, low switching frequency, and low harmonics [1–5]. The multiple MMCs that form a mesh connection make the HVDC grid more flexible, reliable, and economical than pointto-point VSC–HVDCs; this type of grid also shows remarkable potential in large-scale renewable power integration and high-power and highvoltage application fields [6,7]. The DC short-circuit fault is a critical issue that must be solved in the HVDC grid [8–13] because the DC fault current can increase to a high level in a short time with high fault energy. For safety, isolating the DC fault current (tens of kA) rapidly (within a few milliseconds) and dissipating the fault energy (thousands of MJ) are required, thereby causing remarkable challenges to the design of the DC breaker and DC protection. Therefore, limiting the DC fault current is crucial in solving the DC fault issue in the HVDC grid (see Fig. 1).
⁎
The use of an extra DC inductor in the DC line is a commonly used fault current limiting (FCL) approach [14,15]. When a DC fault occurs, the DC inductor can effectively reduce the increasing speed of the fault current. However, using the DC inductor has an adverse effect on the MMC controller’s dynamics and stability. Another approach is by adopting additional FCL devices. A superconducting fault current limiter is proposed in [16] to limit the fault current by changing its operation from the superconducting state to the normal state as soon as a large current is detected. A current limiting HVDC circuit breaker is proposed in [17] to select the number of inductor branches flexibly and implement the FCL function. A multilevel nonsuperconducting fault current limiter is proposed in [18] which can control the highlevel fault current by inserting different resistances in the circuit with low power losses. A capacitor-based nonsuperconducting fault current limiter is proposed in [19] which is based on transferring electrical energy to a capacitor during fault occurrence and can be used after fault removal. These devices provide new ideas for FCL, but their reliability needs further testing. Moreover, the performance of existing FCL approaches is unsatisfactory and their extra cost and power loss is
Corresponding authors. E-mail addresses: [email protected] (B. Zhao), [email protected] (Y. Wei), [email protected] (D. Shu).
https://doi.org/10.1016/j.ijepes.2019.105444 Received 1 November 2018; Received in revised form 20 June 2019; Accepted 25 July 2019 Available online 23 August 2019 0142-0615/ © 2019 Elsevier Ltd. All rights reserved.
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Nomenclature N idc idc (t ) uc u c (t ) D D′ Ls Ldc Rs Rf Cd
Ts Ts
Le Re Ce Ts x(t) x (t ) A Idc Udc δ ω0 ωr γ
number of submodules per arm DC fault current averaged DC fault current submodule capacitor voltage averaged submodule capacitor voltage duty cycle of Base Circuit 1 per switching period duty cycle of Base Circuit 2 per switching period arm inductance DC line inductor arm resistance fault resistance capacitance per submodule
high. Alternatively, the FCL function can be realized without additional cost and power loss by developing the control potential of MMC because MMC, as the main source and supplier of the DC fault current and fault energy, can affect the DC fault current, wherein few studies have recognized this capability. A connection exists between submodule (SM) capacitors and the DC fault current [20,21]. At the initial stage of the DC fault, the DC fault current is dominated by the discharging current of SM capacitors, and the fault energy comes from the discharging energy released by SM capacitors. Therefore, SM capacitors can be chosen as a new control object for the purpose of limiting the fault current. Few approaches involving SM capacitor discharge have been proposed. One conventional approach is to block MMC by turning off all insulated gate bipolar transistors (IGBTs) to stop the SM capacitor discharge completely. Although the DC fault is not completely interrupted due to the freewheeling effect of diodes, the DC fault current is reduced [22]. However, one critical drawback is that the blocking action forces IGBTs to turn off the high fault current immediately and directly, resulting in the overvoltage of arm inductors and DC lines and causing isolation challenges, which may have an adverse impact on the service life of IGBTs and arm inductors. Another approach is to bypass the MMC, which can be realized by using its own IGBTs [8] or double thyristor switches [10]. The bypass action is effective in mitigating the increase in DC fault current and letting it decay gradually. However, the AC system and MMC arms will be exposed to a large AC current because bypassing the MMC transforms DC fault into a balanced AC short circuit [22]. Moreover, the DC voltage is forced to become zero, thereby
Ts
equivalent inductance of the DC fault circuit equivalent resistance of the DC fault circuit equivalent capacitance of the DC fault circuit switching period state vector average of state vector x(t) averaged matrix DC current before DC fault occurs DC voltage before DC fault occurs attenuation coefficient resonance angular frequency oscillation angular frequency oscillation angle
possibly leading to the undesirable cascading DC voltage drop of other converters. These block and bypass actions are just two available approaches for MMC FCL control. However, these approaches have inevitable drawbacks. Notably, aside from these two approaches, other options with superior MMC performance exist in limiting the fault current. To find and design optimal FCL control approaches, the analytical relations between the DC fault current and SM capacitors should be examined comprehensively. Some important research has been done on the analysis and calculation of the DC fault current [20–24]. In [23], a mathematical approximation of the DC fault current of MMC without converter blocking was proposed by using theoretical analysis and numerical calculation. A generic DC fault current calculation method for DC grids was proposed in [24], wherein the fault current in every branch could be calculated based on the combination of the simplified equivalent model of MMC and the pre-fault and faulted matrices. These analysis and calculation methods are effective and practical. However, the majority of methods are built on the premise that the control of MMC remains the same as normal operations even when DC fault occurs. If the extra FCL control is introduced in MMC, then SM capacitors will exhibit different behaviors, which may be beyond the scope of these analytical methods. This study aims to reveal the connection between SM capacitors and the DC fault current theoretically and provide mathematical support for the design of FCL control. First, two independent base circuit structures and a new variable (duty cycle of the capacitor insertion state in each switching period) are defined comprehensively to represent the varying DC fault transient circuit structure caused by the continuous insertion and bypass of SM capacitors. Second, on the basis of the state–space averaging method, state equations of the DC fault transient circuit are proposed. Accordingly, analytical expressions of the DC fault current and SM capacitor voltage are derived to further analyze of the effect of using SM capacitors on the DC fault current. The rest of this paper is organized as follows: Section 2 presents the analysis of the relations between SM capacitors and DC fault current. Furthermore, the state–space averaging model, averaged circuit model, and time–domain expression of the DC fault current are given. To verify the validation of the proposed analytical expressions, Section 3 presents the simulation results. Finally, Section 4 discusses the conclusions. 2. Analytical relations between SM capacitors and the DC fault current The MMC should continuously operate in the HVDC grid [13,14] and wait for the DC breaker to isolate and clear the DC fault current. Therefore, the structure of the DC fault transient circuit constantly changes because SM capacitors are continuously switched between the insert and bypass states under the MMC control. The time-varying
Fig. 1. Typical circuit diagram of MMC and DC breakers in the HVDC grid. 2
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circuit structure is a main challenge to analyze and model the DC fault transient. To solve this problem, the state–space averaging method is adopted in this study. Two independent base circuit structures and a new variable are introduced to represent the time-varying circuit structure and the dynamics of SM capacitors generally. The state equations of the DC fault transient circuit are proposed and solved in the time domain. The equivalent averaged circuit model is also given. The relation between SM capacitors and the DC fault current are analyzed accordingly.
Le 0 d idc (t ) = 0 Ce dt uc (t )
A2
dx (t ) dt
K
i dc (t ) . u c (t )
Re 0 0 0
(4)
x (t )
Compared with the converter switching process, the DC fault transient process is slow. Hence, the DC fault current and capacitor voltage are modeled by obtaining the average in an interval of length Ts (one switching period). The average of the state vector x(t) can be expressed as
x (t )
2.1. Two independent base circuit structures and the duty cycle
Ts
=
1 Ts
t + Ts t
x ( )d .
(5)
Fig. 3 shows how the state vector x(t) and its average evolve over one switching period. The averaged matrix A is
Theoretically, the number of SM capacitors inserted in one phase unit varies from 0 to 2 N, and contains various combinations. To represent the different time-varying combinations in a unified way, the following independent circuit structures can be chosen as the base:
R e 2ND
A = DA1 + D A2 =
(a) Base Circuit 1: all SM capacitors are inserted. (b) Base Circuit 2: all SM capacitors are bypassed.
D 2N
,
0
(6)
where D′ = 1 − D is satisfied. The state–space averaged model of the DC fault transient circuit can be obtained as follows:
Fig. 2 shows the actual circuit structure and its equivalent two base circuits. Notably, Base Circuits 1 and 2 are mathematically defined to help represent the DC fault transient circuit structure although they may not necessarily appear in real operation. A variable D is defined as the duty cycle of Base Circuit 1 in each switching period. D represents the discharging of SM capacitors. Therefore, by regulating D within the range [0, 1], the time-varying circuit structures can be simplified. For instance, when D = 0.5 is satisfied, 50% of all capacitors are inserted, and the circuit state corresponds to normal operation in steady state. When D = 0 is satisfied, no capacitors are inserted, which corresponds to the bypass action mentioned in Introduction. Notably, the range of D is theoretically defined as [0, 1], thereby comprehensively representing all the possibilities of the complex time-varying DC fault circuit by the two base circuits. To obtain the FCL function, D should be chosen from the range of [0, 0.5].
Le 0 d 0 Ce dt K
i dc (t )
Ts
u c (t )
Ts
Re 2ND
=
D 2N
d x (t ) Ts dt
0 A
i dc (t )
Ts
u c (t )
Ts
x (t ) Ts
. (7)
2.3. Time domain expressions According to the state–space averaged model in Eq. (7), the second order differential equation of the averaged DC fault current can be obtained as follows:
d 2 i dc (t ) dt
Ts
+
Re d i dc (t ) Le dt
Ts
+
D2 i dc (t ) Le Ce
Ts
= 0,
(8)
2.2. State–Space averaged model In the DC fault transient circuit, the state vector x(t) contained two state variables, namely, DC fault current idc (inductor current) and SM capacitor voltage uc. For simplicity, the voltage of all SM capacitors is assumed balanced because the DC fault transient is very short (within a few milliseconds). The state vector x(t) can be obtained as follows:
x (t ) =
idc (t ) . uc (t )
(1)
During the first subinterval, when MMC is in Base Circuit 1 and all capacitors are inserted, the converter is reduced to a linear circuit (R-LC) that can be described by the following state equations:
Le 0 d idc (t ) = 0 Ce dt uc (t ) dx (t ) dt
K
R e 2N 1 2N A1
0
i dc (t ) , u c (t ) x (t )
(2)
where Le is the equivalent inductance, Re refers to the equivalent resistance, and Ce denotes the equivalent capacitance, which can be obtained as follows:
Le = Re =
2L s 3 2Rs 3
Ce =
+ Ldc + Rf . 3Cd 2N
(3)
During the second subinterval, with MMC in Base Circuit 2, the converter is reduced to another linear circuit (R-L) whose state equations are
Fig. 2. Structure and its equivalent of the two base circuits considered in the FCL control strategy. 3
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Fig. 4 shows that the decreased D results in the increase in capacitance and decrease in both the capacitor voltage and DC fault current. The principles are presented as follows. From the perspective of the definition of D, the reduced D indicates that the discharging process of SM capacitors in each switching period is shortened. Thus, fewer capacitors are inserted in the circuit and less energy in capacitors is released. From the perspective of the averaged circuit, the equivalent capacitance is increased as the capacitor voltage is decreased when D is reduced. The contribution of SM capacitors in MMC to the DC fault current then reduces as the DC fault current is consequently reduced. In this section, the analytical expressions of the DC fault current and SM capacitor voltage are formulated under varying D values. The averaged circuit related to different D values is also proposed. The duty cycle D can represent the discharging of SM capacitors. Therefore, the proposed expressions and the averaged circuit can be used to analyze the FCL effect of SM capacitors in a comprehensive manner to provide a mathematical foundation for the design of an optimal FCL control strategy. D is a good tool for controlling the DC fault current.
Fig. 3. State vector and its average evolve over one switching period.
and the initial condition can be expressed as follows:
i dc (0 + ) d i dc (0 + ) Ts dt
Ts
=
= Idc
2DUdc Re Idc , Le
(9)
where Idc and Udc denote the DC current and DC voltage before the DC fault occurs. The characteristic roots are obtained as follows:
p1,2 =
Re ± 2Le
Re 2Le
2
D2 . Le Ce
3. Simulation results To verify the proposed analytical expressions, the MMC system rated at 200 MVA/ ± 160 kV is simulated by using PSCAD/EMTDC. Fig. 5 shows the configuration of the simulated system. Three MMCs share the same parameters listed in Appendix B. The DC circuit breaker (DCCB) adopts the ABB hybrid DC circuit breaker, which is composed of a load commutation switch, an ultrafast disconnector, and a main breaker with hundreds of IGBTs and surge arresters [25]. In the steady state, MMC1 controls the DC voltage, whereas MMC2 and MMC3 control the active power. P2 = P3 = 85 MW and P1 = 170 MW are satisfied.
(10)
To solve Eq. (8), different cases under varying D values are discussed as follows. (1) Underdamped Case: when D >
Re 2 Le / Ce
In this case, the characteristic roots are complex conjugate with a negative real part that can be expressed as
p1,2 =
(11)
± j r.
By solving Eq. (8) under the initial condition of Eq. (9), the time–domain averaged expressions of the DC fault current and SM capacitor voltage can be obtained as
i dc (t ) u c (t )
Ts
Ts
=
t
= Ae
A 2N
Le Ce
e
sin(
rt
t sin(
+ )
rt
+
+ )
3.1. Feasible control strategy to regulate D A feasible control strategy for the duty cycle D is proposed. D is approximately equivalent to the DC modulation index. According to its definition, D denotes the ratio of the sum of two arm voltages in one phase unit and the pole-to-pole DC voltage that is expressed as
, (12)
where parameters are expressed as
A= = arctan
(
=
Idc sin 2 r Le Idc 4DUdc R e Idc
0
)
Re 2Le
r
=
=
D= D2 Le Ce
2 0
= arctan
2 r
2udc (t )
* udc ,
j= a, b, c,
(14)
where ujp and ujn denote the voltage of the upper and lower arms in the phase unit j, respectively; udc is the pole-to-pole DC voltage; and udc* refers to the DC modulation index, that is, the DC component of the arm reference voltage per unit. Under normal operation, D = udc* = 0.5 is generally satisfied. Notably, Eq. (14) is satisfied on the premise that AC components of ujp and ujn cancel each other. However, the control of D inevitably leads to the appearance of the DC offset in the arm reference voltage. Therefore, a dynamic limiter is proposed to guarantee the symmetry of
.
( )
ujp (t ) + ujn (t )
(13)
(2) Overdamped Case and Critically Damped Case As the resistance in the circuit is significantly small, the underdamped case appears frequently. The overdamped and critically damped cases are very rare. The Appendix A shows the deduction of the time–domain averaged expressions of the DC fault current and SM capacitor voltage in the overdamped and critically damped cases. 2.4. Averaged circuit model According to the state–space averaged model, the circuits can be reconstructed to be equivalent to Eq. (7). Fig. 4 shows the averaged circuit model. Compared with Fig. 2, the capacitor in the averaged circuit model becomes variable and controllable. Both the capacitance and voltage of the capacitor are directly related to the duty cycle D. The averaged circuit provides a clear and intuitive way to observe and analyze the effect of the SM capacitor on the DC fault current.
Fig. 4. Averaged circuit model during DC fault transient when FCL control is considered. 4
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Fig. 5. Configuration of the simulated system.
ensure normal operation. At t = 0.8 s, DC fault occurs in DC line 2. After DC fault is detected, MMCs perform the FCL function by changing the setting value of D. Notably, DCCBs are set to not operate in this condition because the characteristic of DC fault current is considered rather than the protection procedure. Section 3.3 presents the coordination of DCCBs and MMC FCL control. As FCL control is activated only after fault detection, the majority of existing fault detection approaches, such as methods based on voltage across DC reactor [15], DC voltage derivative [28], DC current derivative [29], travelling wave [30], and DC reactor voltage change rate [31], can be used in this study. The generated fault detection signal is shared by MMCs and the DCCB. Fig. 8 shows the comparison of simulation and calculation results of MMC1. The DC fault current and the sum of SM capacitor voltages in the upper arm of phase a are demonstrated. After fault detection, MMC1 sets a different duty cycle D with the step by using 0.1 within the range of [0, 1]. For comparison, the simulation results are also included (green line with the × mark) when MMC adopting block is operational. Fig. 8(a) and 8(b) show that the fault detection delay is set to 0 and 1 ms, respectively. When D ∈ [0, 0.5] is satisfied, the DC fault current is limited (shaded
Fig. 6. Control diagram of the simulated MMC.
the AC components of ujp and ujn. The upper and lower limit can be obtained as follows: * u max * umin =
= min ( 2D , 1) max ( 2D
1, 0 )
.
(15)
Fig. 6 shows the control diagram of the simulated MMC. The DC modulation index (udc*) is equivalent to D and shared by six arms. The AC reference voltages (ua*, ub*, uc*) use the results of conventional P/ Q/Udc and current controls. D is then attached to AC reference voltages and processed by the dynamic limiter to generate reference arm voltages (uap*, uan*, ubp*, ubn*, ucp*, ucn*) for modulation. A carrier phaseshifted sinusoidal PWM scheme is used [26]. The switching frequency for each switching device is 300 Hz. Notably, the control strategy presented in this study is a feasible solution. D is manipulated in an open-loop manner. Untreated AC reference voltages are inevitably influenced by the dynamic limiter. In fact, D can be controlled automatically in the closed-loop manner to achieve the online FCL function, and AC reference voltages can be actively limited in the controllable range [27]. The FCL control strategy with good dynamic performance that considers the interactions between DC fault and AC grid will be presented in a future study. To verify the validity of the proposed D control strategy, Fig. 7(a) shows the waveforms of the upper and lower arm reference voltages when D = 0.2, 0.5, 0.8. Fig. 7(b) shows the corresponding amplitude–frequency characteristic of the upper arm reference. The DC component of the arm reference voltage can accurately track the set value of D because the dynamic limiter can effectively guarantee that AC components of both arm references cancel each other. Fig. 7(b) shows that other undesired harmonics (second- and third-order harmonics) are not high although the amplitude of fundamental frequency component of the arm reference voltage is inevitably changed with the varying of D. 3.2. Accuracy of the proposed analytical expressions To verify the proposed transient analytical expressions, calculation results are compared with simulation results under the pole-to-pole DC fault. Before t = 0.8 s, MMC is in the steady state, and D = 0.5 is set to
Fig. 7. Waveforms of upper and lower arm reference voltages when D varies. 5
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Fig. 8. Comparison of simulation and calculation results of MMC1 under varying D.
area). Otherwise, the DC fault current is increased. The FCL effect of the blocking action is close to the FCL effect when D is in the range of [0.1, 0.2]. Fig. 8(a) and 8(b) present that the analytical and simulation results agree well regardless of fault detection delay, thereby validating the accuracy of the proposed analytical expressions.
currents is mild. The overvoltage of the arm inductor (80.95 kV) and DC line (428.12 kV) is also acceptable. Fig. 9(c) and 10(c) present that MMC is bypassed during 0.801–0.803 s, which corresponds to D = 0.0. In this case, the FCL effect is the most remarkable because DC fault is transformed into AC fault. The DC fault current stops increasing immediately and decays slowly. Compared with the no-action case, the DC fault current peak is reduced by 54%, whereas the AC fault current peak is increased by 70%. In addition, the DC voltage is forced to zero, which may result in the change of DC voltages of other converters and lead to an undesirable impact on the protection and recovery of the HVDC grid. Fig. 9(d) and 10(d) show the results when MMC is blocked during 0.801–0.806 s. Six MMC arms become rectifier bridges, and the antiparallel diodes provide the path for the AC fault current to feed into the DC side continuously. Compared with the no-action case, the DC current peak is reduced by 43%, but the overvoltage of the arm inductor is significantly increased by 27%, thus causing an isolation challenge. Fig. 9(b) and 10(b) show the case when the proposed MMC FCL control is activated and D = 0.2 is set during 0.801–0.803 s. Compared with the three approaches, the proposed FCL control can significantly reduce the DC fault current (by 33% compared with no-action) and avoid the undesired overcurrent (bypass action), overvoltage (block action), and zero-voltage (bypass action) problems, thereby indicating that the use of the proposed FCL control strategy and the appropriate selection of the D value can achieve superior FCL effect.
3.3. Comparison of the FCL effect and other protection approaches To show the effect of the proposed FCL control, the simulation results of the proposed FCL control and three approaches (no action, bypass action, and block action) are compared. At t = 0.8 s, DC fault occurs in DC line 2. At t = 0.801 s, DC fault is detected, MMCs starts the FCL control as DCCB3 and DCCB4 interrupt and isolate the fault current. At t = 0.803 s, DC line 2 is isolated and MMC1 stops the FCL control. MMC1 and MMC3 resume power transmission (P1 = P3 = 85 MW, and P2 = 0). The recovery of fault lines is beyond the scope of this study and thus excluded from this paper. Figs. 9 and 10 show the simulation results of MMC1 and DCCB3, respectively. Fig. 9 shows the waveforms of MMC1 DC current, arm reference voltages of phase a, three upper arm, three-phase AC, and DCCB3 currents (load commutation switch current, IGBT current of the main DC breaker, and surge arrester current). Fig. 10 presents the waveforms of MMC1 DC voltage, and the upper and lower arm voltages of phase a. Table 1 lists the peak value of the DC current, AC current, arm current, arm inductor voltage, and DC voltage. Fig. 9(a) and 10(a) show that MMC remains unchanged after DC fault and maintains its continuous operation under the normal steadystate control strategy. In this case, D = 0.5 is constantly satisfied. The DC fault current is thereby not limited and reaches the peak (3.05 kA) at t = 0.803 s. The overcurrent in the arm (1.50 kA) and AC (1.45 kA)
4. Conclusions This study proposes an analytical analysis method for the DC fault transient circuit, in which the SM capacitor dynamics are controllable 6
Electrical Power and Energy Systems 115 (2020) 105444
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Fig. 9. Comparison of the simulation results under different protection approaches: waveforms of the DC current, DCCB currents, arm reference voltages, arm currents, and AC currents.
and considered as the new control object.
(c) Analytical expressions of the DC fault current and SM capacitor voltage are obtained to guide the design of DC FCL control of MMC. (d) The effect of the SM capacitor on the DC FCL control is concluded. The duty cycle D can represent the discharge of SM capacitors and is a good tool for affecting and controlling the DC fault current. The increasing speed of the DC fault current declines with the decrease in D. The DC fault current may decay when D tends toward zero. (e) A feasible control strategy is proposed to regulate D. By appropriately choosing the value of D, the proposed strategy can significantly reduce the DC fault current and avoid the drawbacks of
(a) Two base circuits (all capacitors are either inserted or bypassed) and one duty cycle index (D, approximately equivalent to the DC modulation index) are defined to represent the complex timevarying DC fault transient circuit structure comprehensively. (b) The state equations of the DC fault circuit are obtained based on the state–space averaging method, and the averaged circuit model is established to show the relationship between the SM capacitor and DC fault current intuitively. 7
Electrical Power and Energy Systems 115 (2020) 105444
X. Li, et al.
Fig. 10. Comparison of the simulation results under different protection approaches: waveforms of the DC line and arm inductor voltages. Table 1 Comparison of the FCL Effect of Several Protection Approaches. Approach
DC current peak (kA)
Arm current peak (kA)
AC current peak (kA)
Arm inductor voltage peak (kV)
DC voltage peak (kV)
DC voltage valley (kV)
No action (D = 0.5) Bypass (D = 0.0) Block Proposed FCL (D = 0.2) Proposed FCL (D = 0.1)
3.05 1.41 1.73 2.05 1.72
1.50 1.67 1.73 1.41 1.52
1.45 2.46 1.73 1.48 1.95
80.95 76.97 102.48 79.14 77.13
428.12 423.86 465.50 428.60 428.42
247.78 0.00 25.61 83.49 41.79
the conventional block approach (severe overvoltage on arm inductors and IGBTs directly turning off the high fault current) and the bypass approach (significantly large AC current and zero DC voltage).
Acknowledgements This work was supported by the National Natural Science Foundation of China (51807105), the Science and Technology Project of State Grid of China (52018K170028), and the Power Electronics Science and Education Development Program of Delta Group (DREG2018007).
Declaration of Competing Interest The authors declared that there is no conflict of interest. Appendix A (1) Overdamped Case: when D <
Re 2 Le / Ce
In this case, the characteristic roots are expressed as
p1,2 =
2 0
2
±
=
(A1)
± | r |.
Similarly, the DC fault current and SM capacitor voltage are obtained as follows:
u c (t )
Ts
=
i dc (t ) Ts = A1 e p1 t + A2 e p2 t 1 [A1 (p1 Le + R e ) e p1 t + A2 (p2 Le 2ND
+ R e ) e p2 t ]
,
(A2)
where the parameters are expressed as follows:
A1 = A2 =
2 | r | L e Idc + 4DUdc 4 | r | Le
Re Idc
2 | r | Le Idc 4DUdc + Re Idc 4 | r | Le
2DUdc Re
Idc
2DUdc Re
. (A3)
Notably, when D = 0 is satisfied, the DC fault current differential equation changes from second to first order. Fig. 4 shows that the averaged circuit also becomes a first-order circuit (R-L). Hence, the characteristic roots and corresponding parameters are expressed as follows:
p1 = 0, p2 = 2 . 0 = 0 A1 = 0, A2 = Idc
(A4)
Accordingly, the DC fault current and SM capacitor voltage are obtained as follows:
i dc (t )
Ts
uc (t )
= Idc e Ts
=
Udc N
2 t
.
(A5)
8
Electrical Power and Energy Systems 115 (2020) 105444
X. Li, et al.
(2) Critically Damped Case: when D =
Re 2 L e / Ce
In this case, the characteristic roots are are expressed as
p1 = p2 =
(A6)
.
The time–domain averaged expressions of the DC fault current and SM capacitor voltage are obtained as follows:
i dc (t ) u c (t )
Ts
=
Ts
1 2ND
= (A3 + A 4 t ) e
(2DU
dc
+
4DUdc
t Re Idc
2
)
t e
t
,
(A7)
where the parameters are expressed as follows:
A4 =
A3 = Idc 4DUdc Re Idc 2Le
2DUdc . Le
(A8)
Appendix B See Table B1 Table B1 MMC Parameters Used in the Calculation and Simulation. Parameter
Value
Rated MMC output ac voltage Rated capacity of MMC Rated dc-link voltage of MMC Number of SMs of each arm Inductance of each arm Capacitance of each SM Dc line inductor
166 kV 200 MVA ± 160 kV 133 0.1 H (11%) 5000 μF 0.3 H
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