An optimized 0.3 μm N-MOS transistor

Physica 129B (1985) 291-295 North-Holland, Amsterdam

291

AN OPTIMIZED 0.3 um N-MOS TRANSISTOR G. GUEGAN,J. GAUTIER, M. GUERIN, B. DAL'ZOTTO, F. BUIGUEZ LETI-IRDI, LETI-Commissariat ~ l'Energie Atomique, 85 X, 38041 GRENOBLECEDEX, FRANCE ABSTRACT We present new experimental results on optimized MOS transistor with 0.3 ~m channel length. The channel doping p r o f i l e has been optimized to achieve proper threshold voltage with no punchthrough at 3 V. Devices have been fabricated using NMOSprocess and direct e-beamwriting. These devices have long channel behaviour and their characteristics are compared to C.A.D. models for threshold voltage and drain current. They exhibit transconductance values of 150 mS/mmat room temperature and 205 mS/mmat 77° K.

1. INTRODUCTION During the last few years, a constant and large e f f o r t in the fabrication of very small channel MOSFETsI have been provided to prepare

doping profile. This optimization involves the following criterions : -

The threshold voltage, on account of noise

immunity margins and speed performance, must be

future technologies and to explore device per-

both high enough and lower than one volt. An

formance limitations. The scaling of geometri-

estimate of this threshold voltage was given by

cal dimensions down to submicron requires the

our program for automatic scaling of technolo-

optimization of MOS devices for minimum short-

gies 2 and leads to the choice of values between

channel effect and good current drive capabili-

450 mV and 650 mV for an arbitrary choosen 3 V

ties.

supply voltage.

In this paper, we report experimental results on properly scaled N.MOS transistor. The optimization of the channel doping and the de-

-

No punchthrough current must flow between

source and drain for this supply voltage. - Short channel effects like the threshold

vice fabrication process are discussed respec-

sensitivity to channel lengths or to the drain

t i v e l y in section 2 and section 3. Then,

voltage must be weak.

experimental results and comparison between experimental characteristics and analytical models w i l l be given in section 4. Theoretical and experimental variations of the transconduc-

-

The threshold voltage must be as few sen-

sitive to the substrate bias as possible. The general solution with regard to these constraints is to reduce the source drain junc-

tance with channel lengths at room temperature

tions and the oxide thickness and to optimize

and at liquid nitrogen temperature w i l l be des-

the channel doping profile. The research of the

cribed in section 5.

best compromise between short channel effects,

2. CHANNELDOPING PROFILE OPTIMIZATION

through is the key to optimize the doping pro-

substrate sensitivity and drain-source punchThreshold control and subthreshold perfor-

file.

mances which are key features for VLSI circui-

I f the peak concentration is in the bulk,

try w i l l be improvedwith an optimized channel

the threshold voltage control, that is to say, the f a c i l i t y to have a given threshold voltage

0378-4363/85/$03.30 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

292

G Guegan ct a/ /,,ln oplit~flz.dd O .?#,'n :\-,,$10S U'dnsistor

w i t h no dependence w i t h channel lengths is improved. Whether the implant is shallow or deep, the s u r f a c e - d r a i n - i n d u c e d or the volumedrain-induced barrier lowering will If

dominate.

0.4

the charge under the gate is e s s e n t i a l l y

c o n t r o l l e d by the drain v o l t a g e , the s u s b t r a t e sensitivity

will

0.3

be lower. On the c o n t r a r y , i f

]>

t h i s charge i s e s s e n t i a l l y in the bulk, the drain sensitivity

wil

0.2

be lower. Channel im-

>

p l a n t a t i o n parameters have been obtained from

0.1

SUPREM process s i m u l a t o r and MINIMOS device s i m u l a t o r . Simulations w i t h 2D MOS t r a n s i s t o r analyser show t h a t a deep i m p l a n t , l i k e the boron p r o f i l e

of type 2 in f i g .

i,

0

gives b e t -

t e r t h r e s h o l d voltage c o n t r o l and less t h r e s hold voltage s e n s i t i v i t y (fig.

I

I

1

2

I~

3

VD (V)

to the drain voltage

2) than shallow i m p l a n t . This is due to

a screening e f f e c t of the high dose deep im-

FIGURE 2 Simulated t h r e s h o l d voltage versus drain voltage w i t h L = 0.3 ~m, Hox = 15 nm

p l a n t which prevents p o t e n t i a l l i n e s born in the d r a i n region to reach f a r i n t o the 8

channel.

F-- .G

~10 I;

.4

E o

.2

[]Z

I

Z

2_V B 3(V )

5

10 I~

FIGURE 3 Simulated t h r e s h o l d voltage versus s u b s t r a t e bias v o l t a g e w i t h L = 0.3 um, Hox = 15 nm ,

1015

o

I

.2

,

I

.4

,

I

.6

X(~m)

- For a 0.3 pm channel length MOS t r a n s i s tor,

short channel e f f e c t s ,

t h r e s h o l d voltage

c o n t r o l and consequently substhreshold characFIGURE 1 Simulated boron doping p r o f i l e s

teristics

are improved i f the peak concentra-

t i o n is in the volume. But these advantages will

be paid by more s u b s t r a t e s e n s i t i v i t y

G. Guegan et al. / An optimized 0.31~m N-MOS transistor

(fig. 3). In the case of a shallow implant

Figure 4 is a picture of a typical transis-

(boron p r o f i l e of type 1 in f i g . l ) , the deple-

tor after removing the metal and the interme-

tion thickness which depends directly on the

diate insulator. A 0.4 ~m wide polysilicon

doping p r o f i l e w i l l be higher. Consequently

gate as well as source and drain contact are

the transition of the space charge sharing

visible in the active region.

from a trapezoidal shape to a triangular shape w i l l occur for a lower substrate bias. So, in spite of substrate sensitivity in-

4. EXPERIMENTAL RESULTS Figure 5 and figure 6 show respectively

creasing, the doping p r o f i l e of type 2 in fig.

output characteristics of a .22 um and .30 ~m

1 w i l l be adopted because of its a b i l i t y to

channel length device. The channel width is

provide 0.3 ~m channel length transistor with

8.5 ~m and the oxide thickness 12.5 nm. The

long channel characteristics.

transconductance is independent of the gate voltage, due to the saturation velocity of

3. FABRICATION PROCESS The starting substrate is 6 R.cm p. type

carriers. The corresponding subthreshold characteristics (fig. 7) show that the punch-

silicon. The LOCOSisolation technique leads

through effect and the surface-drain-induced

to a final f i e l d oxide of 500 nm. Three d i f f e -

barrier lowering begin to appear for .22 um

rent oxide thicknesses of 12.5, 15 and 20 nm

channel length device at 4 V drain voltage.

were performed. The channel doping is obtained

For such short channel lengths, the high sen-

by a single implant through the gate oxide.

s i t i v i t y of the threshold voltage to the drain

For all lithographic steps, direct e-beamwri-

voltage explains the weak saturation of the

ting were used to define patterns with HPR po-

output characteristics on figure 5. On the

s i t i v e resist which has been inverted for the

other hand, the substhreshold characteristics

metal level. All layers have been patterned by

of a .30 ~m channel length device which show

reactive ion etching. For scaling considera-

no punchthrough and nearly no effect of the

tion, 0.18 ~m source-drain junction depth is

drain voltage on the weak inversion current

obtained by Arsenic implant with a measured

are in good agreementwith the channel doping

sheet resistance of 78 ~/ .

p r o f i l e optimization given in section 2.

.........

FIGURE 4 Picture of an 0.4 ~m polysilicon - gate line

)

.......

FIGURE 5 I-V characteristics. Device dimensions are L = 0.22 ~m, W= 8.5 ~m, Hox = 12.5 nm

293

294

G. Gucga~t et al. ," Atl :)ptimized O..'~/~mN-MOS traHsistur

VT(VB)-VT(O)

L=100 ~Jm 8.52 i .56

.74

/

,29

C t

~

J

I FIGURE 6 I-V c h a r a c t e r i s t i c s . Device dimensions are L = 0.30 um, W = 8.5 um, Hox = 12.5 nm

Log(I)

-2

(R)

VD=4 V

3

2

4

l

5

-VB (V) FIGURE 8 Threshold v o l t a g e versus s u b s t r a t e bias v o l t a g e w i t h channel lengths as parameter. measured, ×x model

Y3

15

VB =8 V

~0.1

VG=5 V

-6

ClZ

E 10

I

/// /

/

/Jl !

ii ii It

"2 " " "

0

-2

2

4

2

VG (V)

I

FIGURE 7 Subthreshold c h a r a c t e r i s t i c s w i t h VD as a parameter at VB = O, L = 0.30 pm ; - - - L =O.22um

2

3

VD (V) FIGURE 9 I-V c h a r a c t e r i s t i c s . Device dimensions are L = 0.29 pm, W = 18.8 pm, Hox = 15 nm measured, xxx a n a l y t i c a l model, ooo c a l c u l a t e d w i t h MINIMOS

Experimental t h r e s h o l d v o l t a g e c h a r a c t e r i s tics

versus s u b s t r a t e bias f o r d i f f e r e n t

nel l e n g t h s are compared ( f i g . analytical

chan-

8) w i t h an

model 4 t a k i n g i n t o account the non

u n i f o r m doping p r o f i l e

w i t h geometrical ap-

p r o x i m a t i o n of the space charge sharing in the b u l k . This t h r e s h o l d v o l t a g e model can be ea-

a given r a t i o

sily

and the c r i t i c a l

i n c o r p o r a t e d w i t h our a n a l y t i c a l

static

between the l o n g i t u d i n a l field.

field

This C.A.D. model and

c u r r e n t model 5 which is based on the c l a s s i c a l

results

q u a d r a t i c f o r m u l a t i o n and take i n t o account

MINIMOS are in good agreement w i t h e x p e r i m e n t a l

effects

values ( f i g .

of t r a n s v e r s a l

on m o b i l i t y .

and l o n g i t u d i n a l

field

The p i n c h o f f p o i n t is d e f i n e d by

device.

o b t a i n e d w i t h the 2 D device s i m u l a t o r 9) f o r a 0.29 pm channel l e n g t h

G. Guegan et al. / An optimized O,3l~rn N-MOS transistor

295

6. CONCLUSION

5. VARIATIONS OF THE TRANSCONDUCTANCE

Doping p r o f i l e of 0.3 ~m channel length MOS

Fig. 10 shows comparison between t h e o r i t i cal and experimental variations of the trans-

transistor have been optimized to achieve pro-

conductance in the saturation regime with

per threshold voltage with no punchthrough

channel lengths at room temperature and at

current at 3 V. Then, devices with channel

77° K. For long channel devices, the trans-

lengths down to 0.22 ~m have been realized and

conductance is inversely proportional to the

their output characteristics are in good

channel lengths but for short channel a satu-

agreement with this previous optimization.

ration of the transconductance which is due to

These characteristics were compared to C.A.D.

the saturation velocity of carriers is obser-

models of threshold voltage and drain current.

ved. The maximumvalue of this transconductance

Excellent transconductance values of 150 mS/mm

is respectively 150 mS/mmand 205 mS/mmat room

at room temperature and 205 mS/mmat 77° K ha-

temperature and at 77° K for an oxide thickness

ve been obtained.

of 12.5 nm. The two variations of transconductance with channel lengths at room temperature

ACKNOWLEDGEMENTS The authors would l i k e to acknowledge the

and a 77° K which are not parallel clearly show the difference of mechanisms involved in the

different teams of LETI-MSC for device proces-

temperature dependenceof electron mobility and

sing, J.F. Proth who provided valuable assis-

saturation velocity. The values of the satura-

-tance in device simulations, and M. Berthier

tion velocity calculated with parameters of the

for quick and e f f i c i e n t typewritting.

C.A.D. drain current model are 7.106 cm.s-1 at room temperature and 107 cm.s-1

at 77° K. REFERENCES

E

1. W.Fichtner, E.N. Fuls, R.L. Johnston,

leee

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lee Z 0

R.K. Watts, W.W. Weick, Optimized MOSFET's with Subquatermicron Channel Lengths, Tech. Dig. IEDM, 1983, pp. 384-387

', ', ', ',

~

llII,

,~,j,~.

~"'L

03 Z rr OC I,--

I [11"

_77OK

"kl I1 [

llkl

16

1

0.1

L

I

III

_293OK

10

(Hm)

FIGURE 10 Experimental and theoretical variations of the transconductance with channel length theory, .. experiments.

2. J. Gautier, B. Giffard, M. Guerin,

G. Guegan, Expectable Performances of short channel NMOS technologies, E.S.S.C.I.R.C. 1983 3. Selberherr, Schfitz, Potzl, MINIMOS, A two dimensional MOS transistor analyser, IEEE Trans. on Electron Devices, vol. ED 27, N° 8, August 1980

'

J. Gautier, G. Guegan, Threshold voltage modelling of submicron MOS devices with non uniform doping profile, E.S.S.D.E.R.C. 1982

5. J. Gautier, G. Guegan, Experimental and theoritical characterization of very short channel MOS transistors, E.S.S.D.E.R.C. 1983