RF performance of four different Tunneling FETs with the recessed channels

Accepted Manuscript Analog/RF performance of four different Tunneling FETs with the recessed channels

Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen PII:

S0749-6036(16)31197-1

DOI:

10.1016/j.spmi.2016.11.005

Reference:

YSPMI 4639

To appear in:

Superlattices and Microstructures

Received Date:

11 October 2016

Accepted Date:

04 November 2016

Please cite this article as: Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen, Analog/RF performance of four different Tunneling FETs with the recessed channels, Superlattices and Microstructures (2016), doi: 10.1016/j.spmi.2016.11.005

This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

ACCEPTED MANUSCRIPT Research highlights  Analog/RF performance of different TFETs with the recessed channels is studied.  The DUTFET has the maximum transconductance.  The LTFET has the minimum gate-to-drain capacitance.

AC

CE

PT

ED

MA

NU SC RI PT

 The LTFET and DUTFET have better analog and RF performance.

ACCEPTED MANUSCRIPT Analog/RF performance of four different Tunneling FETs with the recessed channels Wei Li, Hongxia Liu*, Shulong Wang*, ShupengChen

NU SC RI PT

School of Microelectronics, Key Laboratory of Wide band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071, China

ABSTRACT

In this paper, the performance comparisons of analog and radio frequency (RF) in the four different tunneling field effect transistors (TFETs) with the recessed channels are performed. The Lshaped channel TFET (LTFET), U-shaped channel TFET (UTFET), U-shaped channel with L-shaped gate TFET (LGUTFET) and U-shaped channel with dual sources TFET (DUTFET) are investigated by using Silvaco-Atalas simulation tool. The transconductance (gm), output conductance (gds), gate

MA

capacitance (Cgg), cut-off frequency (fT) and gain bandwidth product (GBW) are the parameters by analyzed. Among all the considered devices, the DUTFET has the maximum gm and gds due to the improved on-state current by dual sources, and the LTFET has the minimum Cgg because of the

ED

minimum gate-to-drain capacitance (Cgd). Since analog/RF characteristics of a device are proportional to gm and inversely proportional to Cgg, the LTFET and DUTFET have better analog/RF performance compared to the UTFET and LGUTFET. The extracted largest fT is 3.02GHz in the LTFET and the

PT

largest GBW is 1.02GHz in the DUTFET. The simulation results in this paper can be used as a reference to choose the TFET among these four TFETs for analog/RF applications.

CE

Keywords：Tunneling field effect transistor (TFET), gate capacitance, cut-off frequency, gain bandwidth product

Introduction

AC

1.

Reducing the size of metal oxide semiconductor field-effect transistor (MOSFET) achieves

enabled extraordinary improvements in chip density, switching speed and operating power [1,2]. However, the aggressive scaling of conventional MOSFETs to nanometer scale has led to short channel effects such as drain induced barrier lowering (DIBL), hot electron effect, high leakage current, *

Corresponding authors. E-mail address: [email protected] (Hongxia Liu) 1

[email protected] (Shulong Wang)

ACCEPTED MANUSCRIPT subthreshold swing limits of 60mV/dec at room temperature, etc [3-5]. Among all the alternative devices, tunneling field effect transistor (TFET) has been proved to be potential candidate for the next generation applications of low power and high frequency due to its lower subthreshold swing (SS), extremely low off-state current and robustness SCEs [1,6,7]. The reason of performance improvements

NU SC RI PT

in TFETs is band-to-band tunneling (BTBT) instead of hot electron emission acts as the main operation mechanism in TFETs [8-10]. However, the low on-state current and ambipolar behavior are inherent disadvantages in the traditional TFETs. In order to solve these problems, various novel device structures have been proposed such as L-shaped channel TFET (LTFET) [11,12], U-shaped channel TFET (UTFET) [13], U-shaped channel with L-shaped gate TFET (LGUTFET) [14] and U-shaped channel with dual sources TFET (DUTFET) [15]. What these four TFETs have in common are that their channels are recessed in the substrates and that they transform planar p-i-n TFETs which are based on the tunneling of parallel to channel into vertical TFETs which are based on the tunneling of perpendicular to channel. Therefore, the tunneling area and on-state current increase. In addition, it has

MA

been demonstrated that a thin n+ pocket between the source and the channel can effectively improve device performance [13,16,17]. Therefore, the n+ pocket is also inserted in the LTFET, UTFET, LGUTFET and DUTFET so that the BTBT takes place for perpendicular and parallel to the channel.

ED

The DC characteristics including Ion/Ioff and SS in TFETs have already been studied widely. However, only a few references focus on the analog/RF performance of traditional TFETs [2,18-21]. In

PT

this paper, for the first time, the analog/RF performance of the LTFET, UTFET, LGUTFE and DUTFET proposed is compared. A comprehensive and quantitative analysis of the key analog/RF

CE

figures-of-merit such as transconductance (gm), output conductance (gds), gate-to-drain capacitance (Cgd), gate-to-source capacitance (Cgs), gate capacitance (Cgg), cut-off frequency (fT) and gain bandwidth product (GBW) is performed. The device with the best analog/RF characteristic is obtained

AC

by comparison.

This paper is organized as follows: In sectionⅡ,the device structures and simulation methods are

given. Section Ⅲ describes the simulated results including input and output characteristics, capacitance and frequency characteristics. Finally, the main conclusions is presented in section Ⅳ. 2.

Device structures and simulation methods

Fig. 1 shows the schematics of the silicon-based LTFET, UTFET, LGUTFET and DUTFET. The 2

ACCEPTED MANUSCRIPT n+ pockets are inserted between the source regions and gate oxide layers in the devices, which can induce the energy to bend significantly at tunneling junctions and decrease tunneling barrier width. Therefore, electron BTBT rate and tunneling current are increased. Unlike the planar TFETs, the channels of these four devices are recessed into the substrates, which transforms the lateral p-i-n

NU SC RI PT

configurations into vertical direction [13]. This design magnifies the tunneling areas and increases the on-state current. The drain region of the UTFET is located at the top of the substrate to extend the offstate drain current path. As a result, the UTFET can obtain the lower off-state drain current than the LTFET. The difference between the LTFET and the LGUTFET is that the gate of the LGUTFET overlaps with the pocket regions in the lateral direction besides the vertical direction. The research results has demonstrated that the overlap regions of the gate and pocket in the lateral direction increase the electric field at the top of tunneling junction [14]. Since the generation rate of BTBT is a strong function of electric field, the enhanced electric field at the top of tunneling junction increases the tunneling current [14]. In the DUTFET, the symmetric dual source regions are located in the both sides

MA

of the gate, which makes the electron BTBT take place in both sides of the gate. Consequently, the

CE

PT

ED

DUTFET can further enhance the tunneling area and tunneling current.

(b)

AC

(a)

(c)

(d)

Fig. 1. Schematics of the (a) LTFET, (b) UTFET, (c) LGUTFET and (d) DUTFET. 3

ACCEPTED MANUSCRIPT In this paper, the four devices mentioned above are studied using 2D device simulator-Silvaco Atlas. By the small signal AC simulation at an operating frequency of 1MHz, the analog and RF performance of these four devices is investigated and the optimal candidate for analog/RF circuits’ applications is obtained. In all the simulations, the nonlocal BTBT model is used. Because the nonlocal

NU SC RI PT

BTBT model takes into account the spatial variation of the energy band, it can model the tunneling process more accurately. The effects of highly doped source, drain and pocket regions are taken into consideration by using bandgap narrowing model and Fermi-Dirac statistics. Moreover, the ShockelyRead-Hall and Lombardi mobility models are adopted in the simulations. The default values are considered for tunneling mass of electron (me) and hole (mp). All the simulation parameters are shown in Table 1.

Table 1. Parameters used for the simulations. Value

Gate length (Lg)

10nm

Gate height (Hg)

60nm

Device width

1μm

Gate oxide (HfO2) thickness (Tox)

2nm

Source doping concentration

1×1020/cm3

Pocket thickness (Tp)

5nm

Drain doping concentration

1×1018/cm3

Source height (Hs)

40nm

Pocket doping concentration

1×1019/cm3

20nm

Gate workfunction

4.4eV

ED

Drain height (Hd)

Value

Overlap length (Lov) in LGUTFET

7nm

Simulation results and discussions

PT

3.

Parameter

MA

Parameter

CE

3.1. Input characteristics

Fig. 2 shows the transfer characteristics for the LTFET, UTFET, LGUTFET and DUTFET at Vd =0.5V. It can been clearly seen that the DUTFET has the greatest on-state (Vd=0.5V, Vg=1V) drain

AC

current. The on-state drain current of three others is about 15μA, which is a 10μA less than that of the DUTFET. From the logarithmic coordinate in Fig. 2, it can be found that curves of transfer characteristics almost have the same bending degree. Therefore, these four devices almost have the same average subthreshold swing (SS).When the gate voltage is varied from 0V to 0.6V, the average SS of all devices is less than 45mV/dec. This is because that the tunneling process of these four devices are identical, which mainly takes place at highly doped p-n junction formed between p+ source region

4

ACCEPTED MANUSCRIPT and n+ pocket region. The tunneling areas of the LTFET, UTFET and LGUTFET are equivalent. Moreover, due to the overlapping of lateral gate and pocket regions in the LGUTFET, the electric field at the top of tunneling junction is enhanced. Therefore, the on-state drain current of LGUTFET is slightly larger than that of the UTFET and LTFET, which can be seen in the inset of Fig. 2. However,

NU SC RI PT

the dual source regions of the DUTFET make the tunneling process generate at the both sides of the gate, which effectively increases the tunneling area in the DUTFET. Therefore, the dual sources is the

MA

optimal technology to raise the on-state drain current.

Fig. 2. Simulated transfer characteristics for the LTFET, UTFET, LGUTFET and DUTFET.

Transconductance (gm) is an important parameter to evaluate analog performance, which is

ED

defined as the slope of transfer characteristics [20]. It is extracted using the following equation：

dI d dVg

(1)

AC

CE

PT

gm 

Fig. 3. Simulated transconductance characteristics for the LTFET, UTFET, LGUTFET and DUTFET at Vd=0.5V.

Transconductance of the device depends on the value of drain current. The device with higher drain current has higher transconductance. The higher gm means more efficient amplification and more suitability for analog applications [22]. Fig. 3 shows the transconductance characteristics for the 5

ACCEPTED MANUSCRIPT LTFET, UTFET, LGUTFET and DUTFET at Vd=0.5V. According to the linear coordinate in Fig. 3, the slopes of the curves increase when the gate voltage increasing from 0.6V. Therefore, gm of these four devices also increases with gate voltage increasing. The maximum value of gm is obtained at Vg=0.9V. Because the DUTFET has the maximum drain current, it has the largest gm. In the LTFET,

NU SC RI PT

UTFET and LGUTFET, almost the same drain current variations with the gate voltages make them have the nearly identical gm.

It can be concluded that DUTFET has the highest drain current and gm as compared to other three counterparts. So, the DUTFET shows the better analog performance. 3.2. Output characteristics

In this section, the output characteristics including drain current versus drain voltage and output conductance are discussed. Fig. 4 shows simulated drain current versus drain voltages for the LTFET, UTFET, LGUTFET and DUTFET at Vg=1V. The drain current increase with drain voltage increasing.

MA

The drain current reaches to saturation at Vd=0.7V. For a specified gate voltage, more drain voltage works on the tunneling junction when the drain voltage increasing, which induces the energy band to bend significantly at tunneling junction. Fig. 5 shows the variations of energy band diagrams from

ED

source to pocket with different drain voltages for the LTFET, UTFET, LGUTFET and DUTFET at Vg=1V. The insets in the figures show the locations of the cutline. For all the devices, when the drain

PT

voltage increasing from 0.2V to 0.6V, the bending degree of energy band increases, but the increasing tends to saturation at Vd=0.6V. Therefore, drain current starts to saturate when the drain voltage

AC

CE

reaches to 0.7V.

Fig. 4. Simulated drain current versus drain voltage for the LTFET, UTFET, LGUTFET and DUTFET at Vg=1V.

In addition, Fig. 4 also shows that DUTFET has no identical output characteristic compared with 6

ACCEPTED MANUSCRIPT the LTFET, UTFET and LGUTFET. The DUTFET has the largest drain current at Vg=Vd=1V because more tunneling area caused by dual sources, which has been discussed above. Fig. 4 also shows that the pinch-off voltage of all the devices is nearly identical and it is about 0.7V. So, the curve slope of the DUTFET is larger compared to other counterparts before saturation. It demonstrates that the

NU SC RI PT

controlling ability of drain voltage to drain current in the DUTFET is greater, which can be explained

ED

MA

by the output conductance.

PT

Fig. 5. Variations of energy band diagrams from source to pocket with different drain voltages for the (a) LTFET, (b) UTFET, (c) LGUTFET and (d) DUTFET at Vg=1V.

CE

The output conductance (gds) is a significant parameter. The relationship between the output conductance and drain voltage at Vg=1V is shown in Fig. 6. The gds in the figure is extracted by using

AC

the following equation:

g ds 

dI ds dVds

(2)

The gds represents the slope of drain current versus drain voltage. Fig. 6 shows that gds increases

with drain voltage increasing. When the drain voltage is greater than 0.5V, gds decrease with drain voltage increasing. Because the higher differential drain current, gds of the DUTFET is the greatest. Moreover, the output resistance (Ro) is calculated as the inverse of the gds and the variations of Ro with respect to the variations of drain voltage are also shown in Fig. 6. The value of Ro is determined by the 7

ACCEPTED MANUSCRIPT series combination of tunneling resistance and channel resistance [23]. When the drain voltage is less than 0.7V, many electrons generated by tunneling junction cannot be completely collected by the drain region, the Ro is mainly determined by the tunneling resistance. So the values of Ro are very small when the devices are not at the saturation region. However, when the devices are at the saturation region

NU SC RI PT

(Vd>0.7V), the electrons generated by tunneling junctions are nearly completely collected by drain regions. Therefore, Ro is mainly determined by the channel resistance close to the drain region when the devices are at the saturation region. It can be concluded that DUTFET and UTFET have the

MA

minimum and maximum channel resistance in saturation region, respectively.

Fig. 6. Simulated output conductance and resistance versus drain voltage

ED

for the LTFET, UTFET, LGUTFET and DUTFET at Vg=1V.

3.3. Capacitance characteristics

PT

The intrinsic gate capacitance is an important parameter for the RF performance analysis [22]. The parasitic gate capacitance determines the switching frequency of digital circuits and amplification ability of analog circuits. The gate capacitance (Cgg) distribution of TFETs is different from that of the

CE

MOSFETs. The gate-to-drain capacitance (Cgd) is the dominate component of gate capacitance (Cgg), whereas gate-to-source capacitance (Cgs) is negligible in both linear and saturation region [24]. The

AC

intrinsic gate capacitance (Cgg) is extracted from signal AC device simulation at frequency of 1MHz. Fig. 7 shows the capacitance versus gate voltage characteristics of the LTFET, UTFET,

LGUTFET and DUTFET at Vds=0V and Vds=0.5V. For all the devices, the Cgd reflects the entire gate capacitance and the Cgs remains very small due to the tunneling barrier of the source. It is worth noting that even drain voltage increase to 0.5V, the gate capacitance is dominated by Cgd. For the LTFET and DUTFET, when the gate voltage is less than 0.2V for Vd=0V and the gate voltage is less than 0.78V for Vd=0.5V, Cgs has higher value compared to Cgd. At this point Cgg is dominated by Cgs for the LTFET 8

ACCEPTED MANUSCRIPT and DUTFET. For the UTFET and LGUTFET, both Cgs and Cgd are very small when the gate voltage is less than 0.7V. Because the drain region of the LTFET and DUTFET is different from that of the UTFET and LGUTFET, the overlap gate-to-drain capacitance is very small for the LTFET. For the DUTFET, the overlap gate-to-drain capacitance is series capacitance of the oxide capacitance and

NU SC RI PT

intrinsic silicon capacitance. So, gate-to-drain overlap capacitance of the DUTFET is also very small. When the gate voltage is lower, higher tunneling barrier makes a few electrons generated by source junction, therefore, Cgs and Cgd mainly depend on the overlap capacitances when gate voltage is lower. Because overlap capacitance of Cgd is smaller than that of Cgs for the LTFET and DUTFET, Cgs is larger than Cgd at a lower gate voltage. For higher gate voltage, there are more electrons tunneling from source to channel and they are collected by drain region, which makes intrinsic Cgd increase extremely and Cgg is dominated by Cgd for all the devices. Whereas the overlap Cgd in the LGUTFET and UTFET is larger than that of the LTFET and DUTFET, so Cgd is almost the same as Cgs at lower gate voltage

AC

CE

PT

ED

MA

for the LGUTFET and UTFET.

Fig. 7. Simulated capacitance-voltage characteristics of the (a) LTFET, (b) UTFET, (c) LGUTFET and (d) DUTFET.

In addition, the pinch-off point is pushed to higher value of Vds for higher Vgs in TFETs. For higher Vgs, there is a higher band bending at the source junction, so a larger percentage of the drain to source bias appears to the source side. For a given Vgs, the drain voltage continues to impact the 9

ACCEPTED MANUSCRIPT tunneling barrier width of the source side until Vds reaches to pinch-off point, beyond which the pinchoff finally starts to set in and Cgd starts to decrease. It can be clearly seen in Fig. 8, which plots the Cgd as a function of the drain voltage for different gate voltages. For Vg=1V, Cgd starts to decrease dramatically when the drain voltage exceeds 0.5V. However, the drain voltage that Cgd starts to

NU SC RI PT

decrease dramatically decreases with gate voltage decreasing. This phenomenon is applicable for all the

ED

MA

devices.

Fig. 8. Simulated Cgd as a function of drain voltage at different gate voltages

PT

for (a) LTFET, (b) UTFET, (c) LGUTFET and (d) DUTFET. Table 2. Extracted capacitance parameters at Vg=1 for the LTFET, UTFET, LGUTFET and DUTFET.

Vd=0.5V

Device name

Vd=0V

Cgs (fF/μm)

Cgd (fF/μm)

Cgg (fF/μm)

Cgs (fF/μm)

Cgd (fF/μm)

LTFET

4.25

0.99

3.39

5.32

0.10

5.22

UTFET

8.76

1.20

7.75

10.16

0.10

10.06

LGUTFET

9.16

1.35

7.80

10.58

0.17

10.41

DUTFET

8.30

1.90

6.67

10.12

0.20

9.91

AC

CE

Cgg (fF/μm)

In conclusion, because the LTFET has the least overlap area of gate to drain, its Cgd and Cgg are the least compared to other counterparts. Both the UTFET and LGUTFET have almost the same overlap area of the gate to drain as gate to source, so their capacitance characteristics are identical. Although Cgs of the DUTFET is the largest, its overlap Cgd is less than that of the UTFET and 10

ACCEPTED MANUSCRIPT LGUTFET and larger than that of the LTFET, so its capacitance characteristic is almost the same as that of the UTFET and LGUTFET. The capacitance parameters of all the devices at Vg=1V are shown in Table 2.

NU SC RI PT

3.4. Frequency characteristics The frequency including cut-off frequency (fT) and gain bandwidth product (GBW) are vital figures of merit in the presentation of device frequency performance for RF applications. The cut-off frequency depends on the ratio of gm to the total capacitance and can be defined as

fT 

2 Cgs

gm gm gm   1  2Cgd / Cgs 2  Cgs  Cgd  2 Cgg

(3)

The gain bandwidth product, for a certain DC gain is 10, is defined by fA=gm/2π10Cgd

(4)

Fig. 9 shows the comparisons of fT as a function of gate voltage for different devices. The fT

MA

increases with gate voltage increasing when the gate voltage is less than 0.8V. Because increasing onstate current causes gm to increase, gm plays the important role in determining cut-off frequency when the gate voltage is less than 0.8V. When the gate voltage is larger than 0.8V, fT falls with gate bias

ED

increasing. The gate field makes the mobility degradation, which causes the combined effect of the increasing of Cgd and the limitation of gm. It is observed that higher cut-off frequency is obtained for the

AC

CE

greatest gm.

PT

LTFET and DUTFET. Because the LTFET has the least gate capacitance and the DUTFET has the

Fig. 9. Simulated cut-off frequency versus gate voltage for the LTFET, UTFET, LGUTFET and DUTFET.

Fig. 10 shows the comparisons of GBW as a function of the gate voltage for different devices. The variation tendencies of GBW are the same as that of cut-off frequency. The maximum GBW is 11

ACCEPTED MANUSCRIPT obtained at Vg=0.62V for all the devices. Since the LTFET and DUTFET have advantages of the gateto-drain capacitance and gm respectively over the UTFET and LGUTFET, they have higher GBW. By comparing fT and GBW with different devices, the LTFET and DUTFET have better frequency characteristics. The LTFET has the best cut-off frequency because it has the least gate capacitance. The

NU SC RI PT

DUTFET has the maximum GBW because it has the better input characteristic.

Fig. 10. Simulated gain bandwidth product versus gate voltage for the LTFET, UTFET, LGUTFET and DUTFET.

MA

In conclusion, the LTFET and DUTFET are the better candidates as the new generation devices for analog/RF applications. However, the maximum cut-off frequency and gain bandwidth product are only 3.02GHz and 1.02GHz, respectively. Using the heterojunction between source and channel and

ED

narrow bandgap materials such as SiGe and InAs in source region can decrease tunneling barrier width and improve the on-state current and transconductance. As a result, the future work should focus on

PT

using of narrow bandgap materials in source region and heterojunction between source and pocket to further improve their analog/RF performance. Conclusions

CE

4.

In this paper, the analog and RF performance of the LTFET, UTFET, LGUTFET and DUTFET

AC

whose channels are recessed into the substrates are investigated by Silvaco-Atlas simulation tool. The important parameters such as transconductance (gm), output conductance (gds), gate capacitance (Cgg), cut-off frequency (fT) and gain bandwidth product (GBW) are analyzed. The DUTFET has the maximum gm and gds due to the more tunneling areas caused by dual sources. The LTFET has the minimum Cgg among all the considered devices. And the dominated gate-to-drain capacitance (Cgd) in the LTFET is minimum, which is caused by less overlap area of gate and drian. So the frequency characteristics of the LTFET and DUTFET are better than that of other structures. The LTFET obtains 12

ACCEPTED MANUSCRIPT the maximum fT of 3.02GHz. The DUTFET obtains the maximum GBW of 1.02GHz. Therefore, the LTFET and DUTFET can be used as the potential TFETs for the analog and RF applications. Acknowledgements

NU SC RI PT

This work was supported by the National Natural Science Foundation of China [grant numbers 61376099, 61434007 and 61504100]; the Foundation for Fundamental Research of China [grant numbers JSZL2016110B003].

References

[1] M. Ionescu, H. Riel, Ionescu, Tunnel field-effect transistors as energy-efficient electronic switches, Nature 479 (2011) 329-337.

[2] V. Vijayvargiya, S. K. Vishvakarma, Effect of drain doping profile on double-gate tunnel fieldeffect transistor and its influence on device RF performance, IEEE Trans. Nanotechnol. 13 (2014)

MA

974-981.

[3] S. Bangsaruntip, G. M. Cohen, A. Majumdar, J. W. Sleight, Universality of short-channel effects in undoped-body silicon nanowire MOSFETs, IEEE Electron Device Lett. 31 (2010) 903-905.

ED

[4] K. K. Young, Short-channel effect in fully-depleted SOI MOSFETs, IEEE Trans. Electron Devices 36 (1989) 399-402.

[5] H. Masuda, M. Nakai, M. Kubo, Characteristics and limitation of scaled-down MOSFET's due to

PT

two-dimensional field effect, IEEE Trans. Electron Devices, 26 (1979) 980-986. [6] K. Boucart, A. M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans.

CE

Electron Devices 54 (2007) 1725-1733. [7] E. H. Toh, G. H. Wang, G. S. Samudra, Y. C. Yeo, Device physics and design of double-gate

AC

tunneling field-effect transistor by silicon film thickness optimization, Appl. Phys. Lett. 90 (2007), 263507-1-263507-3.

[8] W. Y. Choi, B. G. Park, J. D. Lee, T.-J. K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) Less than 60 mV/dec, IEEE Electron Device Lett. 28 (2007) 743–745.

[9] K. Ganapathi, S. Salahuddin, Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high on current, IEEE Electron Device Lett. 32 (2011) 689-691. [10] P. Wang, B. Tsui, Band engineering to improve average subthreshold swing by uppressing low 13

ACCEPTED MANUSCRIPT electric field band-to-band tunneling with epitaxial tunnel layer Funnel FET structure, IEEE Trans. Nanotechnol. 15 (2016) 74-79. [11] S. W. Kim, W. Y. Choi, M. C. Sun, H. W. Kim, B. G. Park, Design guideline of Si-based Lshaped tunneling field-effect transistors, Jpn. J. Appl. Phys. 51 (2012) 06FE09-1–06FE09-4.

NU SC RI PT

[12] S. W. Kim, J. H. Kim, T. J. K. Liu, W. Y. Choi, B. G. Park, Demonstration of L-shaped tunnel field-effect transistors, IEEE Trans. Electron Devices 63 (2016) 1774-1778.

[13] W. Wang, P. F. Wang, C. M. Zhang, X. Lin, X. Y. Liu, Q. Q. Sun, P. Zhou, D. W. Zhang, Design of U-shape channel tunnel FETs with SiGe source regions, IEEE Trans. Electron Devices 61 (2014) 193-197.

[14] Z.Yang, Tunnel Field-Effect Transistor With an L-shaped Gate, IEEE Electron Device Lett. 37 (2016) 839-842.

[15] Z. Jiang, Y. Q. Zhuang, C. Li, P. Wang, Y. Q. Liu, Vertical-dual-source tunnel FETs with steeper subthreshold swing, Journal of Semiconductors, 37 (2016) 094003-1-094003-7.

MA

[16] W. Cao, C. J. Yao, G. F. Jiao, D. Huang, H. Y. Yu, and M.-F. Li, Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure, IEEE Trans. Electron Devices 58 (2011) 2122-2126.

ED

[17] D. B. Abdi, M. J. Kumar, “In-built N+ pocket p-n-p- n tunnel field-effect transistor, IEEE Electron Device Lett. 35 (2014), 1170-1172.

PT

[18] M. W. Akram, B. Ghosh1, Analog performance of double gate junctionless tunnel field effect transistor, Journal of Semiconductors, 35 (2014) 67400-1-67400-5.

CE

[19] K. Nigam, P. Kondekar, D. Sharma, DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor, Superlattices Microstruct. 92 (2016), 224-231.

AC

[20] G. Singh, S. I. Amin, , S. Anand, R. K. Sarin, Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation, Superlattices Microstruct. 92 (2016), 143-156.

[21] S. Ahish1, D. Sharma, Y. B. N. Kumar, M. H. Vasantha, DC and analogue/radio frequency performance optimisation of heterojunction double-gate tunnel field-effect transistor, Micro. Nano. Lett. 11 (2016) 407 - 411. [22] S. K. Gupta, S. Baishya, Analog and RF performance evaluation of dual metal double gate high-k stack (DMDG-HKS) MOSFETs, J. Nano Electron. Phys. 5 (2013). 14

ACCEPTED MANUSCRIPT [23] A. S. Verhulst, W. G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel Filed-effect transistor without gate-drain overlap, Appl. Phys. Lett. 91 (2007) 053102-1-053102-3. [24] S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, Effective capacitance and drive current for

AC

CE

PT

ED

MA

NU SC RI PT

tunnel FET (TFET) CV/I estimation, IEEE Trans. Electron Devices 56 (2009) pp. 2092-2098.

15

NU SC RI PT

ACCEPTED MANUSCRIPT

AC

CE

PT

ED

MA

Fig. 2. Simulated transfer characteristics for the LTFET, UTFET, LGUTFET and DUTFET.

NU SC RI PT

ACCEPTED MANUSCRIPT

Fig. 6. Simulated output conductance and resistance versus drain voltage for the LTFET, UTFET, LGUTFET and

AC

CE

PT

ED

MA

DUTFET at Vg=1V.

NU SC RI PT

ACCEPTED MANUSCRIPT

AC

CE

PT

ED

MA

Fig. 4. Simulated drain current versus drain voltage for the LTFET, UTFET, LGUTFET and DUTFET at Vg=1V

MA

NU SC RI PT

ACCEPTED MANUSCRIPT

Fig. 5. Variations of energy band diagrams from source to pocket with different drain voltages for the (a) LTFET,

AC

CE

PT

ED

(b) UTFET, (c) LGUTFET and (d) DUTFET at Vg=1V.

MA

NU SC RI PT

ACCEPTED MANUSCRIPT

Fig. 8. Simulated Cgd as a function of drain voltage at different gate voltages for (a) LTFET, (b) UTFET, (c)

AC

CE

PT

ED

LGUTFET and (d) DUTFET.

NU SC RI PT

ACCEPTED MANUSCRIPT

AC

CE

PT

ED

MA

Fig. 10. Simulated gain bandwidth product versus gate voltage for the LTFET, UTFET, LGUTFET and DUTFET.

NU SC RI PT

ACCEPTED MANUSCRIPT

AC

CE

PT

ED

MA

Fig. 9. Simulated cut-off frequency versus gate voltage for the LTFET, UTFET, LGUTFET and DUTFET.

MA

NU SC RI PT

ACCEPTED MANUSCRIPT

Fig. 7. Simulated capacitance-voltage characteristics of the (a) LTFET, (b) UTFET, (c) LGUTFET and (d)

AC

CE

PT

ED

DUTFET.

NU SC RI PT

ACCEPTED MANUSCRIPT

AC

CE

PT

ED

MA

Fig. 3. Simulated transconductance characteristics for the LTFET, UTFET, LGUTFET and DUTFET at Vd=0.5V.

NU SC RI PT

ACCEPTED MANUSCRIPT

(b)

(c)

ED

MA

(a)

(d)

AC

CE

PT

Fig. 1. Schematics of the (a) LTFET, (b) UTFET, (c) LGUTFET and (d) DUTFET.