Analysis and design of a 1.0-V CMOS mixer based on variable load technique

Microelectronics Journal 43 (2012) 1003–1009

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Analysis and design of a 1.0-V CMOS mixer based on variable load technique Bao-Lin Wei a,n, Yu-Jie Dai b a b

College of Information and Communication, Guilin University of Electronic Technology, Guilin 541004, China Institute of Microelectronics, Nankai University, Tianjin 300457, China

a r t i c l e i n f o

abstract

Article history: Received 2 November 2011 Received in revised form 16 July 2012 Accepted 24 July 2012 Available online 15 August 2012

A CMOS active mixer based on variable load technique which can operate at 1.0 V supply voltage is proposed and its operation principle, noise and linearity analysis are presented. Different from the conventional Gilbert mixer based on RF current-commutating, the proposed mixer controls the load impedance according to the LO signal. It has only two stacked transistors at each branch which is suitable for low-voltage applications. The mixer was fabricated in 0:18-mm 1P6M CMOS process and measured in 2.4-GHz ISM band. With an input 2.440 GHz RF signal and a 2.442 GHz LO signal, the conversion gain is 5.3 dB, the input-referred third-order intercept points is 4.6 dBm, the input-referred 1 dB compression point is  7.4 dBm, and the single-sideband noise figure is 21.7 dB. Total DC current consumption is 3.5 mA. & 2012 Elsevier Ltd. All rights reserved.

Keywords: Mixer CMOS Low-voltage Variable load technique

1. Introduction Highly integrated, low voltage and low power are the essential goals in integrated circuit design. These characteristics are especially critical in mobile wireless communication systems due to the limitation of battery capacity. With the reducing scale of CMOS technologies, the key problem of migration to advanced CMOS technologies comes from continual reduction in supply voltages, resulting in poor performance in analog and RF circuits [1,2]. Insufficient voltage headroom results in some circuit topologies unable to satisfy the required specifications or even unable to operate. Hence, research for low-voltage circuit topologies is important [1–7]. Mixer is the core component in both transmitter and receiver, it operates with low supply voltage and low power. The Gilberttype mixer is the most mature mixer architecture widely used as the down-converter in CMOS superheterodyne receiver. In this type of mixer, the gm stage are stacked on top of the current source tail, the switching pairs are stacked on top of the gm stage, and finally, the load are placed on top of the switching transistors. Due to large number of stacked transistors at a low voltage supply and the voltage drops across the load resistors, the switching transistors and the transistors in the transconductor become critical, so this architecture cannot be used in CMOS advanced technologies which work with low supply voltage below 1 V [1,2]. To reduce the supply voltages, some folded mixer architectures have been investigated in [2,5], they can work well with 1.0 V

n

Corresponding author. Tel.: þ86 773 2293189. E-mail addresses: [email protected], [email protected] (B.-L. Wei).

0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.07.015

supply voltage. However, as mentioned in [1], for the folded mixer in [2]: (1) The peak-to-peak amplitude of LO signal is lower than supply voltages. (2) The circuit cannot be easily biased, in spite of the fact that the linearity and especially IIP3 performance of this circuit depends on proper biasing of transistor and switching section. (3) The switches are biased at non-zero drain current, which contributes more flicker noise to the output and increases the mixer’s noise figure. The linearity of the folded mixer in [5] is very low. Moreover, it consumes too large DC current, and the noise figure will be large for low RF signal level. A folded-cascode even harmonic mixer (FEHM) for low-voltage was investigated in [6]. It can operate in 0.9-V low voltage, but the frequency-doubling technique must be employed in the local oscillator (LO) stage to produce a LO double-frequency signal, and two LC-tanks have to be adopted to reduce the voltage headroom and select the LO double-frequency signal, which would enlarge the chip area. Moreover, to improve the linearity and avoid gain degradation, an off-chip resistor-turning network composed of two large resistors has been adopted between the output of the current reuse circuit and the input of the buffer, and the IIP3 performance is strongly dependent on the value of the resistorturning network and the DC bias voltage of RF stage and LO stage. Another candidate for low-voltage application is the switched transconductor mixer [7], it utilizes switches connected to the supply voltage. The source of the gm stage is switched to the ground and V dd,sw in each LO period, which will generate considerable switching noise. Moreover, as the 1/f noise of gm stage is mixed up, and the mixer needs two DC supply voltages (i.e. Vdd and V dd,sw ). In this work, a low-voltage CMOS down-conversion mixer controlling its variable load according to the LO signal to achieve

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B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

mixing is proposed. It was implemented in 0:18-mm 1P6M CMOS process and measured in 2.4-GHz ISM band. We focus on the operation principle and measurement results of the mixer in [8], the noise and linearity analysis of this are focused on in this paper. This paper is organized as follows: The proposed active variable load mixer core’s operation principle and its conversion gain are presented in Section 2. In Section 3, the noise and linearity of the mixer are analyzed. The design process and the experimental results of the proposed mixer are shown and discussed in Section 4. Finally, Section 5 is the conclusion of this paper.

Transistor M1 acts as the transconductance (gm) stage, and operates in saturation region. To derive the down-conversion output voltage of the circuit, focusing on RF input and IF output frequencies, vRF(t) and vo(t) are expressed as vRF ðtÞ ¼ vrf expðjoRF tÞ,

ð6Þ

vo ðtÞ ¼ vo,rf expðjoRF tÞ þvo,if expðjðoRF oLO ÞtÞ:

ð7Þ

The relationship among vrf, vo,rf and vo,if in Fig. 1(a) can be written as vo,rf expðjoRF tÞ þ vo,if expðjðoRF oLO ÞtÞ ¼ Z L ðoRF Þ½g mN vrf expðjoRF tÞ þ g L,0 vo,rf expðjoRF tÞ

2. Operation principle of the proposed mixer The single balanced version of the proposed mixer enhances suitability for low-voltage applications based on variable load technique instead of RF current commutating, as shown in Fig. 1(a). VB0 and VB are DC bias voltage. Transistor M2 operating in triode region acts as the variable load. Its conductance GL(t) is controlled by the LO signal vLO(t), that is GL ðtÞ ¼ bp ðV DD V B vLO ðtÞ9V THP 9Þ,

1 X

g L,n sinðnoLO tÞ:

ð2Þ

n¼1

When V LO r V DD V B 9V THP 9, g L,0 ¼ bp ðV DD V B 9V THP 9Þ, g L,1 ¼ bp V LO , and g L,n ¼ 0 for n 4 1. On the other hand, the harmonic components g L,n ðn ¼ 3,5,7, . . .Þ generate when V LO 4 V DD V B 9V THP 9. In this case, g L,0 and g L,1 are given by    1 y cos y þ sin y þ , ð3Þ g L,0 ¼ bp V LO 2 p p

g L,1 ¼ bp V LO



 1 y sin y cos y þ þ , 2 p p

ð4Þ

where

y ¼ sin1

þððjg L,1 =2Þvo,rf expðjðoRF oLO ÞtÞÞ,

ð8Þ

where gmN is the transconductance of the NMOS M1. From this equation, vo,rf and vo,if are given by g Z L ðoRF Þ v , vo,rf ¼  mN 1 þ g L,0 Z L ðoRF Þ rf

ð9Þ

ð1Þ

where bp is the transconductance parameter, VTHP is the threshold voltage of PMOS transistors. In this work, GL ðtÞ ¼ 0 in the case of V DD V B vLO ðtÞ9V THP 9 o 0 for simplification. When vLO ðtÞ ¼ V LO sin oLO t, GL(t) can be expanded in a series of sinusoids: GL ðtÞ ¼ g L,0 þ

Z L ðoRF oLO Þ½g L,0 vo,if expðjðoRF oLO ÞtÞ

V DD V B 9V THP 9 : V LO

ð5Þ

vo,if ¼ 

j g L,1 Z L ðoRF oLO Þ v : 2 1 þ g L,0 Z L ðoRF oLO Þ o,rf

ð10Þ

Thus, the voltage conversion gain (Gv) of the mixer is given by Gv ¼

vo,if g L,1 Z L ðoRF oLO Þ j g mN Z L ðoRF Þ  : ¼ 2 1 þg L,0 Z L ðoRF Þ 1þ g L,0 Z L ðoRF oLO Þ vrf

ð11Þ

When Z L ðoRF Þ b1=g L,0 , Z L ðoRF oLO Þ b 1=g L,0 , 9Gv 9 is g mN 9g L,1 9= 2g 2L,0 . Fig. 1(b) shows dependence of the voltage conversion gain on LO amplitude VLO in this case. In small LO amplitude region, the conversion gain increases proportionally to LO amplitude, which originates from g L,1 . With large LO amplitude, the conversion gain saturates and even decreases slightly due to increase in g L,0 . From these analytical results, to improve the voltage conversion gain, the bp (i.e. W/L) of the PMOS should be decreased, and V B and g mN should be increased. The mixer core proposed in Fig. 1(a) has some disadvantages. Firstly, it can be seen from Eqs. (9) and (10) that the RF feedthrough term exists in the output voltage, and it is larger than the mixing term. Secondly, the LO feedthrough will be found in the output if DC current of M1 is taken into account. To solve these disadvantages, the double balance structure is proposed as shown in Fig. 2. It is composed of four parts identical to Fig. 1(a), four resistors R are used

1.4 1.2

VDD

1 M2 0.8 VB +LO

O M1

VB0 +RF

0.6 0.4

ZL

0.2 0 0

0.5

1

1.5

2

Fig. 1. The proposed mixer based on variable load technique. (a) Basic operation principle of the proposed single balanced mixer and (b) its voltage conversion gain (Gv) versus LO amplitude.

B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

1005

VDD 2

i n,1/f

2

Ron

2

i n2 2 vn,out1

M1 2 in1

vin

2

i n,1/f

1

Fig. 2. Double balanced version of the proposed variable load mixer. Fig. 3. Noise equivalent circuit of the proposed single balanced mixer.

to sum the transconductance stages’ output voltage, so it can cancel the RF term in the output voltage of the single balanced version. The four resistors R and capacitor C also act as a low-pass-filter to filter the high-order harmonic of the mixing output. Based on Eqs. (9) and (10), the drain voltage at M1, M2, M5 and M6, namely v1, v2, v3 and v4 in Fig. 2 are   j ð 7 g L,1 Þ g mN v1ð,2,3,4Þ ¼ 1 ð 8 vRF Þ, ð12Þ 2 g L,0 g L,0 where Z L ðoRF Þ b 1=g L,0 , Z L ðoRF oLO Þ b1=g L,0 for simplification, because with R ¼ 3:4 kO and C ¼0.5 pF, the calculated 1=g L,0 is 97:4 O, 9Z L ðoRF Þ9 is in the range of 3:5323:57 kO for a frequency range of 2.4–2.5 GHz, and 9Z L ðoRF oLO Þ9 is 17:8 kO. The first and second terms of the right hand side in Eq. (12) means RF and IF components, respectively. Thus v2 þ v4 v1 þ v3  vo ¼ vIF þ vIF ¼ 2 2 j g mN g L,1 ðvRF þ vRF Þ: ¼ 2 g 2L,0

ð13Þ

It can be seen from Eq. (13) that the RF term in the output voltage is canceled. The proposed mixer in this paper is based on variable load technique. The load transistors (M3–M4 and M7–M8) operate in triode region during the LO signal period, resulting in their resistances ð1=GLðtÞ Þ controlled by the LO signal. Thus the output has a voltage term to achieve mixing. It can easily operate at sub 1.0 V low supply voltage because it has only two stacked transistors at each branch.

The flicker (1/f ) noise contribution from a MOSFET is K g2 , C ox WLf m

i2n,1=f ¼

where K is a process-dependent constant on the order of 1025 V2 F, f is the frequency. The noise equivalent circuit of the proposed single balanced mixer (Fig. 1(a)) is shown in Fig. 3, where Ron is the linear resistance of M2. As in [10], there is no switching in this mixer, so all noise contributions from M1 and M2 are directly propagated to the output without the need of consider frequency mixing. From Eqs. (14)–(16), the output noise term due to M1, M2 in Fig. 1(a) can be calculated as [11]  v2n,out1 ¼ 4kT gg mN þ

2

v2n,out ¼ 4ðv2n,out1 þ 4kTRÞ9Hðf Þ9 ,

v2n,in ¼

v2n,out 2

G2v 9Hðf Þ9

The proposed mixer is applied for low IF down conversion mixer, so the thermal noise and flicker (1/f) noise are the primary noise source. Let i2n ðf Þ represents the thermal noise current in the drain due to the channel resistance. If the transistor operates in the triode region [9], then ð14Þ

where Ron is the channel resistance, T is the temperature in Kelvin, and k is Boltzmann’s constant. For MOS transistor operates in the saturation region i2n ðf Þ ¼ 4kT gg m ,

ð18Þ

¼

4 G2v

 4kT gg mN þ

g 2mN K ðC ox WLÞN f

  g 2mP K 4kT 2 þ Ron þ 4kTR : Ron ðC ox WLÞP f

ð19Þ

Thus, the noise factor of the mixer core in Fig. 2 is F ¼ 1þ

4kT , Ron

ð17Þ

where H(f) is the transfer function of RC network. When referred to the RF input port, all the input-referred noise in Fig. 2 is given by

3.1. Noise figure

i2n ðf Þ ¼

 g 2mN K g 2mP K 4kT 2 þ þ Ron : ðC ox WLÞN f ðC ox WLÞP f Ron

All output noise in the double balanced mixer (shown in Fig. 2) can be calculated as

þ 3. Noise figure and linearity analysis

ð16Þ

ð15Þ

where the coefficient g is derived to be equal to 2/3 for long channel transistors and may be needed to be replaced by a larger value for submicron MOSFETs, gm is the transconductance of transistor.

4R2on G2v RS

gg mN þ

 ! g 2mN g 2mP 1 R K þ 2 þ þ , Ron Ron 4kTf ðC ox WLÞN ðC ox WLÞP ð20Þ

where RS is the source resistance. It can be seen from Eq. (20) that one must choose enough MOSFET dimension to guarantee the corner frequency of the flicker noise is below the IF frequency, otherwise, the dominant noise source of the mixer would be the flicker noise. Eq. (20) also indicate that the noise figure of the mixer is partly in proportion to the resistance of the RC network. The simulated single-sideband noise figure (NF SSB ) versus frequency of the double balanced mixer in different resistance ðRÞ are illustrated in Fig. 4, which shows the NFSSB of the mixer increased with the increment of the value of R. In condition of R ¼ 3:4 kO and W=L of NMOS is 100 mm=0:5 mm, W=L of PMOS is 160 mm=0:2 mm, the calculated noise figure from Eq. (20) and simulated NF SSB are 18.2 dB and 19.4 dB in 2 MHz IF frequency, respectively.

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B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

Here drain current of M2 is the sum of bias current IB and injected signal current is(t). The bias current depending on the vLO(t) and DC output voltage vout,DC is given by

SSB Noise Figure (dB)

30 R 2R 4R

27

IB ðtÞ ¼ IZ ½ðlnð1 þeðV DD V B 9V thp 9vLO ðtÞÞ=Zft ÞÞ2 ðlnð1 þ eðV DD V B 9V thp 9vLO ðtÞZðV DD vout,DC ÞÞ=Zft ÞÞ2 :

24

ð25Þ

From the above equation, a nonlinearity analysis for the variable load can be performed in the similar way to that in switching pair in the Gilbert mixer [15]. Since i(t) is small, a third-order Taylor expansion provides

21 18

vout ðtÞ  p0 ðtÞ þ p1 ðtÞis ðtÞ þ p2 ðtÞis ðtÞ2 þp3 ðtÞis ðtÞ3 , 15 0.1

1

10

100

Frequency (MHz) Fig. 4. Simulated single-sideband noise figure ðNF SSB Þ versus frequency in different R.

ð26Þ

where p0 ðtÞ, p1 ðtÞ, p2 ðtÞ, and p3 ðtÞ are periodic waveforms through vLO(t). They can be expressed as follows: V DD V B 9V thp 9vLO ðtÞ p0 ðtÞ ¼ V DD  þ2ft lnðef ðtÞ 1Þ ¼ vout,DC ,

Z

ð27Þ 3.2. Linearity Linearity is another important consideration in mixer design. The linearity of the mixer in Fig. 1(a) is determined by the linearity of the mixer’s transconductance stage and load transistors. The linearity of transconductance has been discussed in [12]. Generally, transconductance linearity can be improved by increasing the gate overdrive voltage. As the basic operating principle for CMOS transistor suggests, CMOS has high linearity with low gain in linear region and low linearity with high gain in saturation region [13]. In the mixer proposed in this paper, the load MOSFETs operate at linear region, they help to improve the linearity but provide less gain; the MOSFETs of gm stage operate at saturation region, help to improve the gain but offer lower linearity. The linearity of the mixer core which is illustrated in Fig. 1(a) will be discussed, the methodology and results can be readily extended to the double balanced version. The third-order intermodulation of the mixer (IIP 3,mixer ) can be related to those of transconductor M1 ðIIP3,gm Þ and variable load M2 ðIIP 3,vl Þ as follows: 1 IIP 23,mixer



g2 1 þ mN : 2 IIP3,gm IIP 23,vl

ID,M2 ¼ IZ ½ðlnð1þ e

p2 ðtÞ ¼

gðtÞ

ft

4I2Z ðexpðf ðtÞÞ1Þ2 f ðtÞ3

ð28Þ

,

f hðtÞ , p3 ðtÞ ¼  t 3 24IZ ðexpðf ðtÞÞ1Þ3 f ðtÞ5 where sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IB ðtÞ f ðtÞ ¼ ðlnð1 þeðV DD V B 9V thp 9vLO ðtÞÞ=Zft ÞÞ2  , IZ

ð29Þ

ð30Þ

ð31Þ

gðtÞ ¼ ð1f ðtÞef ðtÞ Þef ðtÞ ,

ð32Þ

hðtÞ ¼ 3e3f ðtÞ þ ðf ðtÞ2 þ3f ðtÞ6Þe2f ðtÞ þ ðf ðtÞ2 3f ðtÞ þ 3Þef ðtÞ :

ð33Þ

ð21Þ

This relation allows us to separate the mixer to two parts in nonlinear distortion analysis. Consider the variable load M2. The operating point of the transistors varies periodically with time. Such large-signal behavior of M2 is described by the semi-empirical ‘‘single-piece’’ MOS transistor model presented in [14–17], which uses the same kind of smooth interpolation between the operation regions. The drain current of M2 can be given by ðV DD V B 9V thp 9vLO ðtÞÞ=Zft

expðf ðtÞÞ , IZ ðexpðf ðtÞÞ1Þf ðtÞ

ft

p1 ðtÞ ¼ 

vout ðtÞ  vout,DC þ

2

ÞÞ

ðV DD V B 9V thp 9vLO ðtÞZðV DD vout ðtÞÞÞ=Zft

ðlnð1þ e

When vLO(t) is periodic function of time, p1 ðtÞ, p2 ðtÞ, and p3 ðtÞ are also periodic. Without loss of generality, p1 ðtÞ, p2 ðtÞ, and p3 ðtÞ can be considered odd functions of time and can be expanded in a Fourier series. As the mixer is used only for down conversion by fundamental LO tone in this case, Eq. (26) provides the distortion behavior of the variable load in the frequency band of interest as follows:

ÞÞ2 ,

 vout,DC þ½b1 is ðtÞ þ b2 is ðtÞ2 þ b3 is ðtÞ3  sinðoLO tÞ,

ð22Þ

2 IZ ¼ 2bp ft .

1 1X ½p is ðtÞ þ p2,k is ðtÞ2 þ p3,k is ðtÞ3  sinðkoLO tÞ 2 k ¼ 1 1,k

ð34Þ

where Z In the equations above, ft is the thermal voltage. The parameter Z is related to the subthreshold factor and describes the rate of the exponential increase of drain current with gate-source voltage in the subthreshold region. Here channel length modulation, mobility degradation, and velocity saturation in stronginversion saturation region are neglected for simplification. From Eq. (22), vout(t) can be obtained as follows:

Next consider nonlinearity of the transconductor M1 using the model containing carrier velocity saturation given by

1 vout ðtÞ ¼ V DD  ðV DD V B 9V thp 9vLO ðtÞÞþ 2ft lnðexpðFðtÞÞ1Þ,

Id ¼

Z

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IB ðtÞ þ is ðtÞ : FðtÞ ¼ ðlnð1 þ eðV DD V B 9V thp 9Þ=Zft ÞÞ2  IZ

ð23Þ

ð24Þ

where oLO =2p is the LO frequency, pi,k is the k-th coefficient of the waveform pi(t) in the series, and Z p oLO 2p=oLO bi ¼ i,k ¼ pk ðtÞ sinðkoLO tÞ dt: ð35Þ 2 2p 0

1 V 2od b , 2 n 1 þ YV od

ð36Þ

where bn is transconductance parameter of M1, V od ¼ V B0 V THN is gate overdrive voltage and VTHN is threshold voltage of NMOS transistor M1. Y ¼ m0 =ð2vsat LÞ þ y is obtained from saturation velocity (vsat), carrier mobility at low electric field (m0 ) and mobility

B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

degradation factor (y). From the first and third derivatives of Id (gmN and g ð2Þ mN ), the IIP3 can be obtained as follows:

4. Measurement results The double balanced version of the proposed mixer shown in Fig. 2 had been fabricated in 0:18-mm 1P6M CMOS process. Its micrograph is shown in Fig. 7. The occupation area is 0:53 0:405 mm2 , including the pads and ESDs. The active chip area is 0:15  0:14 mm2 . To avoid mismatches, all the transistors and

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u u8g  mN IIP 3,gm ¼ t ð2Þ  g  mN

¼

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4 V od ð2 þ YV od Þð1þ YV od Þ2 : 3 Y

ð37Þ

0.405 mm

It can be seen from Eq. (37) that in order to improve the inputreferred third-order intercept point ðIIP3Þ of the gm stage, VB0 should be increased. Eq. (37) gives IIP 3,gm  0:75 V for NMOS device with L ¼ 0:5 mm and VB0 ¼0.65 V in our design. Based on Eqs. (21), (35) and (37), the calculated IIP3 of the mixer is IIP 3,mixer  6.1 dBm. From Eqs. (28)– (35), it can be seen that the input-referred third-order intercept point ðIIP3Þ of the mixer is partly depended on the DC bias voltage VB of the variable load stage. To investigate how VB affect the IIP3 performance, the mixer’s IIP3 under difference VB and same VB0 ¼ 0.65 V was simulated. The simulated IIP3 in different VB are illustrated in Fig. 5, which shows that the IIP3 in power (PIIP3) is 1.6 dBm in the case of VB ¼350 mV, in the case of VB ¼300 mV and VB ¼250 mV, the PIIP3 is 1.4 dBm and 3.9 dBm, respectively. It can bee seen from Fig. 5 that reducing VB can improve the IIP3 performance, but from Eq. (11), it will depress the conversion gain. The simulated conversion gain (CG) versus LO power of the double balanced mixer in different VB are illustrated in Fig. 6, which shows that with the reducing VB, the conversion gain ðCGÞ is dropped.

0.530 mm Fig. 7. Micrograph of the fabricated mixer.

abc

20 IF Output Power (dBm)

1007

0 -20 -40 -60 -80 a: VB = 0.35V, PIIP3 = -1.6dBm b: VB = 0.30V, PIIP3 = 1.4dBm c: VB = 0.25V, PIIP3 = 3.9dBm

-100 -120 -140 -45

-35

-25 -15 -5 RF Input Power (dBm)

5 Fig. 8. Output spectrum of two-tone test.

Fig. 5. Simulated input-referred third-order intercept points ðPIIP3 Þ of the double balanced variable load mixer in different VB.

20

8 IF Output Power (dBm)

Fundamental

Conversion Gain (dB)

7 6 5 4 VB = 0.25V VB = 0.35V VB = 0.30V

3 2

0

3rd order

-20 -40 -60 P1dB

1 -80 -50

0 -5

-4

-3

-2

-1 0 1 2 LO Input Power (dBm)

3

4

5

Fig. 6. Simulated conversion gain ðCGÞ of the double balanced mixer in different VB.

-40

-30 -20 -10 RF Input Power (dBm)

PIIP3 0

10

Fig. 9. Two-tone harmonic measurement results with an input frequency spacing of 200 kHz.

1008

B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

metal connections in the circuit was placed as symmetrically as possible [18]. Transistors with non-minimum channel lengths were used to optimize the linearity, 1/f noise, and device matching. The gate length and width of NMOS transistors in gm stage are 0:5 mm and 100 mm, respectively. The W/L of PMOS transistors are 160 mm=0:2mm. In the RC network, R and C are 3:4 kO and 0.5 pF,

35 SSB Noise Figure (dB)

33 31

Measurement

29

Calculation

27

Simulation

25 23 21 19 17 0.1

1

10 Frequency (MHz)

100

Fig. 10. Measured single sideband noise figure (NFSSB) versus frequency, and compared with simulation and calculation results.

Conversion Gain (dB)

8 4 0 -4 -8 -20

-15

-5 0 -10 LO Input Power (dBm)

5

Fig. 11. Measured conversion gain (CG) versus LO input power.

Table 1 Comparison of calculated, simulated and measured results of linearity and noise figure. Parameter

Calculated

Simulated

Measured

NFSSB (dB) PIIP3 (dBm)

18.2 6.1

19.4 3.9

21.7 4.6

respectively. All high frequency signals (i.e. RF and LO signal) were routed on upper or the top metal layer to reduce parasitic capacitances. The fabricated mixer was measured in 2.4-GHz ISM band with a supply voltage of 1.0 V using on-wafer RF probes. The DC bias voltages of VB0 and VB are 0.65 V and 0.25 V, respectively. It draws 875 mA DC current at each branch from the supply. The LO port was driven by a 2.442 GHz LO signal, and the RF signal frequency was 2.440 GHz. The RF signal powers have been corrected to compensate for the insertion loss of the connection to the chip’s pads. From the signal source to the RF pads, the connection is composed of cable, tuner, balun, bias Tee, cable and probe. The correction procedures for the insertion loss of the connection are as follows: Firstly, the open s-parameters from RF input term of the bias Tee to the probe were measured, and then the insertion loss of this part was obtained. Secondly, s-parameters from cable term which connect to signal source to the output term of the balun, and s-parameters from RF input term of the bias Tee to the output of all the measurement setup were measured, respectively. Then the s-parameters were converted to z-parameters, the connection from signal source to output term of the balun was equivalent to a voltage source with an impedance of ZS, and the connection after the RF input term of bias Tee was equivalent to a load ðZ 0 Þ. For a given power from the signal source, we can get the power on the load ðZ 0 Þ, the difference of the two power is the insertion loss from signal source to output term of the balun. The summation of the two steps gives the total insertion loss, which is 5.56 dB. The measurement results are shown in Figs. 8–11. Fig. 8 shows the output spectrum of the two-tone test with the input RF frequencies of 2.4401 GHz and 2.4399 GHz, and the input RF power level of both are  22 dBm. Fig. 9 illustrates the measured intermodulation distortion versus the RF input power, indicating the input-referred third-order intercept points in power (PIIP3) is 4.6 dBm and the input-referred 1 dB compression point (P1 dB ) is  7.4 dBm. To compare with simulation results in Fig. 5, PIIP3 under difference VB and same V B0 ¼ 0:65 V was also measured, the measurement results are 0.3 dBm and 2.3 dBm under conditions of VB ¼0.35 V and VB ¼0.3 V, respectively. The measured single-sideband noise figure (NFSSB) versus frequency is illustrated in Fig. 10, and compared with simulation and calculation results. The measurement result shows a NFSSB of 21.7 dB at the IF frequency. As the resistances in the RC filter contribute considerable noise to the output, the mixer’s noise figure is degraded. However, this SSB noise figure can be acceptable since the noise term contributed from the mixer will be compressed by the LNA’s gain as for the total noise figure of the front-end receiver. Fig. 11 illustrates the measured conversion gain ðCGÞ versus LO input power. The calculated, simulated and measured results of linearity (PIIP3) and single sideband noise figure are compared in Table 1.

Table 2 Summary of results and performance comparison. Ref.

This work

[2]

[3]

[4]

[5]a

[6]

[7]

Supply voltage (V) CG (dB) P 1 dB (dBm) PIIP3 (dBm) NFSSB (dB) RF–IF isolation (dB) LO–IF isolation (dB) Total DC current (mA) Occupation area (mm2)

1.0 5.3  7.4 4.6 21.7 61.5 63.3 3.5 0.53  0.405

1.0 11.9 –  3.0 13.9 – – 3.2 0.16  0.2b

1.0 4.3–7.2 o 16:0 2.0–3.0 16.9–17.4 34.2 43.0 2.9 1.145  1.08

1.0 5.8  16.0  6.0 16.0 39 57 3.8 1.042  1.102

1.0 10.1  25.4  17.0 – – – 12.5 1.38  1.38

0.9 8.3  15.0 0.03 24.5 – 19.0 5.5 –

1.0  10:8 – 4.0 24.8 – – 4.0 0.075  0.065c

a b c

Simulation results. Active occupation area only. Mixer core area only.

B.-L. Wei, Y.-J. Dai / Microelectronics Journal 43 (2012) 1003–1009

The measured performance of the proposed mixer is summarized in Table 2, and compared with several published low-voltage mixers. It can be seen that the linearity performance of the proposed mixer is more competitive. High linearity performance is very important in the front-end receiver because the linearity of mixer has great impact to the dynamic range of the receiver. This is a serious issue in low-voltage mixer design. Though the conversion gain (CG) of the mixers in [4–6] is larger than that of this work, there are 3–5 inductors in these mixers which would increase their occupation area. This point also becomes important for low-cost chip fabrication even in more advanced CMOS process.

5. Conclusion A low-voltage CMOS active mixer was proposed and implemented in 0:18-mm 1P6M CMOS process. PMOSFETs operating in triode region are adopted to act as the variable load controlled by the local signal, make the mixer’s output having a voltage term to perform mixing. Measurement results show that its linearity performance, the single sideband noise figure, and conversion gain performance are acceptable even under 1.0 V supply voltage.

Acknowledgments This work is supported by the National Natural Science Foundation of China (Nos. 61166004 and 61161003), the International Scientific and Technological Cooperation Project of Tianjin Projects of Science and Technology Plan (No. 09ZCGHHZ00200), and the Doctoral Scientific Research Foundation for Guilin University of Electronic Technology (No. UF10028Y). The authors would like to thank associate professor Matsuoka T. and Dr. Wang J. from Osaka University for helping measurement and giving useful suggestions on the paper.

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