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High linearity, low power RF mixer design in 65 nm CMOS technology
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High linearity, low power RF mixer design in 65 nm CMOS technology Raja Mahmou ∗ , Khalid Faitah Laboratory of Electrical Engineering and Control Systems (LGECOS), ENSA Marrakech, Cadi Ayyad University, Morocco
a r t i c l e
i n f o
Article history: Received 5 April 2013 Received in revised form 3 April 2014 Accepted 5 April 2014 Keywords: Low power High linearity 65 nm technology Noise Figure Conversion gain
a b s t r a c t A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB. © 2014 Elsevier GmbH. All rights reserved.
1. Introduction Since several years, research for possibilities of CMOS technologies for RF applications is growing enormously. The trend toward deep sub-micron technologies allows the operation frequency of CMOS circuits above 1 GHz, which opens the way to miniaturize integrated RF circuits while reducing energy consumption. The Mixer block has a critical impact on the performances of all system functions in any RF channel. It is a non-linear device used to translate one frequency to another. On receiver chain (Fig. 1), on which we worked, the principle of any type of RF mixer is that the Local Oscillator (LO) drives by (switching/modulating) the incoming Radio Frequency (RF) to an Intermediate low Frequency (IF) [1]. This work reports a design of Gilbert cell mixer with 65 CMOS technology, starting by the architecture of proposed circuit, then a theoretical study to improve linearity, and simulation result of evaluating parameters on ADS tool, also a potential comparison with recents proposed circuits. 2. Architecture of proposed mixer 2.1. Mixer operation Gilbert Cell is a double balanced mixer, much complex, but have more performances compared to single balanced mixer: all ports of the mixer are inherently isolated from each other, increased
∗ Corresponding author. Tel.: +212 678568165. E-mail addresses: [email protected] (R. Mahmou), [email protected] (K. Faitah).
linearity, and improved suppression of spurious products than less susceptible to supply voltage noise due to differential topography [2]. As shown in Fig. 2, RF signal is applied to the transistors (M2 and M3) which perform a voltage to current conversion. MOSFETs M4–M7 form a multiplication function of the linear RF signal current from (M2 and M3) with LO signal applied across M4–M7. (M2 and M3) provide ±RF current and (M4 and M6) switch between them to provide the inverted RF signal to the left hand load. (M5 and M7) switch between them for the right hand load. The two load resistors form a current to voltage transformation giving a differential output IF signals [2].
2.2. Choice of CMOS 65 nm technology The 65 nm length of MOSFET channels was chosen to maximize gain, to minimize noise and to optimize the footprint of the circuit. The width was chosen maximum with respect to current consumption specifications [3]. Length and width of input RF CMOS block dedicated to analog/RF applications is determined, using a technique based on the minimum noise to obtain optimal size of the width, that is expressed by the following equation [4]: W = Wopt =
1 3ωLRs Cox
(1)
where W and L are respectively the width and the length of MOS channel. Cox is the surface capacitor of the gate-channel and Rs is the resistor of matching (generally equal to 50 ). Then, an adjustment is made after the simulation to achieve the desired performances.
http://dx.doi.org/10.1016/j.aeue.2014.04.006 1434-8411/© 2014 Elsevier GmbH. All rights reserved.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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Fig. 1. Typical transceiver block diagram [1].
2.3. Improving linearity circuit Gilbert Cell Mixer Linearity depends on the three main sources: RF stage, switching and load circuits. On general, linearity is represented by intermodulation (IM3) performances: this parameter is measured by applying the third order products from the mixing of RF and LO tones with the LO tones at the frequencies given by: (2RF ± LO) ± LO and (2LO ± RF) ± LO. Generally the most interesting third other product are: (2RF-LO)-LO and (2LO-RF)-LO as they fall in, or close to the IF band [2]. 2.3.1. Third harmonic relative to the fundamental Input attacks a differential pair, as shown in Fig. 3: VRF and Vout being a differential tensions: VRF = VRF1 − VRF2 and Vout = Vout1 − Vout2 ID3 , ID2 are respectively the drain currents of transistors M3 and M2 , with: Vout = RD (ID2 − ID3 )
(2)
The potential at N point is equal both to VRF1 − VGS1 and VRF2 − VGS2 thus: VRF1 − VRF2 = VGS1 − VGS2
Fig. 3. Double balanced mixer circuit.
Given that [4]:
VGS =
2ID + VTH n Cox (w/L)
Then:
VRF1 − VRF2 =
(4)
2ID2 − n Cox (w/L)
2ID3 n Cox (w/L)
(5)
Our objective is to determine the amplitude ratio of third harmonic of the output signal (Vout ) relative to the fundamental. Based on Eq. (2) we just need to calculate (ID3 − ID2 ). By squaring expression (5), we obtain: (VRF1 − VRF2 )2 =
2 (Iss − 2 ID3 ID2 ) with Iss = ID3 + ID2 n Cox (w/L) (6)
(3) Given that: 2 4ID3 ID2 = (ID3 + ID2 )2 − (ID3 − ID2 )2 = Iss − (ID3 − ID2 )2
By squaring expression (6) and after a serie of simplifications, we obtain ID2 − ID3 =
Fig. 2. Gilbert cell architecture.
1 n Cox (w/L)VRF 2
4Iss 2 − VRF n Cox (w/L)
(7)
Fig. 4. Resistance degeneration circuit.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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m1
0
m1 freq=100.0MHz dB(Vout)=-14.358
-50 -100
dB(Vout)
3
-150 -200 -250 -300 -350 0.0
0.5
1.0
1.5
2.0
2.5
3.0
freq, GHz Fig. 7. Frequency output spectrum.
Fig. 5. Proposed RL degeneration. 2 2 /4(V We pose ˛ = VRF GS − VTH ) , with ˛ 1, enabling us 1/2 to write: (1 − ˛) ∼ 1 − (1/2)˛, then for a small input signal VRF (1.2) = Vm cos(ωt), Eq. (8) becomes:
0
dB(VRF)
m2 freq=1.900GHz dB(VRF)=-23.098
ID2 − ID3 ≈ n Cox (w/L)(VGS − VTH ) Vm cos(ωt) −
m2
3 cos3 ωt Vm
8(VGS − VTH )2
(9)
Given that transconductance of CMOS on saturation is: gm = -50 0.0
0.5
1.0
1.5
2.0
2.5
∂ID w = n Cox (VGS − VTH ) L ∂VGS
From some calculations we find:
3.0
freq, GHz
ID2 − ID3 ≈ gm Vm −
Fig. 6. Frequency input spectrum at 1.9 GHz.
− gm
Iss being equal to the double of drain current of transistors, Eqs. (7) and (3) lead to: ID2 − ID3 =
1 n Cox (w/L)VRF 2
= n Cox (w/L)VRF (VGS − VTH )
1−
3 3Vm
32(VGS − VTH )2
cos ωt
3 cos 3ωt Vm
(11)
32(VGS − VTH )2
Resulting Vm from RF signal is too small, it can be assumed 2 3 /32(V that: Vm (3Vm GS − VTH ) ), which gives the amplitude ratio expression of the output (Vout ) third harmonic relative to the fundamental:
2 4(VGS − VTH )2 − VRF
(10)
2 VRF
(8)
4(VGS − VTH )2
3 Ah3 3Vm = Af 32(VGS − VTH )2
(12)
600
T=10ns
ts(Vout),Vm
400 200 0 -200 -400 -600 0
2
4
6
8
10
12
14
16
18
20
time, nsec Fig. 8. Output signal.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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2.3.2. Degeneration circuit From this analysis, one hand; mixer linearity increases by reducing the ratio (11), other hand by making linear the expression of equivalent circuit transconductance (12):
m1
20
m1 Power_RF=11.600 Line2=18.313 IM3 Line2 Vout_dBm1
0
Gm =
(13)
Generally, degeneration topology (Fig. 4) [6] is one of the most often used for mixers: Given that ID = f(VGS ), Eq. (13) becomes: Gm = (∂f/∂VGS )(∂VGS /∂VRF ) and VGS = VRF − Rs ID „ then:
-20
-40 -40
-30
-20
-10
0
10
20
Gm =
Power_RF
1 − Rs
∂ID ∂VRF
∂f ∂VGS
(14)
Being ∂f/∂VGS the transconductance gm of M1, Eq. (14) leads to:
Fig. 9. Third order interception point (IIP3).
Gm =
m1
4.0
∂ID ∂VRF
gm 1 + gm Rs
(15)
Voltage gain will then be:
m1 freq=100.0MHz Vout.noise=3.970nV
Vout.noise, nV
3.9
Gv =
3.8
3.7
3.6
3.5 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
freq, GHz Fig. 10. Output noise.
m2 freq=1.900GHz VRF.noise=901.2pV
907
VRF.noise, pV
906
(16)
And for Rs 1/gm : Gm ≈ 1/Rs which gives ∂ID ≈ ∂VRF /Rs ; it is therefore a linear variation of drain current relative to the input signal. The issue is, if we increase Rs , it reduces the Gain of circuit, then it conflict to evaluating parameters circuit. R-L degeneration circuit is able to fill this constraint (Fig. 5): Since the amplitude of RF signal (Vm ) arises from LNA circuit, value choices (R and L) of proposed degeneration circuit will increases the IIP3 value without affecting gain. Based on (Fig. 5): VGS = − UR (UR is the voltage across R) Then, when increasing R, VGS increases, therefore and according to Eq. (12), IIP3 value increases. Concerning the gain of circuit: Gm =
908
−gm Rd 1 + gm Rs
∂f ∂VGS = ∂VGS ∂VRF
1 − Lω ·
∂ID ∂VRF
gm = (1 − Lω · Gm )gm
(17)
Then equivalent transconductance of circuit is: Gm =
905
gm 1 + gm Lω
(18)
L is very low; it has no impact on Gm , consequently on the circuit voltage gain Gv = −Gm Rd .
904 903 902
3. Simulation results
m2
901 900 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
freq, GHz
IDS.i, mA
Fig. 11. Input noise.
m1 Vdd=1.800 IDS.i=1.208mA m1
1.208274
On Agilent ADS tool, lengths (65 nm) of MOSFETs channel were chosen to maximize gain, to minimize noise and to optimize the footprint of the circuit. The width of RF input MOSFET was chosen maximum with respect to current consumption specifications [3]. The bias current of M1 (Fig. 2) is fixed by keeping the bias voltage of CMOS at Vdd = 1.8 V.
Values at bias point indicated by marker m1. Move marker to update. Device Power Consumption, Watts
VDS
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1.80000
0.00217
Vdd Fig. 12. Power consumed by circuit.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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Table 1 Summary result and performance comparison.
GC (dB) IIP3 (dBm) Power (mW) NF (dB) Tech RF (GHz)
This worka
[7] a
[6] a
[8] a
[9]
[10] b
[11] b
8.75 11.6 2.02 4.12 65 nm 1.9
13.97 1.7 2.02 3.13 65 nm 1.9
9.12 10.45 30.78 9.74 0.18 m 1.9
12.42 6 2.02 8.92 65 nm 1.9
10 5 – 12 – –
5.3 +17 4.6 >−6 3.5 4.5 21.7 7.1 0.18 m 0.13 m 2.4 0.05–6.5
[12] a
[13] c
[14] a
[15] c
[16] a
[17] c
13 22.3 6 −3.3 8.6 34 −3.08 −10.8 −4.34 −10.3 6.7 4 0.48 0.905 10.8 7.56 0.423 3 12.7 7.2 7.35 16.5 19.2 10 0.13 m 0.13 m 0.18 m 0.13 m 0.11 m 0.13 m 2.5 2.4 1.56 2.4 2.4 0.402–0.405
[18] a 17.5 −7.2 – 13.5 0.13 m 2.1
a
Simulation result. Measurment result. c Simulation result of LNA-Mixer architecture. [9] Typical characteristics values (B. Razavi). [18] Values are raised from simulation curves. [10] Simulation values of IIP3 and NF are respectively equal to: 3.9 dBm and 19.4 dB. b
VRF and VLO frequencies are respectively 1.9 and 1.8 GHz which provides an intermediate frequency of 100 MHz. Choice of these values gives an IF frequency as agreed to meet most of the wireless networks deployed today, and operating frequency around 1 GHz, such as GSM. The principal parameters adopted to characterize RF mixer are: Conversion Gain, Noise Figure and Linearity [5].
references made here as a comparison, an excellent power consumption is found, which justifies the right technique adopted with the degeneration used and the good commutation of transistors M2 and M3 without a power loss.
3.1.1. Transient and harmonics responses
The purpose is to reveal the feasibility of a Gilbert Cell Mixer in RF chain, dedicated to low power consumption wireless applications; with 65 nm CMOS technology, in order to minimize size as well the power consumption. Theoritical study to increase linearity without degrading conversion gain was achieved. The most important parameters characterizing an RF mixer were simulated, and results shows the performance of this choice compared to recent technologies, also the optimized number of components has enabled us to minimize the power consumed by this circuit.
The following graphs (Figs. 6–8) show that the proposed circuit realizes the function of mixing frequencies: Output signals show a frequency value equal to 100 MHz. Other unwanted harmonics are due to non-linearity circuit, according to Figs. 6 and 7 conversion gain is equal to 8.75 dB. 3.1.2. Order 3 interception point (IIP3) The following graph (Fig. 9) shows an IIP3 value equal to 11.6 dBm. 3.1.3. Noise Figure Curve noise in the input and in the output, are shown in Figs. 10 and 11. By Figs. 10 and 11 and the relation between Output, Input Noise and the Conversion Gain (NF = Nout /Nin ·CG), the Noise Figure is equal to 4.12 dB. 3.1.4. Power consumption DC simulation, allowed us to measure the power consumption of the mixer circuit which is 2.17 mW, with Vdd = 1.8 V. 4. Performances comparison Simulated performances of proposed design; miniaturized Gilbert-Cell with 65 nm-CMOS technology for 1.9 GHz GSM frequency, using R-L linearity degeneration circuit; are summarized in Table 1, and compared (for the same RF band) with the most recent approaches, including: typical characteristics of RF Mixer [9], and our latest works [6],[7] and [8]. Values of: Conversion Gain, IIP3, NF and Power Consumption are raised from curves (Figs. 6–12) and compared to recent simulation results, including simulation results of LNA-Mixer architecture as [13,15,17]. From Table 1, we note that present circuit achieves a very good trade between linearity and gain (IIP3 = 11.6 dBm and GC = 8.75 dB), Lower Noise, such as NF = 4.12 dB is the lower of values after NF of [7], and a miniaturized CMOS technology (65 nm) whilst keeping power consumption the lowest (after [12,13,16]). Although a polarization used is equal to 1.8 V, relatively large compared to
5. Conclusion
References [1] Rogers J, Plett C. Radio frequency integrated circuit design. Artech House Microwave Library; 2003, 5 p. [2] Silver JP. Gilbert cell mixer design tutorial. RF, RFIC, et Microwave Theory and Design; 2010 www.rfic.co.uk [3] Martineau B. Millimeter-Wave building blocks design methodology in CMOS 65 nm process using Agilent tools. In: ADS users’s group meeting. 2009. STMicroelectronics-Crolles/Minatec. [4] LEE. TH. The design of CMOS radio frequency integrated circuits. Cambridge: University Press; 1998. [5] Villegas M, et al. Digital radiocommunications 2/conception of RF integrated circuits and microwaves, Dunod; 1999. p. 219–22. [6] Faitah K, Mahmou R. Design of 1.9 GHz Gilbert-Cell Down conversion mixer with good linearity in 0.18 m CMOS technology. AMSE J Model Meas Contr Gen Phys Electr Appl 2012;85(1–2). [7] Mahmou R, Faitah K. A low power consumption Gilbert-Cell Mixer in 65 nm CMOS technology. In: International symposium of telecom and 8th JFMMA. 2013. [8] Mahmou R, Faitah: K. Conception of RF Mixer with a 65 nm CMOS technology dedicated to low power consumption wireless applications. In: Proceeding IEEE ICMCS’12. 2012. [9] Razavi B. RF microelectronics. Prentice Hall, Ptr; 1998. [10] Wei B-L, Dai Y-J. Analysis and design of 1.0-V CMOS mixer based on variable load technique. Microelectr J 2012;43:1003–9. [11] Augusto R, Ximenes, Swart JW. A CMOS wideband mixer for direct-conversion receivers (DCRs). In: 8th IEEE ICCDCS. 2012. [12] Shirazi AHM, Mirabbasi S. An ultra-low-voltage CMOS mixer using switched transconductance, current-reuse and dynamic-threshold-voltage gain-boosting techniques. 978-1-4673-0859-5/12/$31.00 ©2012 IEEE, no. 393–6. [13] Chong W-K, Ramiah H, Tan G-H, Vitee N, Kanesan J. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application. Int J Electron Commun (AEÜ) 2013, http://dx.doi.org/10.1016/j.aeue.2013.07.009. [14] Lai D, Chen Y, Wang X, Chen X. A CMOS single-differential LNA and current bleeding CMOS mixer for GPS receivers. In: Proceedings of ICCT 2010. 2010. p. 677–80. [15] Martins MA, Oliveira LB, Fernandes JR. Combined LNA and mixer circuits for 2.4 GHz ISM band. In: Proceedings of IEEE international symposium on circuits and systems. 2009. p. 425–8. [16] Chang C-H, Onabajo M. IIP3 enhancement of subthreshold active mixers. In: Circuits and systems II: IEEE transactions, vol. 60(11). 2013, November. p. 731–5.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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[17] Mohamed SAS, Manoli Y. Design of low-power direct-conversion RF front-end with a double balanced current-driven subharmonic mixer in 0.13 CMOS. In: Circuits and Systems I, IEEE Transactions, vol. 60(5). 2013, May. p. 1322–30. [18] Kim M-G, Yun T-Y. Analysis and design of feed forward linearity-improved mixer using inductive source degeneration. IEEE Trans Microw Theory Tech 2014;February:323–31. Raja Mahmou Received Professional License degree of Electrical Engineering (2007), Master of Electrical Engineering (2009), from Faculty of Sciences and Technics of Marrakech, at Cadi Ayyad University (UCAM) of Morocco. Now, PhD candidate in Conception of Analog Systems and RFIC at Laboratory Of Electrical Engineering and Control Systems (LGECOS), UCAM of Morocco, Actually, a Substitute Professor of Analog Electronic, RF CMOS Designs at ENSA Marrakech, author, co-author of publications and communications in some international journals and conferences.
Dr. Khalid Faitah was born in Rabat, Morocco, in June 1965. Received B.S. degree in electronics from Mohamed V University of science, Rabat, Morocco in 1988 and the M.S degree in signal processing in 1997 from Hassan II University of science, Casablanca, Morocco. Received Ph.D. degree in electronic at Ibn Tofal University of science, Kenitra, Morocco on 2003. In 2009 he graduated from HDR (Certificate of Accreditation to the search direction). He is now Professor at ENSA (National Institute of Applied Sciences), Department of Electrical Engineering in Cadi Ayyad University, Marrakech, Morocco where he teaches analog electronics, RF CMOS design, sensors and interface circuits and also is Responsible of the Electrical Engineering and Control Systems Laboratory, His research interests include signal integrity and analog RF CMOS design. He is the author, co-author and reviewer of several publications and communications in recognized journals and international conferences.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
ARTICLE IN PRESS
AEUE-51192; No. of Pages 6
Int. J. Electron. Commun. (AEÜ) xxx (2014) xxx–xxx
Contents lists available at ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue
High linearity, low power RF mixer design in 65 nm CMOS technology Raja Mahmou ∗ , Khalid Faitah Laboratory of Electrical Engineering and Control Systems (LGECOS), ENSA Marrakech, Cadi Ayyad University, Morocco
a r t i c l e
i n f o
Article history: Received 5 April 2013 Received in revised form 3 April 2014 Accepted 5 April 2014 Keywords: Low power High linearity 65 nm technology Noise Figure Conversion gain
a b s t r a c t A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB. © 2014 Elsevier GmbH. All rights reserved.
1. Introduction Since several years, research for possibilities of CMOS technologies for RF applications is growing enormously. The trend toward deep sub-micron technologies allows the operation frequency of CMOS circuits above 1 GHz, which opens the way to miniaturize integrated RF circuits while reducing energy consumption. The Mixer block has a critical impact on the performances of all system functions in any RF channel. It is a non-linear device used to translate one frequency to another. On receiver chain (Fig. 1), on which we worked, the principle of any type of RF mixer is that the Local Oscillator (LO) drives by (switching/modulating) the incoming Radio Frequency (RF) to an Intermediate low Frequency (IF) [1]. This work reports a design of Gilbert cell mixer with 65 CMOS technology, starting by the architecture of proposed circuit, then a theoretical study to improve linearity, and simulation result of evaluating parameters on ADS tool, also a potential comparison with recents proposed circuits. 2. Architecture of proposed mixer 2.1. Mixer operation Gilbert Cell is a double balanced mixer, much complex, but have more performances compared to single balanced mixer: all ports of the mixer are inherently isolated from each other, increased
∗ Corresponding author. Tel.: +212 678568165. E-mail addresses: [email protected] (R. Mahmou), [email protected] (K. Faitah).
linearity, and improved suppression of spurious products than less susceptible to supply voltage noise due to differential topography [2]. As shown in Fig. 2, RF signal is applied to the transistors (M2 and M3) which perform a voltage to current conversion. MOSFETs M4–M7 form a multiplication function of the linear RF signal current from (M2 and M3) with LO signal applied across M4–M7. (M2 and M3) provide ±RF current and (M4 and M6) switch between them to provide the inverted RF signal to the left hand load. (M5 and M7) switch between them for the right hand load. The two load resistors form a current to voltage transformation giving a differential output IF signals [2].
2.2. Choice of CMOS 65 nm technology The 65 nm length of MOSFET channels was chosen to maximize gain, to minimize noise and to optimize the footprint of the circuit. The width was chosen maximum with respect to current consumption specifications [3]. Length and width of input RF CMOS block dedicated to analog/RF applications is determined, using a technique based on the minimum noise to obtain optimal size of the width, that is expressed by the following equation [4]: W = Wopt =
1 3ωLRs Cox
(1)
where W and L are respectively the width and the length of MOS channel. Cox is the surface capacitor of the gate-channel and Rs is the resistor of matching (generally equal to 50 ). Then, an adjustment is made after the simulation to achieve the desired performances.
http://dx.doi.org/10.1016/j.aeue.2014.04.006 1434-8411/© 2014 Elsevier GmbH. All rights reserved.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006
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Fig. 1. Typical transceiver block diagram [1].
2.3. Improving linearity circuit Gilbert Cell Mixer Linearity depends on the three main sources: RF stage, switching and load circuits. On general, linearity is represented by intermodulation (IM3) performances: this parameter is measured by applying the third order products from the mixing of RF and LO tones with the LO tones at the frequencies given by: (2RF ± LO) ± LO and (2LO ± RF) ± LO. Generally the most interesting third other product are: (2RF-LO)-LO and (2LO-RF)-LO as they fall in, or close to the IF band [2]. 2.3.1. Third harmonic relative to the fundamental Input attacks a differential pair, as shown in Fig. 3: VRF and Vout being a differential tensions: VRF = VRF1 − VRF2 and Vout = Vout1 − Vout2 ID3 , ID2 are respectively the drain currents of transistors M3 and M2 , with: Vout = RD (ID2 − ID3 )
(2)
The potential at N point is equal both to VRF1 − VGS1 and VRF2 − VGS2 thus: VRF1 − VRF2 = VGS1 − VGS2
Fig. 3. Double balanced mixer circuit.
Given that [4]:
VGS =
2ID + VTH n Cox (w/L)
Then:
VRF1 − VRF2 =
(4)
2ID2 − n Cox (w/L)
2ID3 n Cox (w/L)
(5)
Our objective is to determine the amplitude ratio of third harmonic of the output signal (Vout ) relative to the fundamental. Based on Eq. (2) we just need to calculate (ID3 − ID2 ). By squaring expression (5), we obtain: (VRF1 − VRF2 )2 =
2 (Iss − 2 ID3 ID2 ) with Iss = ID3 + ID2 n Cox (w/L) (6)
(3) Given that: 2 4ID3 ID2 = (ID3 + ID2 )2 − (ID3 − ID2 )2 = Iss − (ID3 − ID2 )2
By squaring expression (6) and after a serie of simplifications, we obtain ID2 − ID3 =
Fig. 2. Gilbert cell architecture.
1 n Cox (w/L)VRF 2
4Iss 2 − VRF n Cox (w/L)
(7)
Fig. 4. Resistance degeneration circuit.
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m1
0
m1 freq=100.0MHz dB(Vout)=-14.358
-50 -100
dB(Vout)
3
-150 -200 -250 -300 -350 0.0
0.5
1.0
1.5
2.0
2.5
3.0
freq, GHz Fig. 7. Frequency output spectrum.
Fig. 5. Proposed RL degeneration. 2 2 /4(V We pose ˛ = VRF GS − VTH ) , with ˛ 1, enabling us 1/2 to write: (1 − ˛) ∼ 1 − (1/2)˛, then for a small input signal VRF (1.2) = Vm cos(ωt), Eq. (8) becomes:
0
dB(VRF)
m2 freq=1.900GHz dB(VRF)=-23.098
ID2 − ID3 ≈ n Cox (w/L)(VGS − VTH ) Vm cos(ωt) −
m2
3 cos3 ωt Vm
8(VGS − VTH )2
(9)
Given that transconductance of CMOS on saturation is: gm = -50 0.0
0.5
1.0
1.5
2.0
2.5
∂ID w = n Cox (VGS − VTH ) L ∂VGS
From some calculations we find:
3.0
freq, GHz
ID2 − ID3 ≈ gm Vm −
Fig. 6. Frequency input spectrum at 1.9 GHz.
− gm
Iss being equal to the double of drain current of transistors, Eqs. (7) and (3) lead to: ID2 − ID3 =
1 n Cox (w/L)VRF 2
= n Cox (w/L)VRF (VGS − VTH )
1−
3 3Vm
32(VGS − VTH )2
cos ωt
3 cos 3ωt Vm
(11)
32(VGS − VTH )2
Resulting Vm from RF signal is too small, it can be assumed 2 3 /32(V that: Vm (3Vm GS − VTH ) ), which gives the amplitude ratio expression of the output (Vout ) third harmonic relative to the fundamental:
2 4(VGS − VTH )2 − VRF
(10)
2 VRF
(8)
4(VGS − VTH )2
3 Ah3 3Vm = Af 32(VGS − VTH )2
(12)
600
T=10ns
ts(Vout),Vm
400 200 0 -200 -400 -600 0
2
4
6
8
10
12
14
16
18
20
time, nsec Fig. 8. Output signal.
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2.3.2. Degeneration circuit From this analysis, one hand; mixer linearity increases by reducing the ratio (11), other hand by making linear the expression of equivalent circuit transconductance (12):
m1
20
m1 Power_RF=11.600 Line2=18.313 IM3 Line2 Vout_dBm1
0
Gm =
(13)
Generally, degeneration topology (Fig. 4) [6] is one of the most often used for mixers: Given that ID = f(VGS ), Eq. (13) becomes: Gm = (∂f/∂VGS )(∂VGS /∂VRF ) and VGS = VRF − Rs ID „ then:
-20
-40 -40
-30
-20
-10
0
10
20
Gm =
Power_RF
1 − Rs
∂ID ∂VRF
∂f ∂VGS
(14)
Being ∂f/∂VGS the transconductance gm of M1, Eq. (14) leads to:
Fig. 9. Third order interception point (IIP3).
Gm =
m1
4.0
∂ID ∂VRF
gm 1 + gm Rs
(15)
Voltage gain will then be:
m1 freq=100.0MHz Vout.noise=3.970nV
Vout.noise, nV
3.9
Gv =
3.8
3.7
3.6
3.5 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
freq, GHz Fig. 10. Output noise.
m2 freq=1.900GHz VRF.noise=901.2pV
907
VRF.noise, pV
906
(16)
And for Rs 1/gm : Gm ≈ 1/Rs which gives ∂ID ≈ ∂VRF /Rs ; it is therefore a linear variation of drain current relative to the input signal. The issue is, if we increase Rs , it reduces the Gain of circuit, then it conflict to evaluating parameters circuit. R-L degeneration circuit is able to fill this constraint (Fig. 5): Since the amplitude of RF signal (Vm ) arises from LNA circuit, value choices (R and L) of proposed degeneration circuit will increases the IIP3 value without affecting gain. Based on (Fig. 5): VGS = − UR (UR is the voltage across R) Then, when increasing R, VGS increases, therefore and according to Eq. (12), IIP3 value increases. Concerning the gain of circuit: Gm =
908
−gm Rd 1 + gm Rs
∂f ∂VGS = ∂VGS ∂VRF
1 − Lω ·
∂ID ∂VRF
gm = (1 − Lω · Gm )gm
(17)
Then equivalent transconductance of circuit is: Gm =
905
gm 1 + gm Lω
(18)
L is very low; it has no impact on Gm , consequently on the circuit voltage gain Gv = −Gm Rd .
904 903 902
3. Simulation results
m2
901 900 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
freq, GHz
IDS.i, mA
Fig. 11. Input noise.
m1 Vdd=1.800 IDS.i=1.208mA m1
1.208274
On Agilent ADS tool, lengths (65 nm) of MOSFETs channel were chosen to maximize gain, to minimize noise and to optimize the footprint of the circuit. The width of RF input MOSFET was chosen maximum with respect to current consumption specifications [3]. The bias current of M1 (Fig. 2) is fixed by keeping the bias voltage of CMOS at Vdd = 1.8 V.
Values at bias point indicated by marker m1. Move marker to update. Device Power Consumption, Watts
VDS
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1.80000
0.00217
Vdd Fig. 12. Power consumed by circuit.
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Table 1 Summary result and performance comparison.
GC (dB) IIP3 (dBm) Power (mW) NF (dB) Tech RF (GHz)
This worka
[7] a
[6] a
[8] a
[9]
[10] b
[11] b
8.75 11.6 2.02 4.12 65 nm 1.9
13.97 1.7 2.02 3.13 65 nm 1.9
9.12 10.45 30.78 9.74 0.18 m 1.9
12.42 6 2.02 8.92 65 nm 1.9
10 5 – 12 – –
5.3 +17 4.6 >−6 3.5 4.5 21.7 7.1 0.18 m 0.13 m 2.4 0.05–6.5
[12] a
[13] c
[14] a
[15] c
[16] a
[17] c
13 22.3 6 −3.3 8.6 34 −3.08 −10.8 −4.34 −10.3 6.7 4 0.48 0.905 10.8 7.56 0.423 3 12.7 7.2 7.35 16.5 19.2 10 0.13 m 0.13 m 0.18 m 0.13 m 0.11 m 0.13 m 2.5 2.4 1.56 2.4 2.4 0.402–0.405
[18] a 17.5 −7.2 – 13.5 0.13 m 2.1
a
Simulation result. Measurment result. c Simulation result of LNA-Mixer architecture. [9] Typical characteristics values (B. Razavi). [18] Values are raised from simulation curves. [10] Simulation values of IIP3 and NF are respectively equal to: 3.9 dBm and 19.4 dB. b
VRF and VLO frequencies are respectively 1.9 and 1.8 GHz which provides an intermediate frequency of 100 MHz. Choice of these values gives an IF frequency as agreed to meet most of the wireless networks deployed today, and operating frequency around 1 GHz, such as GSM. The principal parameters adopted to characterize RF mixer are: Conversion Gain, Noise Figure and Linearity [5].
references made here as a comparison, an excellent power consumption is found, which justifies the right technique adopted with the degeneration used and the good commutation of transistors M2 and M3 without a power loss.
3.1.1. Transient and harmonics responses
The purpose is to reveal the feasibility of a Gilbert Cell Mixer in RF chain, dedicated to low power consumption wireless applications; with 65 nm CMOS technology, in order to minimize size as well the power consumption. Theoritical study to increase linearity without degrading conversion gain was achieved. The most important parameters characterizing an RF mixer were simulated, and results shows the performance of this choice compared to recent technologies, also the optimized number of components has enabled us to minimize the power consumed by this circuit.
The following graphs (Figs. 6–8) show that the proposed circuit realizes the function of mixing frequencies: Output signals show a frequency value equal to 100 MHz. Other unwanted harmonics are due to non-linearity circuit, according to Figs. 6 and 7 conversion gain is equal to 8.75 dB. 3.1.2. Order 3 interception point (IIP3) The following graph (Fig. 9) shows an IIP3 value equal to 11.6 dBm. 3.1.3. Noise Figure Curve noise in the input and in the output, are shown in Figs. 10 and 11. By Figs. 10 and 11 and the relation between Output, Input Noise and the Conversion Gain (NF = Nout /Nin ·CG), the Noise Figure is equal to 4.12 dB. 3.1.4. Power consumption DC simulation, allowed us to measure the power consumption of the mixer circuit which is 2.17 mW, with Vdd = 1.8 V. 4. Performances comparison Simulated performances of proposed design; miniaturized Gilbert-Cell with 65 nm-CMOS technology for 1.9 GHz GSM frequency, using R-L linearity degeneration circuit; are summarized in Table 1, and compared (for the same RF band) with the most recent approaches, including: typical characteristics of RF Mixer [9], and our latest works [6],[7] and [8]. Values of: Conversion Gain, IIP3, NF and Power Consumption are raised from curves (Figs. 6–12) and compared to recent simulation results, including simulation results of LNA-Mixer architecture as [13,15,17]. From Table 1, we note that present circuit achieves a very good trade between linearity and gain (IIP3 = 11.6 dBm and GC = 8.75 dB), Lower Noise, such as NF = 4.12 dB is the lower of values after NF of [7], and a miniaturized CMOS technology (65 nm) whilst keeping power consumption the lowest (after [12,13,16]). Although a polarization used is equal to 1.8 V, relatively large compared to
5. Conclusion
References [1] Rogers J, Plett C. Radio frequency integrated circuit design. Artech House Microwave Library; 2003, 5 p. [2] Silver JP. Gilbert cell mixer design tutorial. RF, RFIC, et Microwave Theory and Design; 2010 www.rfic.co.uk [3] Martineau B. Millimeter-Wave building blocks design methodology in CMOS 65 nm process using Agilent tools. In: ADS users’s group meeting. 2009. STMicroelectronics-Crolles/Minatec. [4] LEE. TH. The design of CMOS radio frequency integrated circuits. Cambridge: University Press; 1998. [5] Villegas M, et al. Digital radiocommunications 2/conception of RF integrated circuits and microwaves, Dunod; 1999. p. 219–22. [6] Faitah K, Mahmou R. Design of 1.9 GHz Gilbert-Cell Down conversion mixer with good linearity in 0.18 m CMOS technology. AMSE J Model Meas Contr Gen Phys Electr Appl 2012;85(1–2). [7] Mahmou R, Faitah K. A low power consumption Gilbert-Cell Mixer in 65 nm CMOS technology. In: International symposium of telecom and 8th JFMMA. 2013. [8] Mahmou R, Faitah: K. Conception of RF Mixer with a 65 nm CMOS technology dedicated to low power consumption wireless applications. In: Proceeding IEEE ICMCS’12. 2012. [9] Razavi B. RF microelectronics. Prentice Hall, Ptr; 1998. [10] Wei B-L, Dai Y-J. Analysis and design of 1.0-V CMOS mixer based on variable load technique. Microelectr J 2012;43:1003–9. [11] Augusto R, Ximenes, Swart JW. A CMOS wideband mixer for direct-conversion receivers (DCRs). In: 8th IEEE ICCDCS. 2012. [12] Shirazi AHM, Mirabbasi S. An ultra-low-voltage CMOS mixer using switched transconductance, current-reuse and dynamic-threshold-voltage gain-boosting techniques. 978-1-4673-0859-5/12/$31.00 ©2012 IEEE, no. 393–6. [13] Chong W-K, Ramiah H, Tan G-H, Vitee N, Kanesan J. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application. Int J Electron Commun (AEÜ) 2013, http://dx.doi.org/10.1016/j.aeue.2013.07.009. [14] Lai D, Chen Y, Wang X, Chen X. A CMOS single-differential LNA and current bleeding CMOS mixer for GPS receivers. In: Proceedings of ICCT 2010. 2010. p. 677–80. [15] Martins MA, Oliveira LB, Fernandes JR. Combined LNA and mixer circuits for 2.4 GHz ISM band. In: Proceedings of IEEE international symposium on circuits and systems. 2009. p. 425–8. [16] Chang C-H, Onabajo M. IIP3 enhancement of subthreshold active mixers. In: Circuits and systems II: IEEE transactions, vol. 60(11). 2013, November. p. 731–5.
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[17] Mohamed SAS, Manoli Y. Design of low-power direct-conversion RF front-end with a double balanced current-driven subharmonic mixer in 0.13 CMOS. In: Circuits and Systems I, IEEE Transactions, vol. 60(5). 2013, May. p. 1322–30. [18] Kim M-G, Yun T-Y. Analysis and design of feed forward linearity-improved mixer using inductive source degeneration. IEEE Trans Microw Theory Tech 2014;February:323–31. Raja Mahmou Received Professional License degree of Electrical Engineering (2007), Master of Electrical Engineering (2009), from Faculty of Sciences and Technics of Marrakech, at Cadi Ayyad University (UCAM) of Morocco. Now, PhD candidate in Conception of Analog Systems and RFIC at Laboratory Of Electrical Engineering and Control Systems (LGECOS), UCAM of Morocco, Actually, a Substitute Professor of Analog Electronic, RF CMOS Designs at ENSA Marrakech, author, co-author of publications and communications in some international journals and conferences.
Dr. Khalid Faitah was born in Rabat, Morocco, in June 1965. Received B.S. degree in electronics from Mohamed V University of science, Rabat, Morocco in 1988 and the M.S degree in signal processing in 1997 from Hassan II University of science, Casablanca, Morocco. Received Ph.D. degree in electronic at Ibn Tofal University of science, Kenitra, Morocco on 2003. In 2009 he graduated from HDR (Certificate of Accreditation to the search direction). He is now Professor at ENSA (National Institute of Applied Sciences), Department of Electrical Engineering in Cadi Ayyad University, Marrakech, Morocco where he teaches analog electronics, RF CMOS design, sensors and interface circuits and also is Responsible of the Electrical Engineering and Control Systems Laboratory, His research interests include signal integrity and analog RF CMOS design. He is the author, co-author and reviewer of several publications and communications in recognized journals and international conferences.
Please cite this article in press as: Mahmou R, Faitah K. High linearity, low power RF mixer design in 65 nm CMOS technology. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.04.006