Ultra low power and high gain switched CMOS gm-boosted current reused mixer for wireless multi-standard applications

Microelectronics Journal 45 (2014) 1575–1582

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Ultra low power and high gain switched CMOS g m
boosted current reused mixer for wireless multi-standard applications Sid-Ahmed Tedjini-Bailiche a,b,n, Mohamed Trabelsi a, Abdelhalim Slimane b, Mohand-Tahar Belaroussi b, Fayrouz Haddad c, Sylvain Bourdel d a

École Nationale Polytechnique d'Alger, Avenue Hacen Badi El Harrach, 16200 Algiers, Algeria Centre de Développement des Technologies Avancées, Cité 20 Août 1956 Baba Hassen, Algiers, Algeria c IM2NP – Polytech 38, rue Frédéric Joliot-Curie IMT Technopôle de Château Gombert, 13451 Marseille Cedex 20, France d Grenoble INPG/IMEP-LAHC – Minatec, 3 rue Parvis Louis Néel, CS 50257, 38016 Grenoble Cedex 1, France b

art ic l e i nf o

a b s t r a c t

Article history: Received 17 December 2013 Received in revised form 9 July 2014 Accepted 7 October 2014 Available online 27 October 2014

An ultra low power and low voltage down conversion mixer is presented in this paper for the frequency band of 1.8–2.4 GHz. Designed in 0:18 μm CMOS technology, the double balanced proposed mixer is composed by two cascaded stages. The first one is based on cross coupled capacitors technique in current reused topology providing a high voltage gain, while the second one employs a current reused transducer coupled to LO driven inverters to perform the down conversion. All the devices operate on moderate inversion for better trade-off between gain, linearity, and low power consumption. The post layout simulation shows a 23 dB of voltage gain conversion, an IIP3 of
2 dBm, with 300 μW of power consumption under 0.9 V voltage supply. & 2014 Elsevier Ltd. All rights reserved.

Keywords: Mixer Low power Multistandards Switched transconductance Current reuse Cross coupled capacitors gm
boosted

1. Introduction According to the recent advances in CMOS transceivers, multistandard idea is the key solution to figure out the dilemma between the rapid growth of communication standards and high level of integration needs of RF system architectures [1]. Besides, low power and low cost transceiver designs are highly recommended and encouraged by the market for an effective competitiveness. However, most of the building blocks in the RF section are known by their high power consumption and large silicon area. Therefore, sharing the hardware remains to be an important suggestion to reach low power and low cost purpose for such sections [2]. In this context, up and down conversions, which are mainly based on mixers as building blocks, are the two functions essentially used to perform the frequency translation in the transmission and receiving operation modes, respectively. In down conversion mode, the mixer of receiving path is always in post-position of low noise amplifier circuit. A shared mixer in this configuration is undoubtedly a challenging design to achieve frequency translation under multi-standard requirements including GSM (DCS1800, PCS1900), 3G (UMTS), Bluetooth and WLAN b/g.

n

Corresponding author. Phone: þ213 2135 1018. E-mail address: [email protected] (S.-A. Tedjini-Bailiche).

http://dx.doi.org/10.1016/j.mejo.2014.10.002 0026-2692/& 2014 Elsevier Ltd. All rights reserved.

As mixer topology, the double balanced configuration is more used then the single one for its benefit in terms of common mode unwanted signals cancellation such as a common mode noise. For such topologies, Gilbert cell is a conventional double balanced one that provides gain [3]. In general, a moderate gain could be necessary to reach front-end requirements when a differential LNA precedes the mixer. However, a high gain mixer performance is more appreciated to increase the whole front end gain. Besides, the high gain needs an appropriate biasing leading to high power consumption and low linearity performances. Therefore, mixer design is still challenging to make trade-off between those performances. For instance, lowering the supply voltage to reduce the power is challenging task due to stacked stages of Gilbert cell. In pseudo differential mixers, the stacked stages are reduced to three to operates at low supply voltage [4]. However, it is often combined with a bleeding technique for a high gain purpose leading to additional current consumption. Switched transconductors represent a good alternative to the conventional Gilbert cell by employing LO driven inverters instead of commuting stages [5]. As inverters operate in linear mode, less headroom is needed even for three stacked stages. In [6], the same technique is reported using a current reuse configuration to achieve a high gain conversion. All transistors operate in weak inversion inducing some benefits on linearity as

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shown in Section 3.3. This mode of operation becomes more attractive for best trade off between gain and power consumption. However, the frequency response is poor compared with the strong inversion mode [7]. Obviously, the moderate inversion mode seems the best choice for the best gain and power dissipation compromise. Moreover, some other techniques were reported to reduce power consumption in front-end circuits for wireless applications. For instance, a cross coupled mixer is presented in [8]. A cross coupled LNA combined with current reuse is also used in [9]. In [10], the transconductance of common gate LNA is boosted using cross coupled technique. In this work, a multi-standard switched transconductance mixer is addressed to operate in range frequency of 1.8–2.4 GHz. Operating in moderate inversion mode, the proposed mixer is based on two cascaded stages. The first one consists of the cross coupled current reused capacitor providing a high voltage gain. The switching operation is performed in the second stage, also based on the current reuse providing an additional gain conversion. This paper is organized as follows: the second section describes the employed current reused and gm boosted techniques. The mixer design is presented in Section 3. The simulation results and discussion are presented in Section 4.

RL

RL vout

vout vin

vin

−A

Fig. 2. Transconductance: (a) common gate and (b) cross coupled.

id+

id−

Cc

2. Background 2.1. Current reuse

Cc v RF

The current reuse technique is widely used in amplifiers and mixers to improve the gain and to save the power consumption [11–13]. To increase the effective transconductance of the amplifier in Fig. 1a, the current reuse technique is simply implemented by stacking the NMOS and PMOS transistors as depicted in Fig. 1b. The DC voltage gain of this topology is given by GV ¼ ðg mN þ g mP Þðr dsN J r dsP Þ

ð1Þ

where gmN, gmP represent the transconductances of active devices NMOS and PMOS respectively, while rdsN and rdsP are their output resistances. 2.2. Cross coupled capacitor transconductance The common gate amplifier depicted in Fig. 2a is an alternative topology to the common source amplifier. It offers the capability of simple matching to 50 Ω by choosing the size of NMOS transistor for g m ¼ 20 ms [14]. However, in this condition, the drawback of this amplifier is undoubtedly its high noise figure, and relatively low gain compared to the common source amplifier. As shown is Fig. 2b, the g m boosted topology was initially introduced in [15] to decrease the noise figure and to increase the effective transconductance in common gate amplifier. The technique of the topology uses an inverting amplification value, A, as

Fig. 3. Cross coupled capacitor differential transconductance.

shown in Fig. 2b, the current ids is given by ids ¼ g m ð1 þ AÞvin

ð2Þ

where ð1 þ AÞg m represents the effective transconductance of the g m
boosted topology denoted by Gm;eff , which is much higher then the intrinsic MOS transconductance for the same DC power dissipation and specific value of a passive inverted amplification A: Gm;eff ¼ ð1 þ AÞg m

ð3Þ

This latter could be easily obtained by using a capacitive cross coupling technique in differential form as depicted in Fig. 3 [15,8]. According to the figure above, the inverting amplification value, A, is approximately given by the capacitive voltage division ratio as follows [8]: A¼

Cc C c þcgs

which leads to an effective transconductance of
 2C c þ C gs gm Gm;eff ¼ C c þ C gs

ð4Þ

ð5Þ

Thus, C c b C gs results in Gm;eff  2g m . 2.3. Switching operation

RL vout

+vin

vout

+v in

Fig. 1. (a) Common source amplifier and (b) current reuse amplifier.

The switched transconductance is an efficient technique used to perform the down conversion operation under a low voltage supply. As depicted in Fig. 5, the switched g m allows the reduction of the supply voltage by means of inverter stages instead of commuting stages. The gain conversion is given by [5]
 2 sin ðπ  f LO τsw Þ CG  ð6Þ g m RL π π  f LO τsw where τsw is the rising and falling times of the trapezoidal LO wave (Fig. 5). For an ideal LO, the τsw tends to zero leading to the well

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1577

vbp M7

M8

CC

M20

CC off chip

vRF

2.11 pF

M5

6.35 nH

M19

M6 M13 M14

M11 M12

vLO

+vIF

t

5.19 nH

−vIF M3 1:2

CC vbn

M4

M9

M15 M16

M10

CC

M18 M2

M1

M17

Fig. 4. Proposed double balanced mixer.

102

RL

vIF

RL

0.05

101

vRF 100

0

IC

g3

vx vLO

10−1

vx

t

-0.05 10−2

τ sw

10−3 0.2

Fig. 5. Switched transconductance mixer.

2

π

g m RL :

3.1. Low power and high linearity constraints In saturation mode, the weak, moderate, and strong inversions are the three MOSFET operation regions that depend on the overdrive voltage. For sub-micron MOSFET devices, the drain current model that allows to handle these operation regions is expressed as follows [16,17]: ð8Þ

where


 vgs
vth X ¼ 2ηϕt ln 1 þ exp 2ηϕt

0.5 0.6 VGS (V)

0.7

-0.1 0.8

In order to define and illustrate the operation regions, the inversion coefficient I C is defined as follows [18]:

Fig. 4 depicts the complete double balanced proposed mixer. In addition to the matching network, the proposed mixer is composed of two cascaded stages where the first one is based on a cross coupled capacitor amplifier in current reuse configuration, and the second stage is simply a switched transconductance. The biasing circuit is not shown for simplicity purpose.

μ0 C ox W X 2 2nL 1 þ θX

0.4

ð7Þ

3. Proposed core mixer

ID ¼

0.3

Fig. 6. Inversion coefficient simulation for a fixed V DS in 0:18 μm CMOS process technology.

known gain conversion of Gilbert cell as follows: CG 

Ic g3

ð9Þ

IC ¼

ID 2nμ0 C ox ϕt

2


 W L

ð10Þ

Fig. 6 shows the inversion coefficient versus the applied voltage vgs . Thus, the MOSFET device operates in weak inversion for I C o 0:1, in moderate inversion when 0:1 o I C o 10 and in strong inversion for I C 410 [18]. In order to choose one of the above regions of operation, the power efficiency and linearity are two constraints to be considered in the proposed design. In terms of power efficiency, the g m =I D ratio is the most relevant indicator that translate power into transconductance [19]. In Fig. 7, the variation of I D =g m ratio with I D shows clearly that the weak and moderate inversion operation modes offer clearly the best trade-off between power dissipation and transconductance which is more attractive for low power applications. However, the moderate inversion region is more appropriate in terms of MOSFET's linearity as shown in Fig. 6, since the thirdorder transconductance g 3 reaches the zero-crossing at the middle of the moderate inversion zone leading to a good trade-off between transconductance, linearity, and low power dissipation.

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45

25

40

22.5

35

20

Gv (dB)

gm / IDS (V -1)

1578

30

17.5

25

15

20

12.5 0

2.5p

5p

7.5p

10p

12.5p 15p

Cc (F)

15 10−11

10−10

10−9

10−8

10−7

10−6

10−5

Fig. 9. Voltage gain conversion variation at 2.4 GHz versus C c capacitor with f IF ¼ 50 MHz.

IDS (A) Fig. 7. g m =I D ratio variation with ID consumption for 0:18 μm CMOS process technology.

vRF

id+

CGD X

CC

C DS

CGS

0

vout 2 −5

RO

id+

IIP3 (dBm )

(gm3 + gm5)vgs

id−

−10

−15 W17=14 μ m W17=16 μ m W17=18 μ m W17=20 μ m

−20

+ Cc

Cc

− −25 0.3

vRF Fig. 8. Small signal equivalent model of cross coupled capacitor differential transconductance.

Fig. 4 depicts the proposed mixer in a double balanced configuration and composed of two cascaded stages. The first stage is based on cross coupled capacitor amplifier in current reuse configuration while the second is simply a switched transconductance topology. All MOSFETs of the first stage operate in moderate inversion to reach a good trade off between gain, power dissipation, and linearity as mentioned in Section 3.1. Fig. 8 shows the equivalent small signal circuit of the g m
boosted amplifier cell where its voltage gain can be derived from the KCL at the node X. Thus, the total conversion gain of the proposed mixer is equal to the voltage gain multiplication of the two cascaded stages Gv1 and Gv2 as given in the following expression, while the details of the derivation is reported in Appendix A:

GV ¼

0.4

0.45

0.5

0.55

0.6

VGS (V) Fig. 10. IIP3 variation with vgs for different inverters devices size.

Table 1 Mixer design dimensions.

3.2. Gain conversion

ð1 þ AÞðg m;3 þ g m;5 Þ þ jωðC ds
C gd Þ þ

0.35

1 r0

1 þ jωðC ds þ C gd Þ r0
 2 sin ðπ  f LO τsw Þ ðg m;9 þ g m;11 ÞRL  π π  f LO τsw

ð11Þ

MOSFET

W=L (μm)

M 1;2 M 3;4 M 5;6 M 7;8 M 9;10;13;14 M 11;12;15;16 M 17;19 M 18;20

20/0.5 16/0.18 77/0.18 80/0.5 18/0.18 90/0.18 18/0.18 90/0.18

where C gd and C ds represent the capacitance of the equivalent transistor of the current reuse cell (M 5 , M 3 ) and r 0 its output resistance. Analytically, the maximum gain conversion is related to the maximum inverting amplification value, A, which, in turn, depends on the achievable capacitor C C value in CMOS technology. Therefore, the gain conversion variation with C C value is shown in Fig. 9 at f RF ¼ 2:4 GHz and f IF ¼ 50 MHz. The maximum gain conversion of 24 dB could be reached for large C C values inducing a large design area. Therefore, a capacitor value of 4 pF is graphically chosen where the gain conversion reaches a 98% of

S.-A. Tedjini-Bailiche et al. / Microelectronics Journal 45 (2014) 1575–1582

1579

Fig. 11. Mixer layout without pads.

−10

30

−15 −20

20

−25 −30

Gv (dB)

−35 −40 −45 1.5G

10

0 1.75G

2G

2.25G

2.5G

p ost layou t @1.8 GHz p ost layou t @2.1 GHz p ost layou t @2.4 GHz sch em atic @ 2.4 GHz

2.75G

−10

Fig. 12. Input return loss S11 .

its maximum value. If the mixer devices are sized to obtain g m;3 ¼ g m;5 and g m;9 ¼ g m;11 , the voltage gain becomes 1
 4g m;3 þ jωðC ds
C gd Þ þ 4g m;9 sin ðπ  f LO τsw Þ r0 RL  GV ¼ 1 π π  f LO τsw þ jωðC ds þC gd Þ r0

−20 103

104

105

106

107

108

109

1010 1011

IF Freq (Hz)

ð12Þ

Fig. 13. Post layout simulation of the gain conversion for different RF bands.

when high gain is provided by the first stage [14]: 1



1 IIP321

þ

G2V1 IIP322

ð13Þ

3.3. Linearity

IIP32mixer

In the proposed mixer, the second stage is used to perform the switching operation. However, this stage dominates the linearity performance of the whole mixer according to Eq. (13), especially

where GV 1 is the gain of the cross coupled capacitor amplifier stage while IIP31 and IIP32 denote the IIP3 of the first and second stages, respectively.

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The output current of the depicted switched transconductance in Fig. 4 is given by iout ¼ Gm vgs þ G2 v2gs þ G3 v3gs þ ⋯

ð14Þ

where vgs represents the gate to source voltage applied to the switched transconductance devices. Because of finite series resistance of the couple inverters formed by M 17 ; M 18 and M 19 ; M 20 , the second stage experiences a negative feedback effect witch leads to second order interaction [20]. As shown in Appendix B, when the current reuse configuration is used instead of the common source stage, the third order transconductance of the second stage denoted G3 is given by ! g 22;9 g m;9 RON;17 1 G3 ¼ g
2 3;9 g m;9 1 þ g m;9 RON;17 ð1 þ g m;9 RON;17 Þ4 ! g 22;11 g m;11 RON;20 1 g
2 þ ð15Þ 3;11 g m;11 1 þ g m;11 RON;20 ð1 þ g m;11 RON;20 Þ4 According to Eq. (15), the mixer linearity is simply maximized for G3 ¼ 0. This can be done by sizing the transistors of the current reuse cell and those of the commuting inverters leading to proper values of the resistances (RON;17 , RON;20 ) of the couple of transistors (M 17 ; M 20 ) and (M 18 ; M 19 ). To reach this goal, the mixer's IIP3 is simulated to illustrate its variation with vgs for different transistor sizes of the inverters as shown in Fig. 10. The IIP3 reaches its peak value of
2.5 dBm for W 17 ¼ 18 μm at vgs ¼ 0:54 while the g 3 approaches its minimum value as suggested in Fig. 6. The RON;17 and RON;20 values, which are obtained by a proper sizing, cancels out the residual g 3 leading to an optimal IIP3 value. 25 0

VOUT (dB)

−25

−50

−75

−100

−125 −50

−40

Finally, Table 1 summarizes the design values of the mixer components.

−30

−20

−10

0

P RF (dB) Fig. 14. Input 3rd order intercept point.

4. Post layout simulation results and discussion Fig. 11 shows the layout of the proposed mixer without pads. The layout occupies about 0.115 mm2 of silicon active area. The four C C capacitors of the first stage represent the fifth of the total area. All of the analysis and preformed results of the proposed mixer are obtained by simulation using SpectreRF tool. Moreover, as the proposed mixer interacts with its external environment, additional off-chip input and output passive networks are designed and added as shown in Fig. 4. The passive band-pass filter is employed for the core mixer matching with the RF source of 50 Ω to receive RF signals in the frequency range of 1.8–2.4 GHz. This input matching network is followed by a transformer balun to create differential input RF signal. A second balun is also added at the output of the mixer to perform the conversion from differential to single ended output (not shown in Fig. 4). In Fig. 12, the simulated input return loss S11 is performed by the periodic S parameter analysis and reported in smith chart where jS11 jo
10 dB for all the band of interest. The DC voltage gain conversion of the mixer is about 26 dB while the cut-off frequency at
3 dB is about 60 MHz for the RF input frequency of 1.8 GHz and 2.1 GHz using a 6 dBm rail to rail LO signal. For 2.4 GHz RF input frequency, the conversion gain is about 23 dB as shown in Fig. 13. Fig. 14 represents the IIP3 of the proposed mixer which reaches
2 dB for the 2.4 GHz standard. The complete mixer consumes a total DC current of 335 μA from a supply voltage of 0.9 V. The mixer figure of merit (FOM) is defined in Eq. (16) [13]. It includes most of the mixer critical performances such as gain conversion, linearity, minimum power dissipation, and noise figure. Table 2 shows the performance comparison with the recent state of the art in CMOS mixer design: ! 10ðG þ IIP3
10Þ=20 FOM ¼ 10 log ð16Þ 10NF=10  P dc With a gain conversion of 23 dB and power dissipation of 300 μW, the proposed mixer is more power efficient than the reported mixers in Table 2. The proposed mixer operates under a low voltage supply even for four stacked stages which is suitable for low voltage applications. In [6], the reported mixer uses a similar switched transconductance technique, but the proposed mixer achieves a better gain conversion. In terms of linearity, the

Table 2 Performances comparison with reported multi-standard CMOS mixer. Ref. [5] [6] [6] [13] [18] [21] [22] [23] [24] [25] This work a b c

Freq (GHz) 0.5–6 2.5 2.5 2.4 5.2 1.63 0.2–13 0.5-7.5 2.4 2.4 1.8–2.4

Computed for 2 GHz. The IIP3 is estimated as P
1 dB þ 10 dB. At 2.4 GHz.

Gain (dB) 7.4–10.2 15.8 13 15.7 3.2 6.63 9.9 5.7 18 19 23–26

IIP3 (dBm) 5–7
8.6
3.08 1
8 1.51
10
5.7 – 3
2c

V dd (V) 1 0.5 0.35 1.8 0.6 1.8 0.8 0.77 – – 0.9

Pdc (mW) 0.42–0.95 1.6 0.48 8.1 0.8 – 0.88 0.48 0.5 4.25 0.3

NF (B) 22.8–24.7 10.56 12.7 12.9 14 21.43 11.7 15 9.6 11 16–20

FOM

Tech a

12.22 16 20.45 10.5 9.57 – 13.8 13.2 24.91b 18.72 20.73

0.18 0.13 0.13 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18

S.-A. Tedjini-Bailiche et al. / Microelectronics Journal 45 (2014) 1575–1582

reported mixers in [5,13,21] achieve better IIP3 with low gain conversion. However, the proposed mixer experiences good linearity, high gain conversion, and low power dissipation. To summarize these performances, the calculated FOM of the proposed mixer is higher than those of the other mixers as reported in the Table 2 except for [24] which presents a better noise performance.

1581

G1, G2, G3 gm, g2, g3

vin

vin iout = gmvgs

+

+

e

−

iout

RON RON

5. Conclusion Fig. B1. Feedback model.

The combination of cross coupled capacitors, current reuse, and switched transconductance techniques is successfully used to design a down conversion CMOS mixer. The proposed mixer is implemented in 0.18-μm CMOS technology in the range of frequency 1.8–2.4 GHz for wireless multi-standard applications. In terms of results, the mixer experiences a low power consumption under a low voltage by operating transistors devices in moderate inversion region. The proposed mixer achieves high gain conversion of 23 dB, high linearity of
2 dBm, a very low power consumption of 300 μW and moderate noise figure less than 18 dB.

where Gi ði ¼ 1; 2; 3; …Þ represents the i order transconductance expressed as 8 8 ∂iout > > > > > G1 ¼ ∂v > g m ¼ ∂iout > > > > in > > ∂e > > > > < < 1 ∂2 iout 1 ∂2 iout G2 ¼ g2 ¼ ðB:2Þ and 2 2 ∂v > > 2 ∂e2 in > > > > > > > > 1 ∂3 iout 1 ∂3 iout > > > > > : g3 ¼ G ¼ > : 3 6 ∂v3 6 ∂e3 in As shown is Fig. B1 e ¼ vin
RON iout

Appendix A The gate voltage of the transistor in Fig. 8 is approximated by a voltage divider as follows: vg 


Cc v C c þ C gs in

ðA:1Þ

thus, vgs can be expressed by 2C c þ C gs v vgs ¼ vg
vin ¼
C c þ C gs in

ðA:3Þ

where Z L ¼ 1=ð1=r o þ jωC ds Þ. Replacing vg and vgs , the voltage gain of the cross coupled capacitor amplifier of the Fig. 4 is jC c ωC gd 2C c þ C gs 1
ðg mn þ g mp Þ

jωC ds rO C c þ C gs vout C c þ C gs ¼ 1 vin
jωðC gd þ C ds Þ
rO

ðA:4Þ

Replacing A by the expression (4) and assuming C c b C gs , the above equation leads to vout ¼ vin

jωðC ds
C gd Þ
ð1 þ AÞðg mn þ g mp Þ
jωðC gd þ C ds Þ þ

1 rO

1 rO

ðA:5Þ

Assuming a finite switch-time inverters in Fig. 4, the voltage of the coupled source node is approximated by a trapezoidal function denoted pðtÞ. In this condition, the conversion gain of the second stage Gv2 is given by the multiplication of the expression (7) by the Fourier transform of pðtÞ which leads to Gv2 ¼ 2ðg mn þg mp ÞRL sin ðπτsw f LO Þ=π 2 τsw f LO . Thus, the total gain conversion is given by Eq. (11).

Appendix B The drain current of the MOS transistor is given by iout ¼ G1 vin þ G2 v2in þG3 v3in þ ⋯

G1 ¼

∂iout ∂e gm ¼ ∂e ∂vin 1 þ g m RON

ðB:4Þ

G2 ¼

1 ∂G1 ∂e g2 ¼ 2 ∂e ∂vin ð1 þ g m RON Þ3

ðB:5Þ

G3 ¼


 2g 22 RON 1 ∂G2 ∂e 1 ¼ g
3 3 ∂e ∂vin ð1 þ g m RON Þ4 1 þ g m RON

ðB:6Þ

ðA:2Þ

Using KCL at node X in Fig. 8:
 vout
vin ðvg
vout ÞjωC gd
ðg mn þg mp Þvgs
¼0 ZL

ðB:1Þ

ðB:3Þ

According to the definition of Gi and g i given by Eq. (B.2), the final expressions of G1 , G2 , and G3 are given by the following equations:

Therefore, for the current reuse configuration, the total G3 is given by Eq. (15). References [1] S. Wu, B. Razavi, A 900-MHz/1.8-GHz CMOS receiver for dual-band applications, IEEE J. Solid-State Circuits 33 (1998) 2178–2185. [2] A. Liscidini, M. Brandolini, D. Sanzogni, R. Castello, A 0.13-μm CMOS front-end for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier, IEEE J. Solid-State Circuits 41 (2006) 981–989. [3] B. Gilbert, A precise four-quadrant multiplier with subnanosecond response, IEEE J. Solid-State Circuits 3 (1968) 365–373. [4] S.A. Tedjini, A. Slimane, M.T. Belaroussi, M. Trabelsi, A 0.9 V high gain and high linear bleeding CMOS mixer for wireless applications, in: 24th International Conference on Microelectronics (ICM), 2012, pp. 1–4. [5] E.A.M. Klumperink, S. Louwsma, G.J.M. Wienk, B. Nauta, A CMOS switched transconductor mixer, IEEE J. Solid-State Circuits 39 (2004) 1231–1240. [6] A. Shirazi, S. Mirabbasi, An ultra-low-voltage CMOS mixer using switchedtransconductance current-reuse and dynamic-threshold-voltage gain-boosting techniques, in: IEEE 10th International New Circuits and Systems Conference (NEWCAS), 2012, pp. 393–396. [7] B. Perumana, R. Mukhopadhyay, S. Chakraborty, C.-H. Lee, J. Laskar, A lowpower fully monolithic subthreshold CMOS receiver with integrated LO generation for 2.4 GHz wireless PAN applications, IEEE J. Solid-State Circuits 43 (2008) 2229–2238. [8] W. Zhuo, S. Embabi, J. de Gyvez, E. Sanchez-Sinencio, Using capacitive crosscoupling technique in RF low noise amplifiers and down-conversion mixer design, in: Proceedings of the 26th European Solid-State Circuits Conference (ESSCIRC'00), 2000, pp. 77–80. [9] S.-T. Wang, A. Niknejad, R. Brodersen, Design of a Sub-mW 960-MHz UWB CMOS LNA, IEEE J. Solid-State Circuits 41 (2006) 2449–2456. [10] F. Belmas, F. Hameau, J. Fournier, A 1.3 mW 20 dB gain low power inductorless LNA with 4 dB Noise Figure for 2.45 GHz ISM band, in: Radio Frequency Integrated Circuits Symposium (RFIC), IEEE; Baltimore, MD, 2011, pp. 1–4. [11] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and mixer, IEEE J. Solid-State Circuits 31 (1996) 1939–1944. [12] F. Gatta, E. Sacchi, F. Svelto, P. Vilmercati, R. Castello, A 2-dB noise figure 900 differential CMOS LNA, IEEE J. Solid-State Circuits 36 (2001) 1444–1452.

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