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A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-μm CMOS technology
Microelectronics Journal 42 (2011) 113–126
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-mm CMOS technology Jun-Da Chen National Quemoy University, Department of Electronic Engineering, University Road, Jinning Township, Kinmen 892, Taiwan
a r t i c l e in fo
abstract
Article history: Received 6 August 2009 Received in revised form 17 August 2010 Accepted 19 August 2010 Available online 15 September 2010
This paper presents a wideband mixer chip covering the frequency range from 3.4 to 6.8 GHz using TSMC 0.18 mm CMOS technology. The linearity can be improved using multiple-gated-transistors (MGTR) topology. The measured 3-dB RF frequency bandwidth is from 3.1 to 6.8 GHz with an IF of 10 MHz. The measured results of the proposed mixer achieve 7.2–4.3 dB power conversion gain and 2–3 dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW, and the excellent LO–RF isolation achieved up to 54 dB at 5 GHz. The paper presents a mixer topology that is very suitable for low-power in ultra-wideband system applications. & 2010 Elsevier Ltd. All rights reserved.
Keywords: Gilber-cell mixers UWB MGTR IIP3
1. Introduction The UWB communication system has been widely used in short distance wireless local area networks, with a wide band and high bit rates. The multi-band orthogonal frequency division multiplexing (OFDM) UWB system uses a specific frequency band (3.1–5 or 3.1–10.6 GHz) to access data [1–6]. The IEEE 802.15.3a ultrawideband (UWB) system is currently considering direct-sequence code division multiple-access (DS-CDMA) and multi-band orthogonal frequency division multiplexing (MB-OFDM) as candidates for an international standard for wireless personal area networks (WPAN). According to the MB-OFDM specification, the UWB spectrum is divided into 14 bands, each with a bandwidth of 528 MHz. In addition, each band is composed of 128 sub-channels with a channel bandwidth of 4.125 MHz [5,6]. Fig. 1 shows the band structure of the MB-OFDM UWB applications. The first 12 bands are then grouped into four band groups, each consisting of three bands, and the last two bands are grouped into the fifth band group [6]. The focus of this work is to design a low-power direct-conversion mixer for an MB-OFDM UWB RF receiver, as shown in Fig. 2. The systems can remove off-chip IF filters because there are no image problems. In the direct-conversion architecture circuit design, CMOS technology can provide a single-chip solution which greatly reduces the cost, and is widely used in UWB receivers [5,6]. In the front-end system design, the linearity of the transceiver is dominated by mixers, because the receiver dynamic range is often limited by the first down-conversion mixer. The mixer plays an important role in
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improving overall system linearity. Passive and active mixers are two common topologies in recent research. The implementation of the CMOS down-conversion mixer can be passive or active. The passive mixer has high linearity [7]. Unfortunately, it does not provide a conversion gain, and owns higher conversion loss and noise figure. The active mixer includes a single-balanced Gilbert-cell mixer and double-balanced Gilbert-cell mixers. In the traditional Gilbert-cell mixer, high linearity and conversion gain under low voltage operation increase the bias current of transconductance. However, flicker noise and power consumption are also directly proportional to the amount of current [8]. The Gilbert-cell switched series transconductor (SwGm) mixer in [9] has been shown to be effective in increasing conversion gain, linearity, and sufficient isolation under low voltage supply. But it only displayed a narrowband response at 2 GHz and was not suitable for UWB system applications. Therefore, wideband input matching networks are applied to achieve a wide operating frequency. The linearity can be improved by using multiple-gated-transistors (MGTR) topology [10]. The remaining parts of this paper are organized as follows. In Section 2, the paper analyzes the mixer in detail and compares it with a traditional well-known double-balanced switching mixer (Gilbert cell). The low-voltage high-linearity mixer for directconversion UWB receiver improvement is proposed in Section 3. In Section 4, the implementation and measured results will be presented. Finally, the conclusion is summarized in Section 5.
2. Traditional Gilbert-cell mixers The traditional double balanced Gilbert mixer is chosen for investigation because its good LO to RF and LO to IF port isolation
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Group 1 Band Band #2 #3
Band #1
3432 3960
Band #4
4488
5016
Group 2 Band Band #5 #6
5544
Group 3 Group 4 Group 5 Band Band Band Band Band Band Band Band #8 #9 #10 #11 #13 #14 #7 #12
6072
6600
7128
7656
8184
8712
9240
9768
10296 M Hz
Fig. 1. The IEEE 802.15.3a spectrum.
I -channel mixer Mixer
Antenna RF Filter
LNA
0°
LO
mixer can be estimated by VIF 2 G ¼ 20log gm RL VRF p
I (+) I (-)
Balun LO
180°
Quad -VCO LO
RF
90°
LO
Q (+) Q (-)
Balun Q-channel mixer
Mixer
Fig. 2. A block diagram of the direct-conversion receiver including the proposed mixers.
VDD Load stage RL
RL
IF+ Switching stage
LO+
-IF
M3
M5
M4
M6
+LO
LO-
RF+
M2
M1
Transconductance stage
w ðVG VTH Þ L
ð2Þ
2 w G 20log mn Cox ðVG VTH ÞRL L p
ð3Þ
gm ¼ mn Cox
270°
-RF
IDC
where Cox is the gate capacitance per unit area, mn the mobility of electrons near the silicon surface, W the gate width, and L the effective gate length. RL represents the load resistance and gm the transconductance of M1 and M2. The operation principle is shown in Fig. 4. Assume LO is estimated by a sinusoidal wave, the conversion gain value can be conservatively estimated as [13] " # pffiffiffi VIF 2 2ðVGS VTH ÞSW G ¼ 20log gm RL 1 Þ ð4Þ VRF p pVLO where (VGS–VTH)SW represents the over-drive voltage of M3–M6. VLO is the amplitude of the LO signal. Transconductance stages (M1–M2) are operated in the triode region when the supply voltage is below 1 V. It cannot operate in the saturated region because it is difficult to obtain bias conditions and a sufficient level of voltage swing under a restricted supply voltage. Thus, the specification is barely satisfied. The traditional double-balanced Gilbert-cell switched transconductor mixer (SwGm) is shown in Fig. 5 [14]. The transconductance stages (M3–M6) are designed so the transistors can be operated in the saturation region. Moreover, switch stages (M1–M2) are designed so the transistors can be operated in the triode region when the supply voltage is below 1 V. The conversion gain of the mixer can be estimated by VIF 2 G ¼ 20log gm RL ð5Þ VRF p w ðVG VDS1 VTH Þ L
ð6Þ
2 w G 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð7Þ
gm ¼ mn Cox Fig. 3. CMOS Gilbert-cell mixer (GmSw).
release the DC offset problem, which is easily filtered out at the output [11]. Fig. 3 shows the main elements of the double balanced Gilbert mixer, including transconductance stages, switch stages, and the loads network (GmSw) [12]. The double balanced mixer has higher linearity compared to single balanced switching mixer. To achieve good linearity, conversion gain, and low noise, transistors (M1–M6) are designed to operate in the saturation region. The switch stages are driven by a local oscillation signal (VLO). The local oscillation (LO) signal must be large enough to make (M3–M6) act as switches. Thus, the large LO sinusoidal waveform can be considered square one to drive ideal switches. The mixer actually behaves as a multiplier to sample the RF signals. IRF is multiplied by an ideal square wave current IL. The conversion gain of the
ð1Þ
Comparing Eq. (3) with (7), the conversion gain of the Gilbertcell (GmSw) mixer is higher than the Gilbert-cell switching transconductor (SwGm) mixer. The main advantages of the SwGm mixer is that it can work even with a supply voltage lower than 1 V. Fig. 6 shows the use of the simulated switching waveforms current ILO. The switched series mixer (SwGm) is shown in Fig. 7. It consists of switch stages (M1–M4), transconductance stages (M5–M8), and the loads network. The switch stages are designed so the transistors can be operated in the triode region when the supply voltage is below 1 V. Furthermore, the transconductance stages are designed so that the transistors can be operated in the saturation region. We consider the operating description of the switching stages (M1–M4) of the MOS capacitor. A simplified
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
115
VLO+ (V) VLO- (V)
3 2
Frequency = 5GHz LO Power = 0d Bm = 0.223V Saturation region DC
-1 -2 -3
1.2V
ILO-
1 0
ILO+
+LO
LO-
DC1.2V
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
3 2
M4 ILO+ (mA)
M3
0
DC1.2V DC0.6V
M3 = M4 = 30/0.18
1 0 -1 -2 -3
1 +LO
3 2 ILO- (mA)
-1 1 +ILO 1
1 0 -1 -2 -3
-LO -1 ILO ILO+-ILO- (mA)
1 -ILO ILO+ - ILO1 ILO
3 2 1 0 -1 -2 -3
-1
Fig. 4. Simulated switching waveforms current ILO (GmSw).
VDD
Load stage
view of their bias-dependence can be obtained by observing the conditions in the channel region during cut-off and triode models. An MOS transistor can be viewed as a four-terminal device with capacitances between each terminal pair, as shown in Fig. 8. Cgb is the gate to bulk capacitance, Cgs is the gate to source capacitance, and Cgd is the gate to drain capacitance. The primary junction capacitances of interest are the source–bulk, Csb, and drain–bulk, Cdb, capacitance. When the MOS is operating in cut-off mode, the gate-to-source and the gate-to-drain capacitances both equal zero. The gate-to-substrate capacitance can be estimated by
RL
RL
IF+
-IF
Transconductance stage
RF+
M3
M5
M4
M6
RF+
Cgb ¼ Ccox WL
ð8Þ
-RF
LO+
Switching stage
M2
M1
IDC
Fig. 5. CMOS Gilbert-cell switched transconductor mixer (SwGm).
-LO
In linear-mode operation, the gate-to-substrate capacitance equals zero. The channel charge is roughly shared between the source and drain, so Cgs ¼Cgd. Their values can be conservatively estimated as Cgs ffi Cgd ffi 12Ccox WL
ð9Þ
The gate overlaps the source and drain junction by a small amount in a real device. This leads to additional overlap
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC 0.2V ILOLO+
3 2 1 0 -1 -2 -3 0
0.1
0
0.1
0
0
0.3
0.4
0.2 time, nsec
0.3
0.4
0.1
0.2 time, nsec
0.3
0.4
0.1
0.2 time, nsec
0.3
0.4
ILO+ M2
1 DC0.5V
DC0.5V
0.2 time, nsec
2
LOILO+ (mA)
M1
VLO+ (V) VLO- (V)
116
0 -1 -2
M1 = M2 = 30/0.18 1
2
+LO ILO- (mA)
-1 1 +ILO 1
1 0 -1 -2
-LO
1 -ILO ILO+ - ILO1
ILO ILO+ - ILO- (mA)
-1
ILO -1
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5
Fig. 6. Simulated switching waveforms current ILO (SwGm).
capacitance, and the overlap capacitance can be found as CgsðoverlapÞ ¼ Ccox WLov
ð10Þ
CgdðoverlapÞ ¼ Ccox WLov
ð11Þ
where the Lov is the overlap distance. The overlap capacitance is much smaller. Table 1 summarizes the approximate gate capacitance values in two different operating models [15]. These capacitances are proportional to the width of the transistor. Now we consider the voltage-dependent source–substrate and drain– substrate junction capacitances, Csb and Cdb, respectively. Due to bulk–source connection, the Csb will be about zero. The drain– bulk capacitance can be expressed as Cdb ¼ ASCJa þPSCjp
ð12Þ
where AS is the area of the drain diffusion, PS is the perimeter of the drain diffusion, Cdb is the drain–bulk capacitance, CJa is the drain–bulk capacitance per unit area under bias Vdb, and Cjp is the sidewall capacitance per unit length under bias Vdb. The MOS triode region channel resistance value can be conservatively estimated as 1 L rds ¼ ð13Þ mn COX ðVGS VTH Þ W
where rds is the small-signal drain–source resistance. Based on the above description, the choice of large sizes in M3–M4 will produce a large capacitance and reduce resistance. Define a unit nMOS transistor to have effective resistance R. An nMOS transistor of k times unit width has resistance R/k and capacitance KC. Fig. 9 shows a simplified switched series triode region RC model. Fig. 10 shows the use of the simulated series switching waveforms current ILO. Figs. 6 and 10 show the switching waveforms with and without M3–M4. Due to the choice of large W/L ratio for M3–M4, the circuit will discharge a negative current during the negative half cycle of the input voltage. Figs. 6 and 10 show that the simulated switching waveforms current ILO are 1.25 and 2.5 mA, respectively. Comparing Fig. 6 with Fig. 10, the current ILO of the proposed switched series stage is two times higher than the single switched stage. The conversion gain value can be conservatively estimated as VIF 4 G ¼ 20log gm RL ð14Þ VRF p where RL is the load resistance and gm is the transconductance of M5–M8. Due to the choice of large W/L ratio for M3, the VDS3 will approximate zero (VDS3 ffi0). The transconductance stages (M5–M8) are operated in the saturation region when the supply
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
3. The proposed mixer core analysis
VDD
Load stage
117
3.1. Gain
RL
RL
-IF
IF+ Transconductance stage
RF+
M6
M5
M8
M7
+RF
-RF M4
M3
-LO
LO+ M2
M1
IDC
Switching stage
Fig. 7. The switched series architecture mixer (SwGm).
D Cgd
Cdb
A complete schematic of the proposed mixer series-parallel switched stage is shown in Fig. 11. It consists of switch stages (M1–M8), transconductance stages (M9–M12), and the loads network. The bias voltage of VLO + and VLO and the W/L ratios of transistors M1–M8 are designed so that the transistors can be operated in the triode region when the supply voltage is below 1 V. Further, the bias voltage of VRF + and VRF and the W/L ratios of transistors M9–M12 are designed so that the transistors can be operated in the saturation region. We consider the LO stages operating a series-parallel in the triode region. Based on the above description, a simplified series-parallel switched triode region RC model is shown in Fig. 12. The parallel path will produce two times the capacitance value and reduce the resistance value by half. Fig. 13 shows the use of the simulated series switching waveforms current ILO. Figs. 10 and 13 show the simulated switching waveforms current (ILO) are 2.5 and 5 mA, respectively. Comparing Fig. 10 with Fig. 13, the current ILO of the proposed switched series-parallel is two times higher than the current from the switched series. In Fig. 13, we can express the LO signal as a square wave local oscillator sq(oLOt) and the RF signal as a sinusoidal wave vRF 7 ¼VRF sin oRFt. The IRF multiplied by an ideal square wave current ILO, sq(oLOt), alternates between +4 and –4. The conversion gain value can be conservatively estimated as v v IDC IDC RF RF þ gm IL , ID10 ¼ gm IL ID9 ¼ ð17Þ 4 4 4 4 ID11 ¼
G
rd
v IDC RF gm IL , 4 4
ID12 ¼
v IDC RF þ gm IL 4 4
ð18Þ
B IL ¼ sqðwLO tÞ
ð19Þ
IIF ¼ ðID9 þID11 ÞðID10 þ ID12 Þ ¼ ðID9 ID10 ÞðID12 ID11 Þ
ð20Þ
Csb
Cgs
S
IIF ¼ gm VRF sin wRF t sqðwLO tÞ 4 1 ¼ gm VRF sin wRF t 4 sin wLO t þ sin 3wLO t þ 3 p
Cgb
ð21Þ
Fig. 8. RC circuit models of an MOS transistor.
¼ Table 1 Approximation of intrinsic MOS gate capacitance.
gm VRF ½cosðwRF wLO ÞtcosðwRF þwLO Þt þ
VIF ¼
Capacitance
Cut-off
Triode
Cgb Cgs Cgd Cg ¼ Cgb + Cgs + Cgd
CoxWL CoxWLov CoxWLov CoxWL + 2CoxWLov
0 CoxWL/2 + CoxWLov CoxWL/2 + CoxWLov CoxWL + 2CoxWLov
voltage is below 1 V: w ðVG VDS1 VTH Þ L
ð15Þ
4 w G 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð16Þ
gm ¼ mn Cox
8
p
Comparing Eq. (7) with (16), the conversion gain of the switched series mixer is two times higher than the Gilbert-cell switching transconductor (SwGm) mixer.
8
p
Gnovel
gm VRF RL cosðwRF wLO Þt VIF 8 ¼ 20log gm RL VRF p
8 w Gnovel 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð22Þ
ð23Þ
ð24Þ
ð25Þ
According to Eq. (25), the conversion gain is directly proportional to the bias current causing a large voltage drop in RL. Thus, the voltage swing headroom decreases. The choice of RL will affect the conversion gain and the output swing. RL cannot be too large to suppress the output swing. Nevertheless, minimum RL is still required to maintain enough conversion gain, especially for low voltage operation. Comparing Eq. (16) with (25), the conversion gain of the proposed switched series-parallel mixer is two times higher than the switched series mixer. The main advantage of the proposed mixer is that it can work when the supply voltage is below 1 V. This is particularly an important improvement in the low power mixer design. Assuming LO is estimated by a sinusoidal wave, the conversion gain of the proposed mixer can be
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
D
Cgd3
Cdb3
M3 = 240/0.18 M1 = 30/0.18 M3/M1 = 8 Cdb3
rd3
D
Cgd3 = 8Cgd1
rds3 = 1/8rds1
Cgs3 = 8Cgs1 G
Cgs3 Cgd1
Cdb1
S D
G
rds1
Cgs1 S
S
Cgs1
Cdb1 = Cds1
D
9/8
G
Cgd1
Cdb1
rd1
9Cgd1 Cdb3 = Cds3 = 8Cds1
8/9 Cds1
rds1 9Cgs1 S
VLO+ (V) VLO- (V)
Fig. 9. A simplified switched series triode region RC model.
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC ILOM3
0.2V ILO+
LO-
0.1
0.2 time, nsec
0.3
0.4
M2
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
2 ILO+ (mA)
M1
0 M4
LO+ DC0.5V
3 2 1 0 -1 -2 -3
DC0.5V
M1 = M2 = 30/0.18 M3 = M4 = 240/0.18
1 0 -1 -2
1 +LO
2 ILO- (mA)
-1 1 +ILO -1 1 -LO
1 0 -1 -2
-1 1
-1 2
ILO+ - ILO-
ILO
ILO ILO+ - ILO- (mA)
-ILO
-2
3 2 1 0 -1 -2 -3
Fig. 10. Simulated switched series waveforms current ILO (SwGm).
estimated by Gnovel
" !# pffiffiffi VIF 8 2ðVG VDS1 VTH ÞSW ¼ 20log gm RL 1 VRF p pVLO
ð26Þ
where (VG–VDS1–VTH)SW represents the over-drive voltage of M1– M8 and VLO is the amplitude of the LO signal. According to (22), there are no LO and RF signals leakage if the input LO stage signal is an ideal square wave in the double-balanced Gilbert mixer. Therefore, the ideal double balanced mixers reject
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
119
LO-to-IF, RF-to-IF, and LO-to-RF feedthrough since the LO signal as a square wave is a differential structure. However, the LO input signal is actually a sinusoidal wave generated by the voltagecontrolled oscillator (VCO). Therefore, the ideal isolation is not being achieved.
choose a proper size and gate bias of the auxiliary MOSFET and then the combined transistors will yield g 00 m close to zero, as shown in Fig. 15. Since the auxiliary MOSFET is biased in subthreshold regime, this linearization method does not consume any extra power.
3.2. Linearity
3.3. Noise
The proposed core mixer adopts the switched series-parallel (SwGm) technique to improve the conversion gain and the MGTR technique to improve the linearity [10], as shown in Fig. 14. Using Taylor series expansion, the drain current of a common-source MOSFET can be expressed as
For the conventional double-balanced mixer (GmSw) in Fig. 3, an approximation for the total white noise has been derived as [8] 2R I Vo,2 n ¼ 8KTRL 1 þ g load þ ggm RL ð28Þ pA
iDS ¼ Idc þgm vgs þ
gum 2 g 00 m 3 v þ v þ 2! gs 3! gs
ð27Þ
ðnÞ represents the nth-order transconductance and vgs the where gm gate-to-source voltage. In the MGTR technique, the negative g 00 m peak value can be canceled by another auxiliary MOSFET. We
VDD
Load stage RL
RF+
Vo,2
RL -IF
IF+ Transconductance stage
M10
M9
+RF
M12
M11 -RF
M5
M6
M7
M8 -LO
LO+ M1
M2
M3
M4
n
¼ 8KTRL ð1 þ 4ggm RL Þ
K COX WLf
D
G
Cgd6
Cdb5
rd5
Cgs5 Cgd1
ð30Þ
where W, L, and Cox represent the transistor’s width, length, and gate capacitance per unit area, respectively. The constant K is
Fig. 11. The switched series-parallel mixer design.
Cgd5
ð29Þ
where the first term is owing to the two load resistors, and the second term shows the noise of the transconductance stage transferred to the mixer output, assuming a conversion gain of 8/ p. In the conventional Gilbert-cell mixer (GmSw), the switching transistors can also significantly contribute to noise, especially at high LO frequency [8]. In comparison with the common-mode, the noise can be deleted so that the (SwGm) mixer has negligible 1/f noise from the switching transistors [14]. Comparing Eq. (28) with (29), we can exclude the terms with switching transistors. Therefore, this noise current can be canceled in the differential voltage output. According to this reason, the proposed mixer switching transistors do not contribute differential noise. The next step is the flicker-noise analysis. To appraise the flicker-noise contribution from the transconductance transistors, we need to know the flicker-noise behavior of MOS device. The flicker noise is modeled as a voltage source in series with the gate of value [9]: Vn2 ¼
IDC
Switching stage
where K is Boltzmann’s constant, T is the temperature in Kelvin, I is the bias current of the mixer, A is the LO amplitude, g 2=3 for long transistor devices and gm is the transconductance of the MOS devices. The first term is owing to the two load resistors, the second term is the output noise owing to the four switches, and the third term shows the noise of the transconductance stage transferred to the mixer output, assuming a conversion gain of 2/ p. Using the same example, an analysis similar to [8] for the proposed mixer results in
Cdb5
rd6
Cgs6 Cgd2
Cdb1
M5 = 240/0.18 M1 = 30/0.18 M5/M1 = 8
Cdb6
Cdb6
18Cgd1
G
Cdb2
M6 = 240/0.18 M2 = 30/0.18 M6/M2 = 8
D 16/9 Cds1
9/16 rds1
rd1
Cdb1
rd2
Cdb1
S 18Cgs1
Cgs1
S
Cgs2
S
Fig. 12. A simplified switched series-parallel triode region RC model.
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC 0.2V DC 0.2V ILO+
3 2 1 0 -1 -2 -3
VLO+ (V) VLO- (V)
120
ILO-
M5
M6 M7
-LO
LO+ M2 M3
M4
DC 0.5V
ILO+ (mA)
M1
DC 0.5V IDC M1 = M2 = 30/0.18 M5 = M6 = 240/0.18 1
ILO- (mA)
+LO -1 1 +ILO -1 1 -LO
-ILO 4
0.1
0.2 time, nsec
0.3
0.4
0
100
200 300 time, psec
400
0
0.1
0.2 0.3 time, nsec
0.4
0
0.1
0.2 0.3 time, nsec
0.4
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5
ADD M2, M6, M3, M7 Without M2, M6, M3, M7 (ILO+) - (ILO-) mA
-1 1 -1
0 M8
ILO+ - ILO-
ILO -4
6 4 2 0 -2 -4 -6
Fig. 13. Simulated switched series-parallel waveforms current ILO (SwGm).
VDD
Load stage
RL
RL IF+ Transconductance stage
M9
-IF
M13 M14
M11
M10
M51
M16
M12 +RF
RF+
-RF
M5
M7
M6
M8
LO+
-LO M1
Switching stage
M3
M2
M4
IDC
Fig. 14. The proposed mixer switched series-parallel core design and transconductance linearization using MGTR.
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Auxiliary
RF+
M13
M9
Vgs
gm ′′
Master
121
Vth
Vgs-Vshift
Gate to source voltage, Vgs (V)
Fig. 15. Schematic illustration of gm cancellation using MGTR.
CMFB
MIXER CORE
VDD
BUFFER
M17 M23
M22
M18 Vconf
M20
On chip
M21
M19
RF+
C7
R3
C8
R4
M26 M27
Vref
M9
M31 M14
M10
M11
M 15 M 16
M7
M8
IF+-IF
M12
RFM5
M6
M25
LO+ M1
M3
M2
M24
M4 vbias
LOIDC On chip Fig. 16. Complete schematic of the proposed mixer.
dependent on device characteristics and can vary widely for different devices in the same process. The 1/f noise is inversely proportional to the transistor area, WL. In other words, to increase the sizes of the transconductance transistors NF should be decreased for 1/f noise.
DC_BLOCK Master Auxiliary
C2 L1
C1
M9
RF+
R1
4. Mixer implementation and measured results Fig. 16 shows a complete schematic of the proposed mixer. The mixer consists of five major parts: transconductance stages (M9–M12), switching stages (M1–M8), MGTR circuitry (M13–M16), CMFB circuitry (M17–M23), and output buffers (M24–M27). The input matching networks of RF and LO are shown in Fig. 17. The passive components metal-insulator-metal (MIM) capacitors (C1–C3), poly/diffusion resistor (R1), and spiral inductor (L1) are adopted for matching the network at the input RF stage to resonate over the entire frequency band. Furthermore, we use one spiral inductor (L2), one poly/diffusion resistor (R2), and three metal-insulator-metal (MIM) capacitors (C4–C6) to match the
M13 Rg
Rg
C3 Vgs-Vshift
Vgs DC_BLOCK C4 LO+
L2
C5
R2
Rg
M5
M6
M1
M2
C6 Vgs Fig. 17. The input matching networks of RF and LO.
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VDD Vref
0
BUFFER
Measured RF return loss Simulated RF return loss
-5 CMFB
M17
-10 dB
M18 M26
Vconf
-15 -20
C7
R3
R4
C8
-25
M27
-30 M24
+ RF -
IF+-IF
0
M25
2
3
5 6 4 Frequency (GHz)
7
8
9
10
7
8
9
10
0
Rg + LO -
1
Measured RF return loss Simulated RF return loss
-5 vbias
-10 dB
Fig. 18. Simplified mixer schematic with load network.
-15 -20
DC PORT
-25 -30 0
2
1
3
4 5 6 Frequency (GHz)
RF PORT
LO PORT
Fig. 20. Measured RF and LO ports return loss.
9
IF PORT Fig. 19. Chip microphotograph.
input LO stage to resonate over the entire frequency band. The resistance Rg is added as a bias voltage resistance. Both RF and LO stage impedances have a value of 50 O. Fig. 18 shows the simplified mixer schematic consisting of a common-mode feedback (CMFB) circuitry [16] and a mixer core with two output buffer stages. Differential active PMOS loads instead of resistive loads are used here to increase the conversion gain without sacrificing the voltage swing headroom. The DC level at the mixer output is adjusted by a common-mode feedback (CMFB). The CMFB-loop is an amplifier comparing the reference voltage with the mixer output voltage and adjusts the DC current through the load resistors. The drain current of M21 is then adjusted and mirrored to the two PMOS connected in parallel with the load resistors. Transistors M19 through M23 serve as a CMFB circuit to set up the common-mode voltage. It is used to generate a stable dc level to the gates of M17–M18. With a high enough loop gain, Vref and Vcont will be about equal. The value of Vref is selected to optimize the linearity by allowing the maximum range of output voltage swing. The common-mode voltage level of the output nodes is designated to be about 0.75 V (Vref) by using a CMFB circuit. At a high frequency signal, C7 and C8 can be estimated to a short circuit. C7 and C8 can reject LO and RF signals at IF [10], and
Conversion Gain (dB)
8 7 6 5 RF at 3.4GHz (TT) RF at 5.0GHz (TT) RF at 6.8GHz (TT) RF at 7.3GHz (TT) RF at 8.4GHz (TT) RF at 9.5GHz (TT) RF at 10.0GHz (TT)
4 3 2 1 0 -40
-35
-30 -25 -20 RF Input power (dBm)
-15
-10
Fig. 21. Simulated conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm, TT represents the simulation results of typical-NMOS and typical-PMOS.
therefore reduce the noise figure. The RF signal is translated into the voltage signal by the load stage consisting of M17, M18, R3, and R4. The load stage provides output impedance through the resistive loads (that is, R3 and R4) and creates appropriate voltage swing headroom by the transistors (that is, M17 and M18). The buffer stage consisting of nMOS transistors (M24–M27) drive 50 O loads for measurement. The proposed UWB mixer is implemented in a 1P6M 0.18 mm CMOS process. Fig. 19 shows the microphotograph of the fabricated circuit with a chip area of 1.145 1.08 mm2 including the pad frames. The performance of the UWB mixer through on-wafer testing operates the RF signal with 30 dBm, and LO signal with 0 dBm. Both RF and LO frequency were swept from 3.4 to 6.8 GHz with a fixed IF
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
5
Conversion Gain (dB)
4 3 2 1
Conversion Gain (dB)
7 6 5 4 3 2
RF at 3.4GHz RF at 5.0GHz RF at 5.8GHz RF at 6.8GHz RF at 7.3GHz
1 0 -1 -40
-35
-20 -30 -25 RF Input power (dBm)
-15
-10
Fig. 24. Measured conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm.
10 9 8 7 6 5
Simulated 1.1V Simulated 1V Simulated 0.9V Simulated 0.8V
4 3 2
0
RF at 3.4GHz (SS) RF at 5.0GHz (SS) RF at 6.8GHz (SS) RF at 7.3GHz (SS) RF at 8.4GHz (SS) RF at 9.5GHz (SS) RF at 10.0GHz (SS)
-1 -2 -3 -4
1 0 -40
-5 -40
-30 -25 -20 RF Input power (dBm)
-35
-15
-10
Fig. 22. Simulated conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm, SS represents the simulation results of slow-NMOS and slowPMOS.
9 8 Conversion Gain (dB)
8
Conversion Gain (dB)
frequencies of 10 MHz. The total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW. The RF and LO ports impedance matching are 50 O, respectively. Fig. 20 shows RF and LO ports return loss, from 3 to 11 GHz; the measured results are less than –9 dB. Fig. 21 shows the simulated TT stand for typical model conversion gain with respect to the RF power. As shown in this figure, the simulated conversion gain displayed a 3-dB variation across the 3.4–9.5 GHz input frequency. Fig. 22 shows the simulated SS stand for typical model conversion gain with respect to the RF power. Fig. 23. shows the simulated conversion gain versus RF frequency. Fig. 24 shows the measured conversion gain with respect to the RF power. As shown in this figure, the measured results of conversion gain display a 3-dB variation across the 3.4–6.8 GHz input frequency. Fig. 25 shows the simulated TT stand for typical model conversion gain versus supply voltage at 5 GHz. As shown in this figure, the main advantages of the SwGm mixer is that it can work even with a supply voltage lower than 1 V. Comparing Fig. 21 with Fig. 22, and with Fig. 24, the measured conversion gain was between TT and SS typical model. The IM3 was measured, using two Agilnet E8247C continuous wave (CW) generators and an Agilent E4407B spectrum analyzer, as shown in Fig. 26. Fig. 27 shows the measured fundamental output power and third-order intermodu-
123
7 6 5 4 3
pre simulated IF = 10MHz (TT) pre simulated IF = 50MHz (TT) post simulated IF = 10MHz (TT) pre simulated IF = 100MHz (TT) pre simulated IF = 150MHz (TT)
2 1 0 3
4
5
6
7
8
9
10
11
RF Frequency (GHz) Fig. 23. Simulated conversion gain versus RF frequency, RF power is 30 dBm, and LO power is 0 dBm.
-35
-30 -25 -20 RF Input power (dBm)
-15
-10
Fig. 25. Simulated conversion gain versus supply voltage, LO power is 0 dBm at 3.4 GHz.
lation (IM3) with respect to the RF input frequency spacing of 10 MHz, and the IIP3 is 2 dBm at 3.4 GHz. Fig. 28 shows the IIP3 is 3 dBm at 6.8 GHz. Fig. 29 shows the measured isolation of LO-toRF and LO-to-IF at LO of 0 power are 54 and 43 dB at 5 GHz, respectively. Fig. 30 shows the measured RF-to-IF at RF of 30 power is 34.2 dB at 5 GHz. The simulation DSB noise figure minimum is 11.4–12 dB from 3 to 6.8 GHz as shown in Fig. 31. Due to the parasitic effect in the layout, the minimum of the measurement is 13.9–14.4 dB from 3 to 6.8 GHz. This result was measured by using the Agilnet N8975A noise-figure analyzer, but it cannot be measured at frequencies below 10 MHz. Table 2 summarizes the measured results and compares them with the data from previous wideband mixer literatures. As shown in [17], it requires high power consumption and a large supply voltage of 4.9 V. As shown in [17–19,21], Gilber-cell (GmSw) technology high power gain is barely satisfied when the supply voltage is below 1 V. References [18,20–22] require large power LO signal. Reference [20] only has core mixer power consumption, excluding from output source-follower. The Gilber-cell (GmSw) and distributed mixers cannot achieve the specification when the supply voltage is below 1 V [17–21]. The bulk-pumped mixers [22,23] can achieve low power consumption, but require a large power LO signal. Moreover, compared with previously published literature, the proposed mixer consumed a relatively low dc power of 2.9 mW under the supply voltage of 1 V. The mixer achieved high
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
ESA - ESeries Spectrum Analyzer (Agilent E4407B)
IF Balun RF Signal Generator
IF +
IF -
RF +
Balun
Ba lu n
RF-
LO+
LO Signal Generator
LO-
Agilnet E8247C
(Agilent E8247C)
DC Power Supply (HP 4142B) Fig. 26. IIP3 measured setup illustrated.
20 Fundamental IMD3
10
-42 Port to port isolation (dB)
Output Power (dBm)
0 -10 -20 -30 -40 -50 -60 -70
IIP3
-80 -40
-35
-30
-25
-20 -15 -10 -5 Input Power (dBm)
0
5
-45 -48 -51 -54
10
-10
Fig. 27. Measured IIP3 at 3.4 GHz.
-9
-8
-7
-6 -5 -4 -3 Input LO Power (dBm)
-1
-2
0
Fig. 29. Measured isolation of LO to IF and LO to RF at 5 GHz.
-32
20 Fundamental IMD3
10
Port to port isolation (dB)
0 Output Power (dBm)
LO-IF LO-RF
-10 -20 -30 -40 -50 -60 -70 -80
-33 RF-IF -34
-35
IIP3
-90
-36
-40
-35
-30
-25
-20 -15 -10 -5 Input Power (dBm)
Fig. 28. Measured IIP3 at 6.8 GHz.
0
5
10
-30
-25
-20 -15 -10 Input RF Power (dBm)
Fig. 30. Measured Isolation of RF to IF at 5 GHz.
-5
0
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
125
22 Measured IF = 10Mhz Post Simulated IF = 4.125Mhz Pre Simulated IF = 4.125Mhz Pre Simulated IF = 10Mhz Pre Simulated IF = 100Mhz
21 20 Noise Figure (dB)
19 18 17 16 15 14 13 12 11 10 3
4
5
6 7 8 RF Frequency (GHz)
9
10
11
Fig. 31. Measured and simulated DSB noise versus RF frequency, LO power is 0 dBm, and RF power is 30 dBm.
Table 2 Performances of CMOS UWB Mixers. Ref.
Process CMOS (mm)
LO power (dBm)
Gain (dB)
Freq. (GHz)
IF (MHz)
IIP3 (dBm)
NF (dB)
Die area (mm2)
V supply
PDC (mW)
Feature
[17]
0.18
1
0.3–25
10
–
–
0.8 1.0
4.9
71
Gilber-cell+ buffer (GmSw)
[18] [19] [20]
0.13 0.18 0.18
5 2 9
9.5– 12.5 5–12 5.5 5.2–2.5
9–50 0.2–16 3–8.72
10 528 528
– 0.5 0.5 – 0.68 0.65 6.8–7.3 (DSB) 1.14 1.16
3.3 1.8 1.8
97 15 10.4n
Gilber-cell+ buffer (GmSw) Gilber-cell+ buffer (GmSw) Distributed
[21]
0.18
3
2–27
10
2
40
0.18
5
0.5–7.5
100
5.7
14.3–17.0 (SSB) 15
0.87 0.82
[22]
11.5– 13.5 5.7–4.3
– – 5 (5 GHz) 0
0.86 0.72
0.77
0.48
[23]
0.13
13
3 to 1 10–35
100
–
–
0.6 0.4
1.6
6
This work
0.18
0
7.2–4.3
10
2–3
13.9–14.4 (DSB)
1.145 1.08
1
2.9
Distributed+ Gilber-cell+ buffer (GmSw) Bulk-pumped Gilber-cell+ buffer (GmSw) Bulk-pumped Gilber-cell+ buffer (GmSw) Gilber-cell+ buffer (SwGm)
n
3.4–6.8
Only core mixer
Table 3 Device sizes of the proposed mixer. Device
Design values
Device
Design values
MN1–MN4 MN5–MN8 MN9–MN12 MN13–MN16 MP17–MP18 MN19–MN21 MP22–MP23 MN24–MN25 MN26–MN27 R1 R2
30/0.18 (W/L) 240/0.18 (W/L) 90/0.18 (W/L) 72/0.18 (W/L) 512/0.18 (W/L) 15/0.18 (W/L) 512/0.18 (W/L) 304/0.18 (W/L) 300/0.2 (W/L) 101.4 O 141.2 O
R3–R4 Rg C1 C2 C3 C4 C5 C6 C7–C8 L1 L2
1.2 kO 1.5 kO 7.74 pF 0.951 pF 4.90 pF 9.52 pF 0.042 pF 7.62 pF 1.9 pf 1.46 nH 1.32 nH
linearity using the MGTR topology under the low voltage. The device sizes of the mixer are shown in Table 3.
5. Conclusion A MGTR series-parallel Gilber-cell (SwGm) UWB mixer topology has been presented in the above results, which can operate at 1-V supply voltage in a 0.18-mm CMOS technology. In
the proposed topology, the narrowband mixer can be converted into a wideband mixer by the RLC matching method. The LO switched series-parallel system was applied to reduce the supply voltage and dc power consumption. The linearity can be improved by using MGTR topology. The main advantages of the mixer topology contain low dc power consumption, low supply voltage, high-linearity, and moderate power gain. The proposed mixer is suitable for UWB system applications.
Acknowledgment The author would like to thank the National Chip Implementation Center (CIC), Taiwan, for technical support. References [1] R. Harjani, J. Harvey, R. Sainati, Analog/RF physical layer issues for UWB systems, in: Proceedings of the 17th International Conference on VLSI Design, 2004, pp. 941–948. [2] A. Tsitouras, F. Plessas, Ultra wideband, low-power, 3–5.6 GHz, CMOS voltage-controlled oscillator, Microelectron. J. March (2009). [3] K. Zhang, S. Cheng, X. Zhou, W. Li, R. Liu, A wide band differentially switchtuned CMOS monolithic quadrature VCO with a low KVCO and high linearity, Microelectron. J. (2009).
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[4] A. Phan, C.W. Kim, Y.A. Shim, S.G. Lee, A high performance CMOS direct down conversion mixer for UWB system, IEICE Trans. Electron. e88-c (12) (2005) 2316–2321. [5] A. Tanaka et al., A 1.1 V 3.1-to-9.5 GHz MB-OFDM UWB transceiver in 90 nm CMOS, in: IEEE International Solid-State Circuits Conference (ISSCC) Digest Technical Papers, February 2006, pp. 120–121. [6] H. Zheng, S. Lou, D. Lu, C. Shen, A 3.1–8.0 GHz single-chip transceiver for MBOFDM UWB in 0.18-mm CMOS process, IEEE J. Solid-State Circuits 44 (2) (2009) 414–426. [7] A.A. Hafez, M.A. Dessouky, H.F. Ragai, Design of a low-power ZigBee receiver front-end for wireless sensors, Microelectron. J. (2009). [8] H. Darabi, A.A. Abidi, Noise in RF-CMOS mixer: a simple physical model, IEEE J. Solid-State Circuits 35 (1) (2000) 15–25. [9] J.D. Chen, Z.M. Lin, J.S. Row, A 2-GHz low-power down-conversion mixer in 0.18-0mm CMOS technology, IEICE Trans. Electron. e91-c (1) (2008) 64–71. [10] T.W. Kim, B. Kim, K. Lee, Highly linear receiver front-end adopting MOSFET transconductance, IEEE J. Solid-State Circuits 39 (1) (2004) 223–229. [11] T.Y. Yang, H.L. Tu, H.K. Chiou, Low-voltage high-linear and isolation transformer based mixer for direct conversion receiver, in: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2006, pp. 21–24. [12] P.J. Sullivan, B.A. Xavier, W.H. Ku, Low voltage performance of a microwave CMOS Gilbert cell mixer, IEEE J. Solid-State Circuits 32 (7) (1997) 1151–1155. [13] C.C. Tang, C.H. Wu, W.S. Feng, S.I. Liu, A 2.4 GHz low voltage CMOS downconversion double-balanced mixer, IEICE Trans. Electron. e84-c (2001) 1084–1091. [14] E.A.M. Klumperink, S. M., G.J.M. Wienk, B. Nauta, A CMOS switched transconductor mixer, IEEE J. Solid-State Circuits 39 (8) (2004) 1231–1240.
[15] N.H.E. Weste, David Harris, in: CMOS VLSI Design, 3rd ed., Addison Wesley, Reading, 2005. [16] C.C. Meng, S.K. Xu, T.H. Wu, M.H. Chao, G.W. Huang, A high isolation CMFB downconversion micromixer using 0.18-mm deep n-well CMOS technology, in: Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC), June 2003, pp. 619–622. [17] C.S. Lin, P.S. Wu, H.Y. Chang, H. Wang, A 9–50 GHz Gilbert-cell downconversion mixer in 0.13-mm CMOS technology, IEEE Microwave Wireless Components Lett. 16 (5) (2006) 293–295. [18] M.D. Tsai, H. Wang, A 0.3–25 GHz ultra-wideband mixer using commercial 0.18-mm CMOS technology, IEEE Microwave Wireless Components Lett. 14 (11) (2004) 522–524. [19] F.C. Chang, P.C. Huang, S.F. Chao, H. Wang, A low power folded mixer for UWB system applications in 0.18-mm CMOS technology, IEEE Microwave Wireless Components Lett. 17 (5) (2007) 367–369. [20] A.Q. Safarian, A. Yazdi, P. Heydari, Design and analysis of an ultrawide-band distributed CMOS mixer, IEEE Trans. Very Large Scale Integration (VLSI) Systems 13 (5) (2005) 618–628. [21] C.R. Wu, H.H. Hsieh, L.H. Lu, An ultra-wideband distributed active mixer MMIC in 0.18-mm CMOS technology, IEEE Trans. Microwave Theory Techn. 55 (4) (2007) 625–632. [22] K.H. Liang, H.Y. Chang, Y.J. Chan, A 0.5–7.5 GHz ultra low-voltage low-power mixer using bulk-injection method by 0.18-mm CMOS technology, IEEE Microwave Wireless Components Lett. 17 (7) (2007) 531–533. [23] C.L. Kuo, B.J. Huang, C.C. Kuo, K.Y. Lin, A 10–35 GHz low power bulk-driven mixer using 0.13 mm CMOS process, IEEE Microwave Wireless Components Lett. 18 (7) (2008) 455–457.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-mm CMOS technology Jun-Da Chen National Quemoy University, Department of Electronic Engineering, University Road, Jinning Township, Kinmen 892, Taiwan
a r t i c l e in fo
abstract
Article history: Received 6 August 2009 Received in revised form 17 August 2010 Accepted 19 August 2010 Available online 15 September 2010
This paper presents a wideband mixer chip covering the frequency range from 3.4 to 6.8 GHz using TSMC 0.18 mm CMOS technology. The linearity can be improved using multiple-gated-transistors (MGTR) topology. The measured 3-dB RF frequency bandwidth is from 3.1 to 6.8 GHz with an IF of 10 MHz. The measured results of the proposed mixer achieve 7.2–4.3 dB power conversion gain and 2–3 dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW, and the excellent LO–RF isolation achieved up to 54 dB at 5 GHz. The paper presents a mixer topology that is very suitable for low-power in ultra-wideband system applications. & 2010 Elsevier Ltd. All rights reserved.
Keywords: Gilber-cell mixers UWB MGTR IIP3
1. Introduction The UWB communication system has been widely used in short distance wireless local area networks, with a wide band and high bit rates. The multi-band orthogonal frequency division multiplexing (OFDM) UWB system uses a specific frequency band (3.1–5 or 3.1–10.6 GHz) to access data [1–6]. The IEEE 802.15.3a ultrawideband (UWB) system is currently considering direct-sequence code division multiple-access (DS-CDMA) and multi-band orthogonal frequency division multiplexing (MB-OFDM) as candidates for an international standard for wireless personal area networks (WPAN). According to the MB-OFDM specification, the UWB spectrum is divided into 14 bands, each with a bandwidth of 528 MHz. In addition, each band is composed of 128 sub-channels with a channel bandwidth of 4.125 MHz [5,6]. Fig. 1 shows the band structure of the MB-OFDM UWB applications. The first 12 bands are then grouped into four band groups, each consisting of three bands, and the last two bands are grouped into the fifth band group [6]. The focus of this work is to design a low-power direct-conversion mixer for an MB-OFDM UWB RF receiver, as shown in Fig. 2. The systems can remove off-chip IF filters because there are no image problems. In the direct-conversion architecture circuit design, CMOS technology can provide a single-chip solution which greatly reduces the cost, and is widely used in UWB receivers [5,6]. In the front-end system design, the linearity of the transceiver is dominated by mixers, because the receiver dynamic range is often limited by the first down-conversion mixer. The mixer plays an important role in
E-mail address: [email protected] 0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.08.019
improving overall system linearity. Passive and active mixers are two common topologies in recent research. The implementation of the CMOS down-conversion mixer can be passive or active. The passive mixer has high linearity [7]. Unfortunately, it does not provide a conversion gain, and owns higher conversion loss and noise figure. The active mixer includes a single-balanced Gilbert-cell mixer and double-balanced Gilbert-cell mixers. In the traditional Gilbert-cell mixer, high linearity and conversion gain under low voltage operation increase the bias current of transconductance. However, flicker noise and power consumption are also directly proportional to the amount of current [8]. The Gilbert-cell switched series transconductor (SwGm) mixer in [9] has been shown to be effective in increasing conversion gain, linearity, and sufficient isolation under low voltage supply. But it only displayed a narrowband response at 2 GHz and was not suitable for UWB system applications. Therefore, wideband input matching networks are applied to achieve a wide operating frequency. The linearity can be improved by using multiple-gated-transistors (MGTR) topology [10]. The remaining parts of this paper are organized as follows. In Section 2, the paper analyzes the mixer in detail and compares it with a traditional well-known double-balanced switching mixer (Gilbert cell). The low-voltage high-linearity mixer for directconversion UWB receiver improvement is proposed in Section 3. In Section 4, the implementation and measured results will be presented. Finally, the conclusion is summarized in Section 5.
2. Traditional Gilbert-cell mixers The traditional double balanced Gilbert mixer is chosen for investigation because its good LO to RF and LO to IF port isolation
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Group 1 Band Band #2 #3
Band #1
3432 3960
Band #4
4488
5016
Group 2 Band Band #5 #6
5544
Group 3 Group 4 Group 5 Band Band Band Band Band Band Band Band #8 #9 #10 #11 #13 #14 #7 #12
6072
6600
7128
7656
8184
8712
9240
9768
10296 M Hz
Fig. 1. The IEEE 802.15.3a spectrum.
I -channel mixer Mixer
Antenna RF Filter
LNA
0°
LO
mixer can be estimated by VIF 2 G ¼ 20log gm RL VRF p
I (+) I (-)
Balun LO
180°
Quad -VCO LO
RF
90°
LO
Q (+) Q (-)
Balun Q-channel mixer
Mixer
Fig. 2. A block diagram of the direct-conversion receiver including the proposed mixers.
VDD Load stage RL
RL
IF+ Switching stage
LO+
-IF
M3
M5
M4
M6
+LO
LO-
RF+
M2
M1
Transconductance stage
w ðVG VTH Þ L
ð2Þ
2 w G 20log mn Cox ðVG VTH ÞRL L p
ð3Þ
gm ¼ mn Cox
270°
-RF
IDC
where Cox is the gate capacitance per unit area, mn the mobility of electrons near the silicon surface, W the gate width, and L the effective gate length. RL represents the load resistance and gm the transconductance of M1 and M2. The operation principle is shown in Fig. 4. Assume LO is estimated by a sinusoidal wave, the conversion gain value can be conservatively estimated as [13] " # pffiffiffi VIF 2 2ðVGS VTH ÞSW G ¼ 20log gm RL 1 Þ ð4Þ VRF p pVLO where (VGS–VTH)SW represents the over-drive voltage of M3–M6. VLO is the amplitude of the LO signal. Transconductance stages (M1–M2) are operated in the triode region when the supply voltage is below 1 V. It cannot operate in the saturated region because it is difficult to obtain bias conditions and a sufficient level of voltage swing under a restricted supply voltage. Thus, the specification is barely satisfied. The traditional double-balanced Gilbert-cell switched transconductor mixer (SwGm) is shown in Fig. 5 [14]. The transconductance stages (M3–M6) are designed so the transistors can be operated in the saturation region. Moreover, switch stages (M1–M2) are designed so the transistors can be operated in the triode region when the supply voltage is below 1 V. The conversion gain of the mixer can be estimated by VIF 2 G ¼ 20log gm RL ð5Þ VRF p w ðVG VDS1 VTH Þ L
ð6Þ
2 w G 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð7Þ
gm ¼ mn Cox Fig. 3. CMOS Gilbert-cell mixer (GmSw).
release the DC offset problem, which is easily filtered out at the output [11]. Fig. 3 shows the main elements of the double balanced Gilbert mixer, including transconductance stages, switch stages, and the loads network (GmSw) [12]. The double balanced mixer has higher linearity compared to single balanced switching mixer. To achieve good linearity, conversion gain, and low noise, transistors (M1–M6) are designed to operate in the saturation region. The switch stages are driven by a local oscillation signal (VLO). The local oscillation (LO) signal must be large enough to make (M3–M6) act as switches. Thus, the large LO sinusoidal waveform can be considered square one to drive ideal switches. The mixer actually behaves as a multiplier to sample the RF signals. IRF is multiplied by an ideal square wave current IL. The conversion gain of the
ð1Þ
Comparing Eq. (3) with (7), the conversion gain of the Gilbertcell (GmSw) mixer is higher than the Gilbert-cell switching transconductor (SwGm) mixer. The main advantages of the SwGm mixer is that it can work even with a supply voltage lower than 1 V. Fig. 6 shows the use of the simulated switching waveforms current ILO. The switched series mixer (SwGm) is shown in Fig. 7. It consists of switch stages (M1–M4), transconductance stages (M5–M8), and the loads network. The switch stages are designed so the transistors can be operated in the triode region when the supply voltage is below 1 V. Furthermore, the transconductance stages are designed so that the transistors can be operated in the saturation region. We consider the operating description of the switching stages (M1–M4) of the MOS capacitor. A simplified
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
115
VLO+ (V) VLO- (V)
3 2
Frequency = 5GHz LO Power = 0d Bm = 0.223V Saturation region DC
-1 -2 -3
1.2V
ILO-
1 0
ILO+
+LO
LO-
DC1.2V
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
3 2
M4 ILO+ (mA)
M3
0
DC1.2V DC0.6V
M3 = M4 = 30/0.18
1 0 -1 -2 -3
1 +LO
3 2 ILO- (mA)
-1 1 +ILO 1
1 0 -1 -2 -3
-LO -1 ILO ILO+-ILO- (mA)
1 -ILO ILO+ - ILO1 ILO
3 2 1 0 -1 -2 -3
-1
Fig. 4. Simulated switching waveforms current ILO (GmSw).
VDD
Load stage
view of their bias-dependence can be obtained by observing the conditions in the channel region during cut-off and triode models. An MOS transistor can be viewed as a four-terminal device with capacitances between each terminal pair, as shown in Fig. 8. Cgb is the gate to bulk capacitance, Cgs is the gate to source capacitance, and Cgd is the gate to drain capacitance. The primary junction capacitances of interest are the source–bulk, Csb, and drain–bulk, Cdb, capacitance. When the MOS is operating in cut-off mode, the gate-to-source and the gate-to-drain capacitances both equal zero. The gate-to-substrate capacitance can be estimated by
RL
RL
IF+
-IF
Transconductance stage
RF+
M3
M5
M4
M6
RF+
Cgb ¼ Ccox WL
ð8Þ
-RF
LO+
Switching stage
M2
M1
IDC
Fig. 5. CMOS Gilbert-cell switched transconductor mixer (SwGm).
-LO
In linear-mode operation, the gate-to-substrate capacitance equals zero. The channel charge is roughly shared between the source and drain, so Cgs ¼Cgd. Their values can be conservatively estimated as Cgs ffi Cgd ffi 12Ccox WL
ð9Þ
The gate overlaps the source and drain junction by a small amount in a real device. This leads to additional overlap
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC 0.2V ILOLO+
3 2 1 0 -1 -2 -3 0
0.1
0
0.1
0
0
0.3
0.4
0.2 time, nsec
0.3
0.4
0.1
0.2 time, nsec
0.3
0.4
0.1
0.2 time, nsec
0.3
0.4
ILO+ M2
1 DC0.5V
DC0.5V
0.2 time, nsec
2
LOILO+ (mA)
M1
VLO+ (V) VLO- (V)
116
0 -1 -2
M1 = M2 = 30/0.18 1
2
+LO ILO- (mA)
-1 1 +ILO 1
1 0 -1 -2
-LO
1 -ILO ILO+ - ILO1
ILO ILO+ - ILO- (mA)
-1
ILO -1
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5
Fig. 6. Simulated switching waveforms current ILO (SwGm).
capacitance, and the overlap capacitance can be found as CgsðoverlapÞ ¼ Ccox WLov
ð10Þ
CgdðoverlapÞ ¼ Ccox WLov
ð11Þ
where the Lov is the overlap distance. The overlap capacitance is much smaller. Table 1 summarizes the approximate gate capacitance values in two different operating models [15]. These capacitances are proportional to the width of the transistor. Now we consider the voltage-dependent source–substrate and drain– substrate junction capacitances, Csb and Cdb, respectively. Due to bulk–source connection, the Csb will be about zero. The drain– bulk capacitance can be expressed as Cdb ¼ ASCJa þPSCjp
ð12Þ
where AS is the area of the drain diffusion, PS is the perimeter of the drain diffusion, Cdb is the drain–bulk capacitance, CJa is the drain–bulk capacitance per unit area under bias Vdb, and Cjp is the sidewall capacitance per unit length under bias Vdb. The MOS triode region channel resistance value can be conservatively estimated as 1 L rds ¼ ð13Þ mn COX ðVGS VTH Þ W
where rds is the small-signal drain–source resistance. Based on the above description, the choice of large sizes in M3–M4 will produce a large capacitance and reduce resistance. Define a unit nMOS transistor to have effective resistance R. An nMOS transistor of k times unit width has resistance R/k and capacitance KC. Fig. 9 shows a simplified switched series triode region RC model. Fig. 10 shows the use of the simulated series switching waveforms current ILO. Figs. 6 and 10 show the switching waveforms with and without M3–M4. Due to the choice of large W/L ratio for M3–M4, the circuit will discharge a negative current during the negative half cycle of the input voltage. Figs. 6 and 10 show that the simulated switching waveforms current ILO are 1.25 and 2.5 mA, respectively. Comparing Fig. 6 with Fig. 10, the current ILO of the proposed switched series stage is two times higher than the single switched stage. The conversion gain value can be conservatively estimated as VIF 4 G ¼ 20log gm RL ð14Þ VRF p where RL is the load resistance and gm is the transconductance of M5–M8. Due to the choice of large W/L ratio for M3, the VDS3 will approximate zero (VDS3 ffi0). The transconductance stages (M5–M8) are operated in the saturation region when the supply
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
3. The proposed mixer core analysis
VDD
Load stage
117
3.1. Gain
RL
RL
-IF
IF+ Transconductance stage
RF+
M6
M5
M8
M7
+RF
-RF M4
M3
-LO
LO+ M2
M1
IDC
Switching stage
Fig. 7. The switched series architecture mixer (SwGm).
D Cgd
Cdb
A complete schematic of the proposed mixer series-parallel switched stage is shown in Fig. 11. It consists of switch stages (M1–M8), transconductance stages (M9–M12), and the loads network. The bias voltage of VLO + and VLO and the W/L ratios of transistors M1–M8 are designed so that the transistors can be operated in the triode region when the supply voltage is below 1 V. Further, the bias voltage of VRF + and VRF and the W/L ratios of transistors M9–M12 are designed so that the transistors can be operated in the saturation region. We consider the LO stages operating a series-parallel in the triode region. Based on the above description, a simplified series-parallel switched triode region RC model is shown in Fig. 12. The parallel path will produce two times the capacitance value and reduce the resistance value by half. Fig. 13 shows the use of the simulated series switching waveforms current ILO. Figs. 10 and 13 show the simulated switching waveforms current (ILO) are 2.5 and 5 mA, respectively. Comparing Fig. 10 with Fig. 13, the current ILO of the proposed switched series-parallel is two times higher than the current from the switched series. In Fig. 13, we can express the LO signal as a square wave local oscillator sq(oLOt) and the RF signal as a sinusoidal wave vRF 7 ¼VRF sin oRFt. The IRF multiplied by an ideal square wave current ILO, sq(oLOt), alternates between +4 and –4. The conversion gain value can be conservatively estimated as v v IDC IDC RF RF þ gm IL , ID10 ¼ gm IL ID9 ¼ ð17Þ 4 4 4 4 ID11 ¼
G
rd
v IDC RF gm IL , 4 4
ID12 ¼
v IDC RF þ gm IL 4 4
ð18Þ
B IL ¼ sqðwLO tÞ
ð19Þ
IIF ¼ ðID9 þID11 ÞðID10 þ ID12 Þ ¼ ðID9 ID10 ÞðID12 ID11 Þ
ð20Þ
Csb
Cgs
S
IIF ¼ gm VRF sin wRF t sqðwLO tÞ 4 1 ¼ gm VRF sin wRF t 4 sin wLO t þ sin 3wLO t þ 3 p
Cgb
ð21Þ
Fig. 8. RC circuit models of an MOS transistor.
¼ Table 1 Approximation of intrinsic MOS gate capacitance.
gm VRF ½cosðwRF wLO ÞtcosðwRF þwLO Þt þ
VIF ¼
Capacitance
Cut-off
Triode
Cgb Cgs Cgd Cg ¼ Cgb + Cgs + Cgd
CoxWL CoxWLov CoxWLov CoxWL + 2CoxWLov
0 CoxWL/2 + CoxWLov CoxWL/2 + CoxWLov CoxWL + 2CoxWLov
voltage is below 1 V: w ðVG VDS1 VTH Þ L
ð15Þ
4 w G 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð16Þ
gm ¼ mn Cox
8
p
Comparing Eq. (7) with (16), the conversion gain of the switched series mixer is two times higher than the Gilbert-cell switching transconductor (SwGm) mixer.
8
p
Gnovel
gm VRF RL cosðwRF wLO Þt VIF 8 ¼ 20log gm RL VRF p
8 w Gnovel 20log mn Cox ðVG VDS1 VTH ÞRL L p
ð22Þ
ð23Þ
ð24Þ
ð25Þ
According to Eq. (25), the conversion gain is directly proportional to the bias current causing a large voltage drop in RL. Thus, the voltage swing headroom decreases. The choice of RL will affect the conversion gain and the output swing. RL cannot be too large to suppress the output swing. Nevertheless, minimum RL is still required to maintain enough conversion gain, especially for low voltage operation. Comparing Eq. (16) with (25), the conversion gain of the proposed switched series-parallel mixer is two times higher than the switched series mixer. The main advantage of the proposed mixer is that it can work when the supply voltage is below 1 V. This is particularly an important improvement in the low power mixer design. Assuming LO is estimated by a sinusoidal wave, the conversion gain of the proposed mixer can be
118
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
D
Cgd3
Cdb3
M3 = 240/0.18 M1 = 30/0.18 M3/M1 = 8 Cdb3
rd3
D
Cgd3 = 8Cgd1
rds3 = 1/8rds1
Cgs3 = 8Cgs1 G
Cgs3 Cgd1
Cdb1
S D
G
rds1
Cgs1 S
S
Cgs1
Cdb1 = Cds1
D
9/8
G
Cgd1
Cdb1
rd1
9Cgd1 Cdb3 = Cds3 = 8Cds1
8/9 Cds1
rds1 9Cgs1 S
VLO+ (V) VLO- (V)
Fig. 9. A simplified switched series triode region RC model.
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC ILOM3
0.2V ILO+
LO-
0.1
0.2 time, nsec
0.3
0.4
M2
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
0
0.1
0.2 time, nsec
0.3
0.4
2 ILO+ (mA)
M1
0 M4
LO+ DC0.5V
3 2 1 0 -1 -2 -3
DC0.5V
M1 = M2 = 30/0.18 M3 = M4 = 240/0.18
1 0 -1 -2
1 +LO
2 ILO- (mA)
-1 1 +ILO -1 1 -LO
1 0 -1 -2
-1 1
-1 2
ILO+ - ILO-
ILO
ILO ILO+ - ILO- (mA)
-ILO
-2
3 2 1 0 -1 -2 -3
Fig. 10. Simulated switched series waveforms current ILO (SwGm).
estimated by Gnovel
" !# pffiffiffi VIF 8 2ðVG VDS1 VTH ÞSW ¼ 20log gm RL 1 VRF p pVLO
ð26Þ
where (VG–VDS1–VTH)SW represents the over-drive voltage of M1– M8 and VLO is the amplitude of the LO signal. According to (22), there are no LO and RF signals leakage if the input LO stage signal is an ideal square wave in the double-balanced Gilbert mixer. Therefore, the ideal double balanced mixers reject
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
119
LO-to-IF, RF-to-IF, and LO-to-RF feedthrough since the LO signal as a square wave is a differential structure. However, the LO input signal is actually a sinusoidal wave generated by the voltagecontrolled oscillator (VCO). Therefore, the ideal isolation is not being achieved.
choose a proper size and gate bias of the auxiliary MOSFET and then the combined transistors will yield g 00 m close to zero, as shown in Fig. 15. Since the auxiliary MOSFET is biased in subthreshold regime, this linearization method does not consume any extra power.
3.2. Linearity
3.3. Noise
The proposed core mixer adopts the switched series-parallel (SwGm) technique to improve the conversion gain and the MGTR technique to improve the linearity [10], as shown in Fig. 14. Using Taylor series expansion, the drain current of a common-source MOSFET can be expressed as
For the conventional double-balanced mixer (GmSw) in Fig. 3, an approximation for the total white noise has been derived as [8] 2R I Vo,2 n ¼ 8KTRL 1 þ g load þ ggm RL ð28Þ pA
iDS ¼ Idc þgm vgs þ
gum 2 g 00 m 3 v þ v þ 2! gs 3! gs
ð27Þ
ðnÞ represents the nth-order transconductance and vgs the where gm gate-to-source voltage. In the MGTR technique, the negative g 00 m peak value can be canceled by another auxiliary MOSFET. We
VDD
Load stage RL
RF+
Vo,2
RL -IF
IF+ Transconductance stage
M10
M9
+RF
M12
M11 -RF
M5
M6
M7
M8 -LO
LO+ M1
M2
M3
M4
n
¼ 8KTRL ð1 þ 4ggm RL Þ
K COX WLf
D
G
Cgd6
Cdb5
rd5
Cgs5 Cgd1
ð30Þ
where W, L, and Cox represent the transistor’s width, length, and gate capacitance per unit area, respectively. The constant K is
Fig. 11. The switched series-parallel mixer design.
Cgd5
ð29Þ
where the first term is owing to the two load resistors, and the second term shows the noise of the transconductance stage transferred to the mixer output, assuming a conversion gain of 8/ p. In the conventional Gilbert-cell mixer (GmSw), the switching transistors can also significantly contribute to noise, especially at high LO frequency [8]. In comparison with the common-mode, the noise can be deleted so that the (SwGm) mixer has negligible 1/f noise from the switching transistors [14]. Comparing Eq. (28) with (29), we can exclude the terms with switching transistors. Therefore, this noise current can be canceled in the differential voltage output. According to this reason, the proposed mixer switching transistors do not contribute differential noise. The next step is the flicker-noise analysis. To appraise the flicker-noise contribution from the transconductance transistors, we need to know the flicker-noise behavior of MOS device. The flicker noise is modeled as a voltage source in series with the gate of value [9]: Vn2 ¼
IDC
Switching stage
where K is Boltzmann’s constant, T is the temperature in Kelvin, I is the bias current of the mixer, A is the LO amplitude, g 2=3 for long transistor devices and gm is the transconductance of the MOS devices. The first term is owing to the two load resistors, the second term is the output noise owing to the four switches, and the third term shows the noise of the transconductance stage transferred to the mixer output, assuming a conversion gain of 2/ p. Using the same example, an analysis similar to [8] for the proposed mixer results in
Cdb5
rd6
Cgs6 Cgd2
Cdb1
M5 = 240/0.18 M1 = 30/0.18 M5/M1 = 8
Cdb6
Cdb6
18Cgd1
G
Cdb2
M6 = 240/0.18 M2 = 30/0.18 M6/M2 = 8
D 16/9 Cds1
9/16 rds1
rd1
Cdb1
rd2
Cdb1
S 18Cgs1
Cgs1
S
Cgs2
S
Fig. 12. A simplified switched series-parallel triode region RC model.
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Frequency = 5GHz LO Power = 0d Bm = 0.223V Triode region DC 0.2V DC 0.2V ILO+
3 2 1 0 -1 -2 -3
VLO+ (V) VLO- (V)
120
ILO-
M5
M6 M7
-LO
LO+ M2 M3
M4
DC 0.5V
ILO+ (mA)
M1
DC 0.5V IDC M1 = M2 = 30/0.18 M5 = M6 = 240/0.18 1
ILO- (mA)
+LO -1 1 +ILO -1 1 -LO
-ILO 4
0.1
0.2 time, nsec
0.3
0.4
0
100
200 300 time, psec
400
0
0.1
0.2 0.3 time, nsec
0.4
0
0.1
0.2 0.3 time, nsec
0.4
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5
ADD M2, M6, M3, M7 Without M2, M6, M3, M7 (ILO+) - (ILO-) mA
-1 1 -1
0 M8
ILO+ - ILO-
ILO -4
6 4 2 0 -2 -4 -6
Fig. 13. Simulated switched series-parallel waveforms current ILO (SwGm).
VDD
Load stage
RL
RL IF+ Transconductance stage
M9
-IF
M13 M14
M11
M10
M51
M16
M12 +RF
RF+
-RF
M5
M7
M6
M8
LO+
-LO M1
Switching stage
M3
M2
M4
IDC
Fig. 14. The proposed mixer switched series-parallel core design and transconductance linearization using MGTR.
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
Auxiliary
RF+
M13
M9
Vgs
gm ′′
Master
121
Vth
Vgs-Vshift
Gate to source voltage, Vgs (V)
Fig. 15. Schematic illustration of gm cancellation using MGTR.
CMFB
MIXER CORE
VDD
BUFFER
M17 M23
M22
M18 Vconf
M20
On chip
M21
M19
RF+
C7
R3
C8
R4
M26 M27
Vref
M9
M31 M14
M10
M11
M 15 M 16
M7
M8
IF+-IF
M12
RFM5
M6
M25
LO+ M1
M3
M2
M24
M4 vbias
LOIDC On chip Fig. 16. Complete schematic of the proposed mixer.
dependent on device characteristics and can vary widely for different devices in the same process. The 1/f noise is inversely proportional to the transistor area, WL. In other words, to increase the sizes of the transconductance transistors NF should be decreased for 1/f noise.
DC_BLOCK Master Auxiliary
C2 L1
C1
M9
RF+
R1
4. Mixer implementation and measured results Fig. 16 shows a complete schematic of the proposed mixer. The mixer consists of five major parts: transconductance stages (M9–M12), switching stages (M1–M8), MGTR circuitry (M13–M16), CMFB circuitry (M17–M23), and output buffers (M24–M27). The input matching networks of RF and LO are shown in Fig. 17. The passive components metal-insulator-metal (MIM) capacitors (C1–C3), poly/diffusion resistor (R1), and spiral inductor (L1) are adopted for matching the network at the input RF stage to resonate over the entire frequency band. Furthermore, we use one spiral inductor (L2), one poly/diffusion resistor (R2), and three metal-insulator-metal (MIM) capacitors (C4–C6) to match the
M13 Rg
Rg
C3 Vgs-Vshift
Vgs DC_BLOCK C4 LO+
L2
C5
R2
Rg
M5
M6
M1
M2
C6 Vgs Fig. 17. The input matching networks of RF and LO.
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
VDD Vref
0
BUFFER
Measured RF return loss Simulated RF return loss
-5 CMFB
M17
-10 dB
M18 M26
Vconf
-15 -20
C7
R3
R4
C8
-25
M27
-30 M24
+ RF -
IF+-IF
0
M25
2
3
5 6 4 Frequency (GHz)
7
8
9
10
7
8
9
10
0
Rg + LO -
1
Measured RF return loss Simulated RF return loss
-5 vbias
-10 dB
Fig. 18. Simplified mixer schematic with load network.
-15 -20
DC PORT
-25 -30 0
2
1
3
4 5 6 Frequency (GHz)
RF PORT
LO PORT
Fig. 20. Measured RF and LO ports return loss.
9
IF PORT Fig. 19. Chip microphotograph.
input LO stage to resonate over the entire frequency band. The resistance Rg is added as a bias voltage resistance. Both RF and LO stage impedances have a value of 50 O. Fig. 18 shows the simplified mixer schematic consisting of a common-mode feedback (CMFB) circuitry [16] and a mixer core with two output buffer stages. Differential active PMOS loads instead of resistive loads are used here to increase the conversion gain without sacrificing the voltage swing headroom. The DC level at the mixer output is adjusted by a common-mode feedback (CMFB). The CMFB-loop is an amplifier comparing the reference voltage with the mixer output voltage and adjusts the DC current through the load resistors. The drain current of M21 is then adjusted and mirrored to the two PMOS connected in parallel with the load resistors. Transistors M19 through M23 serve as a CMFB circuit to set up the common-mode voltage. It is used to generate a stable dc level to the gates of M17–M18. With a high enough loop gain, Vref and Vcont will be about equal. The value of Vref is selected to optimize the linearity by allowing the maximum range of output voltage swing. The common-mode voltage level of the output nodes is designated to be about 0.75 V (Vref) by using a CMFB circuit. At a high frequency signal, C7 and C8 can be estimated to a short circuit. C7 and C8 can reject LO and RF signals at IF [10], and
Conversion Gain (dB)
8 7 6 5 RF at 3.4GHz (TT) RF at 5.0GHz (TT) RF at 6.8GHz (TT) RF at 7.3GHz (TT) RF at 8.4GHz (TT) RF at 9.5GHz (TT) RF at 10.0GHz (TT)
4 3 2 1 0 -40
-35
-30 -25 -20 RF Input power (dBm)
-15
-10
Fig. 21. Simulated conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm, TT represents the simulation results of typical-NMOS and typical-PMOS.
therefore reduce the noise figure. The RF signal is translated into the voltage signal by the load stage consisting of M17, M18, R3, and R4. The load stage provides output impedance through the resistive loads (that is, R3 and R4) and creates appropriate voltage swing headroom by the transistors (that is, M17 and M18). The buffer stage consisting of nMOS transistors (M24–M27) drive 50 O loads for measurement. The proposed UWB mixer is implemented in a 1P6M 0.18 mm CMOS process. Fig. 19 shows the microphotograph of the fabricated circuit with a chip area of 1.145 1.08 mm2 including the pad frames. The performance of the UWB mixer through on-wafer testing operates the RF signal with 30 dBm, and LO signal with 0 dBm. Both RF and LO frequency were swept from 3.4 to 6.8 GHz with a fixed IF
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
5
Conversion Gain (dB)
4 3 2 1
Conversion Gain (dB)
7 6 5 4 3 2
RF at 3.4GHz RF at 5.0GHz RF at 5.8GHz RF at 6.8GHz RF at 7.3GHz
1 0 -1 -40
-35
-20 -30 -25 RF Input power (dBm)
-15
-10
Fig. 24. Measured conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm.
10 9 8 7 6 5
Simulated 1.1V Simulated 1V Simulated 0.9V Simulated 0.8V
4 3 2
0
RF at 3.4GHz (SS) RF at 5.0GHz (SS) RF at 6.8GHz (SS) RF at 7.3GHz (SS) RF at 8.4GHz (SS) RF at 9.5GHz (SS) RF at 10.0GHz (SS)
-1 -2 -3 -4
1 0 -40
-5 -40
-30 -25 -20 RF Input power (dBm)
-35
-15
-10
Fig. 22. Simulated conversion gain versus RF power with the IF frequency 10 MHz, LO power is 0 dBm, SS represents the simulation results of slow-NMOS and slowPMOS.
9 8 Conversion Gain (dB)
8
Conversion Gain (dB)
frequencies of 10 MHz. The total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW. The RF and LO ports impedance matching are 50 O, respectively. Fig. 20 shows RF and LO ports return loss, from 3 to 11 GHz; the measured results are less than –9 dB. Fig. 21 shows the simulated TT stand for typical model conversion gain with respect to the RF power. As shown in this figure, the simulated conversion gain displayed a 3-dB variation across the 3.4–9.5 GHz input frequency. Fig. 22 shows the simulated SS stand for typical model conversion gain with respect to the RF power. Fig. 23. shows the simulated conversion gain versus RF frequency. Fig. 24 shows the measured conversion gain with respect to the RF power. As shown in this figure, the measured results of conversion gain display a 3-dB variation across the 3.4–6.8 GHz input frequency. Fig. 25 shows the simulated TT stand for typical model conversion gain versus supply voltage at 5 GHz. As shown in this figure, the main advantages of the SwGm mixer is that it can work even with a supply voltage lower than 1 V. Comparing Fig. 21 with Fig. 22, and with Fig. 24, the measured conversion gain was between TT and SS typical model. The IM3 was measured, using two Agilnet E8247C continuous wave (CW) generators and an Agilent E4407B spectrum analyzer, as shown in Fig. 26. Fig. 27 shows the measured fundamental output power and third-order intermodu-
123
7 6 5 4 3
pre simulated IF = 10MHz (TT) pre simulated IF = 50MHz (TT) post simulated IF = 10MHz (TT) pre simulated IF = 100MHz (TT) pre simulated IF = 150MHz (TT)
2 1 0 3
4
5
6
7
8
9
10
11
RF Frequency (GHz) Fig. 23. Simulated conversion gain versus RF frequency, RF power is 30 dBm, and LO power is 0 dBm.
-35
-30 -25 -20 RF Input power (dBm)
-15
-10
Fig. 25. Simulated conversion gain versus supply voltage, LO power is 0 dBm at 3.4 GHz.
lation (IM3) with respect to the RF input frequency spacing of 10 MHz, and the IIP3 is 2 dBm at 3.4 GHz. Fig. 28 shows the IIP3 is 3 dBm at 6.8 GHz. Fig. 29 shows the measured isolation of LO-toRF and LO-to-IF at LO of 0 power are 54 and 43 dB at 5 GHz, respectively. Fig. 30 shows the measured RF-to-IF at RF of 30 power is 34.2 dB at 5 GHz. The simulation DSB noise figure minimum is 11.4–12 dB from 3 to 6.8 GHz as shown in Fig. 31. Due to the parasitic effect in the layout, the minimum of the measurement is 13.9–14.4 dB from 3 to 6.8 GHz. This result was measured by using the Agilnet N8975A noise-figure analyzer, but it cannot be measured at frequencies below 10 MHz. Table 2 summarizes the measured results and compares them with the data from previous wideband mixer literatures. As shown in [17], it requires high power consumption and a large supply voltage of 4.9 V. As shown in [17–19,21], Gilber-cell (GmSw) technology high power gain is barely satisfied when the supply voltage is below 1 V. References [18,20–22] require large power LO signal. Reference [20] only has core mixer power consumption, excluding from output source-follower. The Gilber-cell (GmSw) and distributed mixers cannot achieve the specification when the supply voltage is below 1 V [17–21]. The bulk-pumped mixers [22,23] can achieve low power consumption, but require a large power LO signal. Moreover, compared with previously published literature, the proposed mixer consumed a relatively low dc power of 2.9 mW under the supply voltage of 1 V. The mixer achieved high
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J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
ESA - ESeries Spectrum Analyzer (Agilent E4407B)
IF Balun RF Signal Generator
IF +
IF -
RF +
Balun
Ba lu n
RF-
LO+
LO Signal Generator
LO-
Agilnet E8247C
(Agilent E8247C)
DC Power Supply (HP 4142B) Fig. 26. IIP3 measured setup illustrated.
20 Fundamental IMD3
10
-42 Port to port isolation (dB)
Output Power (dBm)
0 -10 -20 -30 -40 -50 -60 -70
IIP3
-80 -40
-35
-30
-25
-20 -15 -10 -5 Input Power (dBm)
0
5
-45 -48 -51 -54
10
-10
Fig. 27. Measured IIP3 at 3.4 GHz.
-9
-8
-7
-6 -5 -4 -3 Input LO Power (dBm)
-1
-2
0
Fig. 29. Measured isolation of LO to IF and LO to RF at 5 GHz.
-32
20 Fundamental IMD3
10
Port to port isolation (dB)
0 Output Power (dBm)
LO-IF LO-RF
-10 -20 -30 -40 -50 -60 -70 -80
-33 RF-IF -34
-35
IIP3
-90
-36
-40
-35
-30
-25
-20 -15 -10 -5 Input Power (dBm)
Fig. 28. Measured IIP3 at 6.8 GHz.
0
5
10
-30
-25
-20 -15 -10 Input RF Power (dBm)
Fig. 30. Measured Isolation of RF to IF at 5 GHz.
-5
0
J.-D. Chen / Microelectronics Journal 42 (2011) 113–126
125
22 Measured IF = 10Mhz Post Simulated IF = 4.125Mhz Pre Simulated IF = 4.125Mhz Pre Simulated IF = 10Mhz Pre Simulated IF = 100Mhz
21 20 Noise Figure (dB)
19 18 17 16 15 14 13 12 11 10 3
4
5
6 7 8 RF Frequency (GHz)
9
10
11
Fig. 31. Measured and simulated DSB noise versus RF frequency, LO power is 0 dBm, and RF power is 30 dBm.
Table 2 Performances of CMOS UWB Mixers. Ref.
Process CMOS (mm)
LO power (dBm)
Gain (dB)
Freq. (GHz)
IF (MHz)
IIP3 (dBm)
NF (dB)
Die area (mm2)
V supply
PDC (mW)
Feature
[17]
0.18
1
0.3–25
10
–
–
0.8 1.0
4.9
71
Gilber-cell+ buffer (GmSw)
[18] [19] [20]
0.13 0.18 0.18
5 2 9
9.5– 12.5 5–12 5.5 5.2–2.5
9–50 0.2–16 3–8.72
10 528 528
– 0.5 0.5 – 0.68 0.65 6.8–7.3 (DSB) 1.14 1.16
3.3 1.8 1.8
97 15 10.4n
Gilber-cell+ buffer (GmSw) Gilber-cell+ buffer (GmSw) Distributed
[21]
0.18
3
2–27
10
2
40
0.18
5
0.5–7.5
100
5.7
14.3–17.0 (SSB) 15
0.87 0.82
[22]
11.5– 13.5 5.7–4.3
– – 5 (5 GHz) 0
0.86 0.72
0.77
0.48
[23]
0.13
13
3 to 1 10–35
100
–
–
0.6 0.4
1.6
6
This work
0.18
0
7.2–4.3
10
2–3
13.9–14.4 (DSB)
1.145 1.08
1
2.9
Distributed+ Gilber-cell+ buffer (GmSw) Bulk-pumped Gilber-cell+ buffer (GmSw) Bulk-pumped Gilber-cell+ buffer (GmSw) Gilber-cell+ buffer (SwGm)
n
3.4–6.8
Only core mixer
Table 3 Device sizes of the proposed mixer. Device
Design values
Device
Design values
MN1–MN4 MN5–MN8 MN9–MN12 MN13–MN16 MP17–MP18 MN19–MN21 MP22–MP23 MN24–MN25 MN26–MN27 R1 R2
30/0.18 (W/L) 240/0.18 (W/L) 90/0.18 (W/L) 72/0.18 (W/L) 512/0.18 (W/L) 15/0.18 (W/L) 512/0.18 (W/L) 304/0.18 (W/L) 300/0.2 (W/L) 101.4 O 141.2 O
R3–R4 Rg C1 C2 C3 C4 C5 C6 C7–C8 L1 L2
1.2 kO 1.5 kO 7.74 pF 0.951 pF 4.90 pF 9.52 pF 0.042 pF 7.62 pF 1.9 pf 1.46 nH 1.32 nH
linearity using the MGTR topology under the low voltage. The device sizes of the mixer are shown in Table 3.
5. Conclusion A MGTR series-parallel Gilber-cell (SwGm) UWB mixer topology has been presented in the above results, which can operate at 1-V supply voltage in a 0.18-mm CMOS technology. In
the proposed topology, the narrowband mixer can be converted into a wideband mixer by the RLC matching method. The LO switched series-parallel system was applied to reduce the supply voltage and dc power consumption. The linearity can be improved by using MGTR topology. The main advantages of the mixer topology contain low dc power consumption, low supply voltage, high-linearity, and moderate power gain. The proposed mixer is suitable for UWB system applications.
Acknowledgment The author would like to thank the National Chip Implementation Center (CIC), Taiwan, for technical support. References [1] R. Harjani, J. Harvey, R. Sainati, Analog/RF physical layer issues for UWB systems, in: Proceedings of the 17th International Conference on VLSI Design, 2004, pp. 941–948. [2] A. Tsitouras, F. Plessas, Ultra wideband, low-power, 3–5.6 GHz, CMOS voltage-controlled oscillator, Microelectron. J. March (2009). [3] K. Zhang, S. Cheng, X. Zhou, W. Li, R. Liu, A wide band differentially switchtuned CMOS monolithic quadrature VCO with a low KVCO and high linearity, Microelectron. J. (2009).
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