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Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI
ARTICLE IN PRESS Microelectronics Journal 39 (2008) 1751–1760
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Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI Soodeh Aghli Moghaddam , Nasser Masoumi VLSI Research Group, School of ECE, College of Engineering, University of Tehran, Tehran, Iran
a r t i c l e in fo
abstract
Article history: Received 27 August 2007 Received in revised form 5 August 2008 Accepted 18 August 2008 Available online 17 October 2008
Crosstalk noise and delay uncertainty are two major problems in modern very large scale integration (VLSI) design. To overcome these difficulties, a new dielectric structure is proposed for integrated circuits, which is in contrast to the conventional Cu/low-K technology. Both structures are simulated employing a field solver and a time domain simulator. Using the new dielectric structure, near- and farend crosstalk noises are reduced 45.2% and 15% in the test dimensions, respectively. The proposed structure, called gradually low-K, exhibits negligible side-effects in terms of delay and power consumption. Therefore, it is shown that the gradually low-K structure is a relevant choice to overcome the crosstalk and delay uncertainty problems, especially in the global interconnects tier. & 2008 Elsevier Ltd. All rights reserved.
Keywords: Low-K technology Crosstalk noise reduction Delay uncertainty reduction Gradually low-K structure
1. Introduction Very large scale integration (VLSI) technology is improving at an incredible pace nowadays, but unfortunately encounters many complicated problems. Transistors and interconnects shrinking, interconnects length and aspect ratio augmentation, the number of metal layers increasing due to the huge number of transistors and large dimensions of dies, and higher switching frequencies have caused many problems. Some of them are considerable wire’s delay, crosstalk noise, congestion and complicated routing, and delay uncertainty [1]. Coupling and fringing capacitances play an important role in overall circuit delay, besides the wire’s self-capacitance, resistance and inductance. Versatile methods [1,2,4–15] in different levels have been proposed to overcome those problems such as the crosstalk noise: In technology level, optical interconnects [2], nanotube interconnects, 3D-VLSI, and Cu/low-K [3]; in system level, current mode transmission [4], wireless interconnection [5,6], differential mode transmission [7], and serial data bus; in circuit level, buffer insertion, resizing and balancing [8], noise identification and recovery [9], noise filtering [10], and internal switching reduction, and in physical design level, segregation of sensitive areas, shield insertion [11], noiseaware partitioning, floorplanning, placement and routing [12,13] are some of the current proposed solutions. Each method has some advantages and disadvantages. Manufacturing cost, industry opposition against to the change, die’s
Corresponding author.
E-mail address: [email protected] (S.A. Moghaddam). 0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.08.008
area penalty, and bad response at high frequencies reasonably impose us to choose a special method for each problem and trade off its advantages and disadvantages. Cu/low-K technology reduces resistance, coupling, fringing, and ground capacitances of wires; hence the delay of interconnects, especially of global types, decreases and chip performance improves [14]. The International Technology Roadmap for Semiconductors (ITRS) predicts the dielectric constant in VLSI chips will be o2.4 in year 2009 [3]. It is important to note that the delay improvement due to the low-K technology is greater than improvement for crosstalk. Interconnects’ high aspect ratio, low spacing, and high distance to the ground plate cause a large coupling capacitance versus ground one [1]. Additionally, Miller effect alters coupling capacitance measure from zero to twice of its primary value and intensifies delay uncertainty according to the wires relative current directions [15]. Capacitive coupling contributes more than half of the total interconnects delay [1]. Indeed in the technologies below 0.35 mm, coupling capacitance constitutes more than 50% of the wire total capacitance [16]. Thereby, delay uncertainty influences the critical path analysis and recognition and results in a large gaurdbanding overhead [1]. As a solution for crosstalk noise in the technology level, we have proposed a novel gradually low-K structure versus conventional low-K one that delay uncertainty and crosstalk noise of global interconnect tier are more tolerable in it. However, changing and adopting technology according to this method has its own special costs. Section 2 illustrates the new gradually low-K structure and compares it to the conventional low-K one. Then, the frequency
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domain simulation results of scattering parameter for the new structure and traditional low-K one through different geometrical and electrical parameters are presented in Section 3. Section 4 contains time domain simulation results and compares crosstalk near-end noise (NEN) and far-end noise (FEN) of two structures. Section 5 concludes the paper and the new structure opportunities and constraints.
2. Gradually low-K structure Cu/low-K technology offers several advantages such as lowering power consumption and delay of interconnect, as well as saving area due to removing the necessity of buffer insertion. Cu has a lower resistance and therefore, causes a lower loss and delay on wires, compared to Al. Moreover low-K dielectric reduces the coupling, fringing and ground capacitances of wires, so decreases their delay and saves power in the switching process. Cu/low-K technology is a conventional technology in today’s microelectronic industry. Fig. 1 shows a simple circuit model for the two lines of aggressor and victim wires. We have employed lumped RC model to illustrate the crosstalk phenomena. A rise or fall transition in the aggressor wire (input) causes a positive or negative spike in the victim wire (output). In the Fig. 1, CC, CGAgg, CGVic, CLoadAgg, and CLoadVic are the coupling, aggressor ground, victim ground and load capacitances, respectively. Also, RDrvAgg, RDrvVic, RLineAgg, and RLineVic are the resistances of aggressor driver, victim driver, and the line itself, respectively. After applying KCL and KVL rules to Fig. 1 circuit, Eq. (1) can be easily found. This equation exhibits an estimation expression of the crosstalk noise amplitude. In the Eq. (1), VXtalk and VIN represent the OUT and IN nodes voltage, respectively
victim lines, respectively. V Xtalk 1 ¼ 2ð1 þ ðC G þ C Load Þ=C C Þ V IN
(2)
Based on the above assumptions and Eq. (2), any change in the ground to coupling capacitance ratio, affects the output noise. Interconnects ground capacitance, CG, consists of the dielectric layer capacitance with the series substrate one. In the modern integrated circuits, large number of metallization layers, more than 10 ones, increases the wires distance to the ground plate. Therefore, the dielectric part and so the whole of wires ground capacitance decreases, especially for global interconnects. Furthermore, high aspect ratio and narrow width of interconnects considerably increase coupling capacitance, CC, with respect to the ground one, CG. These facts have led to the large augmentation of the CC/CG ratio in the modern VLSI technologies. On the other hand, input capacitance of transistors (CLoad) becomes lower by the technology node shrinking and makes the crosstalk noise worse. As a result, crosstalk reduction techniques in the physical level may be less efficient. Commonly, they try to reduce only the coupling capacitance by optimized spacing, without any change in the overall order of CC/CG, while the CC/CG ratio becomes larger with the trend of technology generation [3]. A big coupling capacitance can cause critical crosstalk noise, delay uncertainty, and signal integrity problem. Considering Eq. (2), the crosstalk noise decreases with increasing the ground capacitance of the victim line, for a determined coupling capacitance, CC. According to this fact and in contrast to the traditional low-K technology, we have proposed a novel low-K dielectric structure named gradually low-K structure [17,18]. This new structure increases the ground capacitance of the wires, decreases the coupling capacitance between wires, and so
V Xtalk 1 ¼ 1 þ ððRDrvAgg þ RLineAgg Þ=ðRDrvVic þ RLineVic ÞÞð1 þ ðC GAgg þ C LoadAgg Þ=C C Þ þ ððC GVic þ C LoadVic Þ=C C Þ V IN
(1)
For more simplicity, we can assume that the wires dimensions, materials, drivers and loads are the same. So Eq. (1) can be shortened to Eq. (2). In this equation, CG and CLoad are ground capacitance and load capacitance of both the aggressor and the
balances their values. Therefore, crosstalk noise and the delay uncertainty are reduced especially in the upper metal layers. Fig. 2 demonstrates a typical gradually low-K structure. Dielectric constant in different metal layers and inter-metal layers is dissimilar and decreases gradually from the bottom layer to the top one. This means that K4oK3oK2oK1. In this scheme, dielectric constant of each metal layer is equal to of its corresponding upper inter-metal layer. Moreover, it is lower than dielectric constant of its bottom inter-metal and metal layers. As such, the CC/CG, ratio
Fig. 1. A simple crosstalk circuit model for two aggressor and victim wires.
Fig. 2. A typical gradually low-K structure, with four different dielectric layers.
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decreases and the crosstalk noise is expected to reduce. It seems useful to remind that parallel plate capacitance is achieved from the Cpp ¼ e0 er A/d expression, that e0,er, A, and d are vacuum space permittivity, dielectric relative permittivity (dielectric constant), the parallel area of two plates, and the plates distance, respectively. It may seem that delay and crosstalk noise are increased in the local and intermediate interconnects and the advantages of gradually low-K structure is corrupted. Fortunately, delay, delay uncertainty, and crosstalk noise of the local and intermediate interconnects are tolerable, and their increment cannot affect total circuit performance and signal integrity, seriously. For the intermediate interconnects tier, dimensions and spacing are so that crosstalk phenomena is not serious in this tier, in contrast to the global one [19]. Another reason is the key difference between local and global interconnects. While the length of the former scales with technology node, for the latter the length is approximately constant. Global interconnect lengths are linked to the die size, which has remained nearly constant at approximately 1 cm2 for desktop microprocessors [2]. Therefore, the crosstalk noise is crucial in global interconnects because of their large lengths and high aspect ratio. Thereby, this structure offers overall satisfactory performance in terms of the crosstalk noise reduction. In the modern ICs design, delay uncertainty makes critical path detection more difficult than delay management. The newly proposed structure can suppress delay uncertainty caused by crosstalk phenomena. It is theoretically possible to optimize specification parameters of the gradually low-K structure, such as number of layers, layers thickness, dielectric constant variation slope, and its first and last values for each application. But some other factors like the manufacturing complexity and reliability issues of using different dielectrics on top of each other (mechanical weakness, problematic adhesion, and thermal stability of the low-K materials), and the matured current physical design tools and fabrication technologies guide us to employ the new structure with maximally 4–5 different dielectric layer, with respect to the local, intermediate, semi-global, and global interconnect tiers. Currently, several low-K materials are examined to employ as a new dialectic material in the metal layers and research in this field proceeds [20].
3. Frequency domain simulation results 3.1. Simulation assumptions and setups One of the useful and common ways to examine new proposed interconnect structures is simulating them using trusty field solvers and measure scattering parameters between their desired ports [21–25]. Scattering parameters show that in an n-port microwave network how much of input powers are reflected from or absorbed by the output ports. These parameters are completely frequency-dependent. Formally, scattering parameters can be defined for any collection of linear electronic components. Since operation frequency of integrated circuits has entered in giga hertz range and also global interconnect length has grown to millimeter values, high-speed VLSI interconnects treat like transmission lines and each interconnect conduct incident and reflected voltage and current waves. Therefore, using scattering parameters to show loss and crosstalk on interconnects becomes more common. For example, S21 relates out-power of port 2 to in-power of port 1 and represents the crosstalk intensity on the victim line. The greater S21 indicates the worse crosstalk noise.
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To study the new structure’s benefits and possible disadvantages, we simulated the gradually low-K structure and conventional low-K one in the frequency domain. A typical structure with five different dielectric layers and two parallel long wires on its top layer has been considered as the test structure. Fig. 3 indicates our simulated five layers structure and the input and output ports of 1and 2. The simulation parameters have been listed in Table 1. Relatively long wires have been considered for global interconnects tier. We have considered dielectric constant of traditional low-K structure equal to 2, in contrast to five different values of 3.9, 3.5, 3, 2.5, and 2 in the gradually low-K one. Simulation is done using the well-known CAD tool, IE3D. IE3D is a 3D field solver simulator and accurately calculates S-parameters of a given structure [25]. To achieve a higher accuracy, some advanced settings were done. The structure has been simulated for frequencies up to
Fig. 3. Simulated gradually low-K structure.
Table 1 Simulation parameters description and value Distribution
Simulation variables
Value
Wires length Wires width Wires thickness Wires distance Wire effective resistivity Wires height to ground plate Substrate thickness Dielectric layers thickness Dielectric layers number Substrate conductivity Dielectric layers conductivity Substrate dielectric constant Dielectric layers constant Dielectric constant in fix structure Simulation range of frequency Simulation range of wires length Simulation range of wires width Simulation range of wires thickness Simulation range of wires distance Simulation range of wires height to ground plate Simulation range of substrate thickness Simulation range of substrate conductivity Simulation range of substrate dielectric constant
L W T D
KSubstrate KDielectric steps Fix KDielectric
1000 mm 0.5 mm 1.1 mm 0.25 mm 2 mO cm 405.9 mm 400 mm 1.6 mm 5 5 S/m 0.0001 S/m 11.8 3.9, 3.5, 3, 2.5, 2 2 1–35 GHz 10–8000 mm 0.5–30 mm 1.1–8 mm 0.25–10 mm 401.6–405.9 mm
100–400 mm 0–10 S/m 8–20
r MH TSubstrate TLayer N
sSubstrate sDielectric
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70 GHz and the results are shown for the frequencies of 1–35 GHz range. Extra vertices have been also added on the lines edges to reach a fine edge meshing. Thickness of lines was considered in simulation, precisely. Moreover the extension for waves port (EFW), the most accurate scheme in IE3D which is not normalized to 50 O standard, and also intelligent fit option have been used. Through changing several parameters value, the scattering parameter between ports 1 and 2, S21, was extracted. In each case, difference between S21 of the traditional low-K (Fix) and the gradually low-K (Gra) structures was computed in the simulation frequency range. The computed variable is not constant across the simulation frequency range, so we have defined a new metric, S21 Improvement, across the whole range. This metric exhibits the maximum improvement of S21 in gradually low-K structure with respect to traditional one, in the simulation frequency range for the determined parameter value. Eq. (3) describes the S21 improvement definition. S21 Improvement ¼ MaxðS21 Fix S21 GraÞjparameter
Fig. 4. (a) S21 of the Fix and Gra test structure versus frequency and (b) S21 in the frequency range of 20–35 GHz.
(3)
Positive S21 Improvement means that Gra structure performs better that Fix in the case of crosstalk and has lower noise. Also, more S21 Improvement shows more effectiveness of Gra structure rather than Fix one. It is important to note that the frequency in which the S21 improvement occurs may be not equal for the different values of a parameter. This fact must be considered in the frequency results analysis. Also, it is possible that for a parameter in some frequencies Gra structure performs worse than Fix one, but its S21 Improvement still keeps positive.
Fig. 5. (a) S21 of the Fix and Gra test structure versus frequency for the different wires length, (b) S21 improvement versus wires length, and (c) S21 improvement versus wires length in the frequency of 1 GHz.
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3.2. Crosstalk improvement versus different parameters Fig. 4(a and b) shows S21 of the test Fix and Gra structures versus frequency. As it shows, approximately an improvement of 0.15 dB is gained and the expected reduction in crosstalk due to increasing the CG/CC ratio in the Gra structure is observed. Figs. 5–14 show S21 and S21 improvement variations versus the frequency and different parameters values. Some of these results
Fig. 8. S21 improvement versus wires height to the ground plate.
Fig. 9. S21 improvement versus wires width.
Fig. 6. (a) S21 of the Fix and Gra test structure versus frequency for the different wires thickness and (b) S21 improvement versus wires thickness.
Fig. 7. S21 of the Fix and Gra test structure versus frequency, for different wires height to the ground plate.
are not trivial and the reasons are not much clear. But the important and nice overall result is that in all cases, expect very large wires distance (space), and bottom metal layers, Gra structure performs better than Fix one. Fig. 5(a–c) illustrates, S21, S21 improvement, and S21 improvement in 1 GHz versus the frequency and wire length, respectively. As expected, Fig 5a shows that increasing the wires length leads to S21 and crosstalk noise increasing. According to Fig 5a details, S21 of shorter wires has an ascendant trend with the frequency augmentation, but for the longer wires there is a maximum point after which S21 starts to be reduced. Longer wires have a lower maximum point frequency. According to Fig. 5b, S21 improvement has a downtrend for shorter wires. But it ascends in the case of wires longer than 1000 mm. It has no uniform trend versus length and frequency. This is due to the inhomogeneous behavior of S21 versus frequency and wires length. In fact, materials behavior analysis in the high frequencies is a complicated process. At the first glance, it is expected that wires length growth increases influence of their inductance on the crosstalk noise and reduces the capacitances portion. But this expectation is not observed for nearly shorter wires. In Fig. 5b, S21 improvements of shorter wires have occurred in the low frequency near 1 GHz, but these points have occurred in high frequency like 14 and 35 GHz for longer wires. This result may reveal a good feature for long global wires. For having a more fair comparison, Fig. 5c illustrates S21 improvement variations in the nearly low frequency of 1 GHz. The
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Fig. 11. S21 improvement versus the substrate dielectric constant (k).
Fig. 12. S21 improvement versus the substrate thickness (substrate conductivity ¼ 5 S/m).
Fig. 10. (a) S21 of the Fix and Gra test structure versus frequency, for different wires distance; (b) S21 improvement versus the wires distance, and (c) operation of fringing and parallel plate parts in a typical coupling capacitance.
non-uniform and not-expected behavior of S21 improvement versus the wires length is observed in this diagram, too. Fig. 6a and b depict, S21 and S21 improvement variations versus frequency and wires thickness, respectively. As we expect with the wires thickness increasing, the CG/CC ratio decreases in both structures and so crosstalk increases (Fig. 6a). Also, the growth of CG due to Gra structure is constant for all values of thickness, while CC becomes larger for higher thicknesses, therefore the Gra structure influence decreases in the higher thicknesses. However, such high aspect ratio wires (up to 16) are not predicted for the future technologies and are unrealistic and impossible. Fig. 7 shows S21 versus frequency with variation in metal (wire) height to the ground plate. We changed location of the two
Fig. 13. S21 improvement versus the substrate thickness (substrate conductivity ¼ 0 S/m).
parallel wires from top dielectric layer to the bottom one. For frequencies nearly below 9 GHz, wires in the lower layers of Fix structure, observe less crosstalk noise, due to their constant CC and larger CG. However, in it the Gra structure, both of them increase in the lower layers and so the variation of crosstalk in the different layers is not considerably.
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Fig. 14. S21 improvement versus the substrate sigma (conductivity).
Moreover, Gra structure has a bad performance compared to Fix one and its S21 is more for Fix structure, as we expected. Gradually increasing of dielectric layers constant from top layer to bottom one, causes this phenomenon. Nevertheless, wire length in the bottom layers of integrated circuits is much lower than 1000 mm, and also their larger CG suppress high crosstalk noise. Therefore, crosstalk noise can be neglected in those layers because of its very low amplitude and this phenomenon does not have destructive effect on the signal integrity. The reason of changing this status nearly over 9 GHz frequency, and better performance of Gra structure with respect to Fix one is not clear for us. But it may be due to changing the material behavior in the very high frequencies, like what happens in the long wires simulation (Fig. 5). Fig. 8 introduces S21 improvement versus wires height to the ground plate, in the frequency of 1 GHz. To have a fair analysis, we show the S21 improvement of different height in the same and nearly low frequency. In Fig. 8, S21 improvement trend matches to the above description and decreases with the wires height to ground plate. Variation of S21 improvement versus wires width is illustrated in Fig. 9. An increment in wire width leads to the ground capacitance increasing. Since CC value does not change, so the crosstalk in both of the Fix and Gra structures decreases. The CG growth enhances the Gra structure effect and this structure reveals its advantages, better. However, for very wide wires the ground capacitance becomes very large and the change caused by Gra structure will has less influence with respect to the Fix structure CG value. Thereby, the S21 improvement has a maximum point versus wires thickness. Fig. 10a and b illustrate, the S21 and S21 improvement versus the frequency for different wires distances and the wires distance (space) in the frequency of 5 GHz, respectively. Except for 0.25 and 5 mm distances, for larger distances Gra structure show worse results rather than Fix one. More wires distance leads to more degradation in Gra structure performance. However, the simulation results imply that for further spaced wires at the frequencies higher than 10 GHz, this trend reverses so that the Gra structure performs better than the Fix one. It can be noted that the wires in our structure show a periodic behavior due to the distributed nature. Fig. 10b shows this trend in the frequency of 5 GHZ. The coupling capacitance between two parallel wires is composed of the parallel plate and the fringing capacitances, as seen in Fig. 10c. The increment of wires distance increases the fringing part of coupling capacitance and decrease the parallel plate part of it, so more electric filed lines pass from the lower dielectric layers with
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respect to what happens in the near parallel wires. Since the Gra structure increases dielectric constant of the lower layers, so this structure increases the fringing part of CC besides CG. Therefore, the crosstalk noise improvement degrades for larger wires distances. This improvement goes to negative values for the very large wires distances and Gra structure shows bad performance rather than Fix one. Nevertheless, the crosstalk amplitude between two far wires is very low. Also, this may be a good feature for increasing the integrated circuits density. It means that smaller wires distances have larger S21 improvement. S21 improvement variation versus substrate dielectric constant (kSubstrate) is illustrated in Fig. 11. As expected, when the dielectric constant of substrate decreases the substrate capacitance part of CG and so total of it decreases. Therefore, any change in dielectric layer capacitance part of CG and so increasing the ground capacitance of wires by the Gra structure has more effect on the S21 improvement. Fig. 11 nearly, verifies this expectation. Figs. 12 and 13 introduce the S21 improvement versus substrate thickness with two different conductivity, ssub ¼ 5 S/m (Fig. 12), and ssub ¼ 0 S/m (Fig. 13). When the substrate thickness decreases the substrate capacitance part of CG and so total of it increases. But, the substrate inductance is changed by the thickness, too. As the result, S21 improvement variations are not similar to the Fig. 11
Fig. 15. S41 comparison of original Fix structure and extracted RLC model, D ¼ 0.25 mm.
Fig. 16. S41 comparison of original Fix structure and extracted RLC model, D ¼ 5 mm.
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and some unknown behaviors are observed. It is noticeable that in all substrate thicknesses Gra structure keeps its better performance with respect to Fix one. Fig. 14 illustrates S21 improvement versus the substrate conductivity. Increment of the substrate conductivity decreases the substrate vertical resistance, so the substrate capacitance part of the CG seems to be short circuit. Therefore, any changing and
increasing of the dielectric layers capacitance part of CG has more effect on S21 improvement. This reasoning adapts with Fig. 14.
4. Time domain simulation results 4.1. Model extraction and simulation setting A couple of Fix and Gra structures with the same dimensions as the previous structures are constructed in the IE3D environment. Table 2 Extracted RLC model parameters values Structure Fix
Fig. 17. S41 comparison of original Gra structure and extracted RLC model, D ¼ 0.25 mm.
Gra
D Element
0.25 mm
5 mm
0.25 mm
5 mm
C1_1 (pF) L1_1 (nH) RL1_1 (O) C2_2 (pF) L2_2 (nH) RL2_2 (O) C1_2 (pF) RC1_2 (O) K1_2
0.0159174 1.23888 11.2596 0.0159166 1.23887 11.2596 0.107156 103789 0.87643
0.021814 1.22944 11.4034 0.021814 1.22944 11.4034 0.00965309 96718.2 0.582172
0.0202901 1.28703 11.6656 0.0202893 1.28702 11.6656 0.110058 136801 0.878999
0.0282909 1.27395 11.9419 0.0282912 1.27396 11.942 0.00974783 54076.3 0.581019
1.2
Fix NEN
1 800m
Gra NEN
Voltages (V)
600m 400m 200m 0 -200m -400m -600m -800m 100m Fig. 18. S41 comparison of original Gra structure and extracted RLC model, D ¼ 5 mm.
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 20. NEN of Fix and Gra structures, D ¼ 0.25 mm.
Fig. 19. Extracted RLC circuit model of aggressor and victim wires, with driver’s resistance and loads capacitance effects.
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400m
Fix FEN
350m
Gra FEN
300m 200m
Voltages (V)
Voltages (V)
250m 150m 100m 50m 0 -50m -100m -150m 100n
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 21. FEN of Fix and Gra structures, D ¼ 0.25 mm.
Gra FEN
Fix FEN
100n
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 23. FEN of Fix and Gra structures, D ¼ 5 mm.
the ground (C1_1 and C2_2) and coupling capacitance (C1_2) values in the Fix and Gra structure for the two cases of D ¼ 0.25 and 5 mm is interesting. In the former case, Gra structure decreases the C1_2/C1_1 ratio from 6.73 to 5.42 and reduces crosstalk, while in the later case that C1_1 is larger than C1_2 in the Fix structure, the new one increases C1_1/C1_2 ratio from 2.26 to only 2.9 and does not increase crosstalk, significantly.
800m 600m Gra NEN Voltages (V)
240m 220m 200m 180m 160m 140m 120m 100m 80m 60m 40m 20m 0 -20m -40m
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400m Fix NEN 200m
4.2. Time domain simulation results
0 -200m -400m 100n
100.2n
100.4n
100.6n
100.8n
Time (S) Fig. 22. NEN of Fix and Gra structures, D ¼ 5 mm.
In these new structures, D (the wires distances) is set to 0.25 and 5 mm, and moreover TSubstrate (the substrate thickness) is set to 100 mm. After filed simulation, RLC models of the Fix and Gra structures have been extracted under two circumstances (D ¼ 0.25 and 5 mm). Consequently, the extracted RLC models have been simulated in the IE3D, too, and their S-parameters have been compared to of the original structures for verification. Since for RLC extraction in IE3D, even number of ports is required, the crosstalk metric in these cases is S41, instead of S21. Figs. 15–18 illustrate the comparison of S41 in the original structures and extracted RLC models. Obviously, they are matched well, especially in the lower frequencies. Fig. 19 shows the extracted model circuit with driver resistance and load capacitance values. The driver resistance is 10 O for the switching transistor (the aggressor line driver) and 20 kO for the off transistor (the victim line driver). The switching frequency is 2 GHz, rise and fall time are set at 1 fs, load capacitances value is 0.5 pf and VDD is 1.5 V. The extracted RLC model has been simulated in HSPICE and the crosstalk NEN and FEN of victim wire for Fix and Gra structures have been achieved. Table 2 includes the extracted model parameters values. Comparison of
Figs. 20–23 show NEN and FEN of Fix and Gra structures for D ¼ 0.25 and 5 mm. For D ¼ 0.25 mm, Gra structure reduces NEN and FEN considerably (45.2% for NEN and 15% for FEN). However for D ¼ 5 mm, as mentioned in Section 3.2, the Gra structure causes a small increase in NEN and FEN because of larger fringing part of coupling capacitance. Nevertheless, since the crosstalk noise in larger wire distances is small enough to be neglected, it is not a considerable disadvantage. Figs. 22 and 23 show this fact. The increased FEN of victim line in the Gra structure for D ¼ 5 mm is lower that the decreased FEN for D ¼ 0.25 mm. Table 3 includes the results of the time domain simulations. According to the table, increasing of wires delay is negligible.
5. Conclusions The new dielectric structure for giga scale integration, called gradually low-K structure, has been proposed as a solution for crosstalk noise and delay uncertainty problems. According to the frequency domain simulations, the crosstalk measure, S21, has been reduced by 1 dB in the frequency range of 1–35 GHz for simulated structures with respect to the traditional low-K one. Moreover according to the time domain simulations, this structure reduces the crosstalk NEN and FEN, 45.2% and 15% in the test structure, respectively. The crosstalk reduction gained by the gradually low-K structure will improve for the very long and near wires. In contrary, it is decreased by increasing wires thickness and decreasing wires height to the ground plane. Wires width growth has considerable positive effect on the crosstalk reduction improvement. It has also shown an upper limit, while its trend becomes inverse for very wide wires.
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Table 3 Fix and Gra structures time domain simulation results
Fix D ¼ 0.25 mm Gra D ¼ 0.25 mm Fix D ¼ 5 mm Gra D ¼ 5 mm
Max (AGGOUT) (V)
AGG DELAY (ns)
MAX (VICIN) NEN (V)
TNEN (ns)
MAX (VICOUT) FEN (V)
TFEN (ns)
2.15 1.95 1.88 1.91
100.055100.036 ¼ 0.019 100.055100.036 ¼ 0.019 100.06100.036 ¼ 0.024 100.063100.036 ¼ 0.027
1.21 0.663 0.384 0.468
100.04 100.04 100.04 100.04
0.374 0.319 0.153 0.231
100.08 100.0122 100.14 100.13
Totally, the gradually low-K structure can be considered as a relevant choice for crosstalk and delay uncertainty reduction in global tiers of modern interconnects, besides the other solutions, and enhances the influence of many crosstalk reduction techniques in the physical design stage. Its manufacturing issues are near to the current low-K technology and seem possible to overcome. References [1] Puneet Gupta, Andrew B. Kahng, Wire swizzling to reduce delay uncertainty due to capacitive coupling, in: Proceedings of the 17th International Conference on VLSI Design (VLSID’04), 2004, pp. 431–436. [2] Mauro J. Kobrinsky, et al., On-chip optical interconnects, Intel Technol. J. 8 (02) (2004) 128–143. [3] International Technology Roadmap for Semiconductors, 2004 edition /http:// public.itrs.netS. [4] Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar, A low-swing differential signaling scheme for on-chip global interconnects, in: Proceedings of the 18th International Conference on VLSI Design, 3–7 January 2005, pp. 634–639. [5] A.B.M. Hun-ur Rashid, S. Watanabe, T. Kikkawa, Interference suppression of wireless interconnection in Si integrated antenna, in: Proceedings of the IEEE International Technology Conference, 2002, pp. 173–175. [6] A.B.M.H. Rashid, S. Watanabe, T. Kikkawa, Crosstalk isolation of monopole integrated antenna on Si for ULSI wireless interconnect, in: Proceedings of the IEEE International Technology Conference, 2003, pp. 156–158. [7] Hatırnaz, Y. Leblebici, modeling and implementation of twisted differential onchip interconnects for crosstalk noise reduction, in: Proceedings of the International Symposium on Circuits and Systems, ISCAS, vol. 5 (04), 2004, pp. 185–188. [8] Ming-Fu Hsiao, M. Marek Sadowska, Sao-Jie Chen, Minimizing coupling jitter by buffer resizing for coupled clock networks, in: Proceedings of the International Symposium on Circuits and Systems, ISCAS, vol. 5 (03), 2003, pp. 509–512. [9] Marcello Lajolo, Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 9 (6) (2001) 974–982. [10] P. Heydari, M. Pedram, Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits, in: 2001 IEEE, Proceedings of 2001 International Conference on Computer Design, ICCD, 23–26, 2001, pp. 104–109.
[11] Junmou Zhang, Eby.G. Friedman, Crosstalk noise model for shielded interconnects in VLSI-based circuits, in: Proceedings of IEEE International [Systems-on-Chip] SOC Conference, 17–20, 2003, pp. 243–244. [12] Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran, Floorplan-based crosstalk estimation for macrocell-based designs, in: Proceedings of 18th International Conference on VLSI Design, 3–7, 2005, pp. 463–468. [13] Jinjun Xiong, Lei. He, Extended global routing with RLC crosstalk constraints, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 13 (3) (2005) 319–329. [14] Corinne Cregut, Gilles Le Carval, Jean Chilo, Low-K dielectrics influence on crosstalk electromagnetic analysis and characterization, in: Proceedings of the IITC 98, 1998, pp. 59–61. [15] Yonghee Im, Kaushik Roy, O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 10 (3) (2002) 221–229. [16] Dennis Sylvester, Chenming Hu, Analytical modeling and characterization of deep-submicrometer interconnect, Proc. IEEE 89 (5) (2001). [17] S.Aghli Moghaddam, N. Masoumi, P. Jabedar, A. Shishegar, Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI ICM 2005, Islamabad, Pakistan, 2005, pp. 13–15. [18] Soodeh Aghli Moghaddam, Nasser Masoumi, Simulation of the novel gradually low-K dielectric structure for crosstalk reduction in VLSI and comparison with low-K technology, in: MWSCAS06. [19] International Technology Roadmap for Semiconductors, 2005 edition /http:// public.itrs.netS. [20] Krishnan Sundaresan, Nihar R. Mahapatra, An accurate energy and thermal model for global signal buses, in: Proceedings of the 18th International Conference on VLSI Design held jointly with Fourth International Conference on Embedded Systems Design (VLSID’05), IEEE. [21] R. Achar, M.S. Nakhla, Simulation of high-speed interconnects, Proc. IEEE 89 (5) (2001) 693–728. [22] Ihsan Erdin, Roni Khazaka, Michel S. Nakhla, Simulation of high-speed interconnects in a multilayered medium in the presence of incident field, IEEE Trans. Microwave Theory Tech. 46 (12) (1998) 2251–2257. [23] Rolf Sihlbom, Markus Dernevik, Mats Lindgren, J. Piotr Starski, Zonghe Lai (Member, IEEE), Johan Liu, High frequency measurements and simulations on wire-bonded modules on the sequential build-up boards (SBU’s), IEEE Trans. Components Packag Manuf Technol—Part A 21 (3) (1998) 478–491. [24] Y. Odate, T. Usami, K. Otsuka, T. Suga, A measurement and simulation study of transmission lines on microstrip and stacked-pair structure for high speed signals, in: Electronic Components and Technology Conference, IEEE, 2000. [25] IE3D Ver. 6, Zeland Software, Inc., 1992–1999.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI Soodeh Aghli Moghaddam , Nasser Masoumi VLSI Research Group, School of ECE, College of Engineering, University of Tehran, Tehran, Iran
a r t i c l e in fo
abstract
Article history: Received 27 August 2007 Received in revised form 5 August 2008 Accepted 18 August 2008 Available online 17 October 2008
Crosstalk noise and delay uncertainty are two major problems in modern very large scale integration (VLSI) design. To overcome these difficulties, a new dielectric structure is proposed for integrated circuits, which is in contrast to the conventional Cu/low-K technology. Both structures are simulated employing a field solver and a time domain simulator. Using the new dielectric structure, near- and farend crosstalk noises are reduced 45.2% and 15% in the test dimensions, respectively. The proposed structure, called gradually low-K, exhibits negligible side-effects in terms of delay and power consumption. Therefore, it is shown that the gradually low-K structure is a relevant choice to overcome the crosstalk and delay uncertainty problems, especially in the global interconnects tier. & 2008 Elsevier Ltd. All rights reserved.
Keywords: Low-K technology Crosstalk noise reduction Delay uncertainty reduction Gradually low-K structure
1. Introduction Very large scale integration (VLSI) technology is improving at an incredible pace nowadays, but unfortunately encounters many complicated problems. Transistors and interconnects shrinking, interconnects length and aspect ratio augmentation, the number of metal layers increasing due to the huge number of transistors and large dimensions of dies, and higher switching frequencies have caused many problems. Some of them are considerable wire’s delay, crosstalk noise, congestion and complicated routing, and delay uncertainty [1]. Coupling and fringing capacitances play an important role in overall circuit delay, besides the wire’s self-capacitance, resistance and inductance. Versatile methods [1,2,4–15] in different levels have been proposed to overcome those problems such as the crosstalk noise: In technology level, optical interconnects [2], nanotube interconnects, 3D-VLSI, and Cu/low-K [3]; in system level, current mode transmission [4], wireless interconnection [5,6], differential mode transmission [7], and serial data bus; in circuit level, buffer insertion, resizing and balancing [8], noise identification and recovery [9], noise filtering [10], and internal switching reduction, and in physical design level, segregation of sensitive areas, shield insertion [11], noiseaware partitioning, floorplanning, placement and routing [12,13] are some of the current proposed solutions. Each method has some advantages and disadvantages. Manufacturing cost, industry opposition against to the change, die’s
Corresponding author.
E-mail address: [email protected] (S.A. Moghaddam). 0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.08.008
area penalty, and bad response at high frequencies reasonably impose us to choose a special method for each problem and trade off its advantages and disadvantages. Cu/low-K technology reduces resistance, coupling, fringing, and ground capacitances of wires; hence the delay of interconnects, especially of global types, decreases and chip performance improves [14]. The International Technology Roadmap for Semiconductors (ITRS) predicts the dielectric constant in VLSI chips will be o2.4 in year 2009 [3]. It is important to note that the delay improvement due to the low-K technology is greater than improvement for crosstalk. Interconnects’ high aspect ratio, low spacing, and high distance to the ground plate cause a large coupling capacitance versus ground one [1]. Additionally, Miller effect alters coupling capacitance measure from zero to twice of its primary value and intensifies delay uncertainty according to the wires relative current directions [15]. Capacitive coupling contributes more than half of the total interconnects delay [1]. Indeed in the technologies below 0.35 mm, coupling capacitance constitutes more than 50% of the wire total capacitance [16]. Thereby, delay uncertainty influences the critical path analysis and recognition and results in a large gaurdbanding overhead [1]. As a solution for crosstalk noise in the technology level, we have proposed a novel gradually low-K structure versus conventional low-K one that delay uncertainty and crosstalk noise of global interconnect tier are more tolerable in it. However, changing and adopting technology according to this method has its own special costs. Section 2 illustrates the new gradually low-K structure and compares it to the conventional low-K one. Then, the frequency
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domain simulation results of scattering parameter for the new structure and traditional low-K one through different geometrical and electrical parameters are presented in Section 3. Section 4 contains time domain simulation results and compares crosstalk near-end noise (NEN) and far-end noise (FEN) of two structures. Section 5 concludes the paper and the new structure opportunities and constraints.
2. Gradually low-K structure Cu/low-K technology offers several advantages such as lowering power consumption and delay of interconnect, as well as saving area due to removing the necessity of buffer insertion. Cu has a lower resistance and therefore, causes a lower loss and delay on wires, compared to Al. Moreover low-K dielectric reduces the coupling, fringing and ground capacitances of wires, so decreases their delay and saves power in the switching process. Cu/low-K technology is a conventional technology in today’s microelectronic industry. Fig. 1 shows a simple circuit model for the two lines of aggressor and victim wires. We have employed lumped RC model to illustrate the crosstalk phenomena. A rise or fall transition in the aggressor wire (input) causes a positive or negative spike in the victim wire (output). In the Fig. 1, CC, CGAgg, CGVic, CLoadAgg, and CLoadVic are the coupling, aggressor ground, victim ground and load capacitances, respectively. Also, RDrvAgg, RDrvVic, RLineAgg, and RLineVic are the resistances of aggressor driver, victim driver, and the line itself, respectively. After applying KCL and KVL rules to Fig. 1 circuit, Eq. (1) can be easily found. This equation exhibits an estimation expression of the crosstalk noise amplitude. In the Eq. (1), VXtalk and VIN represent the OUT and IN nodes voltage, respectively
victim lines, respectively. V Xtalk 1 ¼ 2ð1 þ ðC G þ C Load Þ=C C Þ V IN
(2)
Based on the above assumptions and Eq. (2), any change in the ground to coupling capacitance ratio, affects the output noise. Interconnects ground capacitance, CG, consists of the dielectric layer capacitance with the series substrate one. In the modern integrated circuits, large number of metallization layers, more than 10 ones, increases the wires distance to the ground plate. Therefore, the dielectric part and so the whole of wires ground capacitance decreases, especially for global interconnects. Furthermore, high aspect ratio and narrow width of interconnects considerably increase coupling capacitance, CC, with respect to the ground one, CG. These facts have led to the large augmentation of the CC/CG ratio in the modern VLSI technologies. On the other hand, input capacitance of transistors (CLoad) becomes lower by the technology node shrinking and makes the crosstalk noise worse. As a result, crosstalk reduction techniques in the physical level may be less efficient. Commonly, they try to reduce only the coupling capacitance by optimized spacing, without any change in the overall order of CC/CG, while the CC/CG ratio becomes larger with the trend of technology generation [3]. A big coupling capacitance can cause critical crosstalk noise, delay uncertainty, and signal integrity problem. Considering Eq. (2), the crosstalk noise decreases with increasing the ground capacitance of the victim line, for a determined coupling capacitance, CC. According to this fact and in contrast to the traditional low-K technology, we have proposed a novel low-K dielectric structure named gradually low-K structure [17,18]. This new structure increases the ground capacitance of the wires, decreases the coupling capacitance between wires, and so
V Xtalk 1 ¼ 1 þ ððRDrvAgg þ RLineAgg Þ=ðRDrvVic þ RLineVic ÞÞð1 þ ðC GAgg þ C LoadAgg Þ=C C Þ þ ððC GVic þ C LoadVic Þ=C C Þ V IN
(1)
For more simplicity, we can assume that the wires dimensions, materials, drivers and loads are the same. So Eq. (1) can be shortened to Eq. (2). In this equation, CG and CLoad are ground capacitance and load capacitance of both the aggressor and the
balances their values. Therefore, crosstalk noise and the delay uncertainty are reduced especially in the upper metal layers. Fig. 2 demonstrates a typical gradually low-K structure. Dielectric constant in different metal layers and inter-metal layers is dissimilar and decreases gradually from the bottom layer to the top one. This means that K4oK3oK2oK1. In this scheme, dielectric constant of each metal layer is equal to of its corresponding upper inter-metal layer. Moreover, it is lower than dielectric constant of its bottom inter-metal and metal layers. As such, the CC/CG, ratio
Fig. 1. A simple crosstalk circuit model for two aggressor and victim wires.
Fig. 2. A typical gradually low-K structure, with four different dielectric layers.
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decreases and the crosstalk noise is expected to reduce. It seems useful to remind that parallel plate capacitance is achieved from the Cpp ¼ e0 er A/d expression, that e0,er, A, and d are vacuum space permittivity, dielectric relative permittivity (dielectric constant), the parallel area of two plates, and the plates distance, respectively. It may seem that delay and crosstalk noise are increased in the local and intermediate interconnects and the advantages of gradually low-K structure is corrupted. Fortunately, delay, delay uncertainty, and crosstalk noise of the local and intermediate interconnects are tolerable, and their increment cannot affect total circuit performance and signal integrity, seriously. For the intermediate interconnects tier, dimensions and spacing are so that crosstalk phenomena is not serious in this tier, in contrast to the global one [19]. Another reason is the key difference between local and global interconnects. While the length of the former scales with technology node, for the latter the length is approximately constant. Global interconnect lengths are linked to the die size, which has remained nearly constant at approximately 1 cm2 for desktop microprocessors [2]. Therefore, the crosstalk noise is crucial in global interconnects because of their large lengths and high aspect ratio. Thereby, this structure offers overall satisfactory performance in terms of the crosstalk noise reduction. In the modern ICs design, delay uncertainty makes critical path detection more difficult than delay management. The newly proposed structure can suppress delay uncertainty caused by crosstalk phenomena. It is theoretically possible to optimize specification parameters of the gradually low-K structure, such as number of layers, layers thickness, dielectric constant variation slope, and its first and last values for each application. But some other factors like the manufacturing complexity and reliability issues of using different dielectrics on top of each other (mechanical weakness, problematic adhesion, and thermal stability of the low-K materials), and the matured current physical design tools and fabrication technologies guide us to employ the new structure with maximally 4–5 different dielectric layer, with respect to the local, intermediate, semi-global, and global interconnect tiers. Currently, several low-K materials are examined to employ as a new dialectic material in the metal layers and research in this field proceeds [20].
3. Frequency domain simulation results 3.1. Simulation assumptions and setups One of the useful and common ways to examine new proposed interconnect structures is simulating them using trusty field solvers and measure scattering parameters between their desired ports [21–25]. Scattering parameters show that in an n-port microwave network how much of input powers are reflected from or absorbed by the output ports. These parameters are completely frequency-dependent. Formally, scattering parameters can be defined for any collection of linear electronic components. Since operation frequency of integrated circuits has entered in giga hertz range and also global interconnect length has grown to millimeter values, high-speed VLSI interconnects treat like transmission lines and each interconnect conduct incident and reflected voltage and current waves. Therefore, using scattering parameters to show loss and crosstalk on interconnects becomes more common. For example, S21 relates out-power of port 2 to in-power of port 1 and represents the crosstalk intensity on the victim line. The greater S21 indicates the worse crosstalk noise.
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To study the new structure’s benefits and possible disadvantages, we simulated the gradually low-K structure and conventional low-K one in the frequency domain. A typical structure with five different dielectric layers and two parallel long wires on its top layer has been considered as the test structure. Fig. 3 indicates our simulated five layers structure and the input and output ports of 1and 2. The simulation parameters have been listed in Table 1. Relatively long wires have been considered for global interconnects tier. We have considered dielectric constant of traditional low-K structure equal to 2, in contrast to five different values of 3.9, 3.5, 3, 2.5, and 2 in the gradually low-K one. Simulation is done using the well-known CAD tool, IE3D. IE3D is a 3D field solver simulator and accurately calculates S-parameters of a given structure [25]. To achieve a higher accuracy, some advanced settings were done. The structure has been simulated for frequencies up to
Fig. 3. Simulated gradually low-K structure.
Table 1 Simulation parameters description and value Distribution
Simulation variables
Value
Wires length Wires width Wires thickness Wires distance Wire effective resistivity Wires height to ground plate Substrate thickness Dielectric layers thickness Dielectric layers number Substrate conductivity Dielectric layers conductivity Substrate dielectric constant Dielectric layers constant Dielectric constant in fix structure Simulation range of frequency Simulation range of wires length Simulation range of wires width Simulation range of wires thickness Simulation range of wires distance Simulation range of wires height to ground plate Simulation range of substrate thickness Simulation range of substrate conductivity Simulation range of substrate dielectric constant
L W T D
KSubstrate KDielectric steps Fix KDielectric
1000 mm 0.5 mm 1.1 mm 0.25 mm 2 mO cm 405.9 mm 400 mm 1.6 mm 5 5 S/m 0.0001 S/m 11.8 3.9, 3.5, 3, 2.5, 2 2 1–35 GHz 10–8000 mm 0.5–30 mm 1.1–8 mm 0.25–10 mm 401.6–405.9 mm
100–400 mm 0–10 S/m 8–20
r MH TSubstrate TLayer N
sSubstrate sDielectric
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70 GHz and the results are shown for the frequencies of 1–35 GHz range. Extra vertices have been also added on the lines edges to reach a fine edge meshing. Thickness of lines was considered in simulation, precisely. Moreover the extension for waves port (EFW), the most accurate scheme in IE3D which is not normalized to 50 O standard, and also intelligent fit option have been used. Through changing several parameters value, the scattering parameter between ports 1 and 2, S21, was extracted. In each case, difference between S21 of the traditional low-K (Fix) and the gradually low-K (Gra) structures was computed in the simulation frequency range. The computed variable is not constant across the simulation frequency range, so we have defined a new metric, S21 Improvement, across the whole range. This metric exhibits the maximum improvement of S21 in gradually low-K structure with respect to traditional one, in the simulation frequency range for the determined parameter value. Eq. (3) describes the S21 improvement definition. S21 Improvement ¼ MaxðS21 Fix S21 GraÞjparameter
Fig. 4. (a) S21 of the Fix and Gra test structure versus frequency and (b) S21 in the frequency range of 20–35 GHz.
(3)
Positive S21 Improvement means that Gra structure performs better that Fix in the case of crosstalk and has lower noise. Also, more S21 Improvement shows more effectiveness of Gra structure rather than Fix one. It is important to note that the frequency in which the S21 improvement occurs may be not equal for the different values of a parameter. This fact must be considered in the frequency results analysis. Also, it is possible that for a parameter in some frequencies Gra structure performs worse than Fix one, but its S21 Improvement still keeps positive.
Fig. 5. (a) S21 of the Fix and Gra test structure versus frequency for the different wires length, (b) S21 improvement versus wires length, and (c) S21 improvement versus wires length in the frequency of 1 GHz.
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3.2. Crosstalk improvement versus different parameters Fig. 4(a and b) shows S21 of the test Fix and Gra structures versus frequency. As it shows, approximately an improvement of 0.15 dB is gained and the expected reduction in crosstalk due to increasing the CG/CC ratio in the Gra structure is observed. Figs. 5–14 show S21 and S21 improvement variations versus the frequency and different parameters values. Some of these results
Fig. 8. S21 improvement versus wires height to the ground plate.
Fig. 9. S21 improvement versus wires width.
Fig. 6. (a) S21 of the Fix and Gra test structure versus frequency for the different wires thickness and (b) S21 improvement versus wires thickness.
Fig. 7. S21 of the Fix and Gra test structure versus frequency, for different wires height to the ground plate.
are not trivial and the reasons are not much clear. But the important and nice overall result is that in all cases, expect very large wires distance (space), and bottom metal layers, Gra structure performs better than Fix one. Fig. 5(a–c) illustrates, S21, S21 improvement, and S21 improvement in 1 GHz versus the frequency and wire length, respectively. As expected, Fig 5a shows that increasing the wires length leads to S21 and crosstalk noise increasing. According to Fig 5a details, S21 of shorter wires has an ascendant trend with the frequency augmentation, but for the longer wires there is a maximum point after which S21 starts to be reduced. Longer wires have a lower maximum point frequency. According to Fig. 5b, S21 improvement has a downtrend for shorter wires. But it ascends in the case of wires longer than 1000 mm. It has no uniform trend versus length and frequency. This is due to the inhomogeneous behavior of S21 versus frequency and wires length. In fact, materials behavior analysis in the high frequencies is a complicated process. At the first glance, it is expected that wires length growth increases influence of their inductance on the crosstalk noise and reduces the capacitances portion. But this expectation is not observed for nearly shorter wires. In Fig. 5b, S21 improvements of shorter wires have occurred in the low frequency near 1 GHz, but these points have occurred in high frequency like 14 and 35 GHz for longer wires. This result may reveal a good feature for long global wires. For having a more fair comparison, Fig. 5c illustrates S21 improvement variations in the nearly low frequency of 1 GHz. The
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Fig. 11. S21 improvement versus the substrate dielectric constant (k).
Fig. 12. S21 improvement versus the substrate thickness (substrate conductivity ¼ 5 S/m).
Fig. 10. (a) S21 of the Fix and Gra test structure versus frequency, for different wires distance; (b) S21 improvement versus the wires distance, and (c) operation of fringing and parallel plate parts in a typical coupling capacitance.
non-uniform and not-expected behavior of S21 improvement versus the wires length is observed in this diagram, too. Fig. 6a and b depict, S21 and S21 improvement variations versus frequency and wires thickness, respectively. As we expect with the wires thickness increasing, the CG/CC ratio decreases in both structures and so crosstalk increases (Fig. 6a). Also, the growth of CG due to Gra structure is constant for all values of thickness, while CC becomes larger for higher thicknesses, therefore the Gra structure influence decreases in the higher thicknesses. However, such high aspect ratio wires (up to 16) are not predicted for the future technologies and are unrealistic and impossible. Fig. 7 shows S21 versus frequency with variation in metal (wire) height to the ground plate. We changed location of the two
Fig. 13. S21 improvement versus the substrate thickness (substrate conductivity ¼ 0 S/m).
parallel wires from top dielectric layer to the bottom one. For frequencies nearly below 9 GHz, wires in the lower layers of Fix structure, observe less crosstalk noise, due to their constant CC and larger CG. However, in it the Gra structure, both of them increase in the lower layers and so the variation of crosstalk in the different layers is not considerably.
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Fig. 14. S21 improvement versus the substrate sigma (conductivity).
Moreover, Gra structure has a bad performance compared to Fix one and its S21 is more for Fix structure, as we expected. Gradually increasing of dielectric layers constant from top layer to bottom one, causes this phenomenon. Nevertheless, wire length in the bottom layers of integrated circuits is much lower than 1000 mm, and also their larger CG suppress high crosstalk noise. Therefore, crosstalk noise can be neglected in those layers because of its very low amplitude and this phenomenon does not have destructive effect on the signal integrity. The reason of changing this status nearly over 9 GHz frequency, and better performance of Gra structure with respect to Fix one is not clear for us. But it may be due to changing the material behavior in the very high frequencies, like what happens in the long wires simulation (Fig. 5). Fig. 8 introduces S21 improvement versus wires height to the ground plate, in the frequency of 1 GHz. To have a fair analysis, we show the S21 improvement of different height in the same and nearly low frequency. In Fig. 8, S21 improvement trend matches to the above description and decreases with the wires height to ground plate. Variation of S21 improvement versus wires width is illustrated in Fig. 9. An increment in wire width leads to the ground capacitance increasing. Since CC value does not change, so the crosstalk in both of the Fix and Gra structures decreases. The CG growth enhances the Gra structure effect and this structure reveals its advantages, better. However, for very wide wires the ground capacitance becomes very large and the change caused by Gra structure will has less influence with respect to the Fix structure CG value. Thereby, the S21 improvement has a maximum point versus wires thickness. Fig. 10a and b illustrate, the S21 and S21 improvement versus the frequency for different wires distances and the wires distance (space) in the frequency of 5 GHz, respectively. Except for 0.25 and 5 mm distances, for larger distances Gra structure show worse results rather than Fix one. More wires distance leads to more degradation in Gra structure performance. However, the simulation results imply that for further spaced wires at the frequencies higher than 10 GHz, this trend reverses so that the Gra structure performs better than the Fix one. It can be noted that the wires in our structure show a periodic behavior due to the distributed nature. Fig. 10b shows this trend in the frequency of 5 GHZ. The coupling capacitance between two parallel wires is composed of the parallel plate and the fringing capacitances, as seen in Fig. 10c. The increment of wires distance increases the fringing part of coupling capacitance and decrease the parallel plate part of it, so more electric filed lines pass from the lower dielectric layers with
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respect to what happens in the near parallel wires. Since the Gra structure increases dielectric constant of the lower layers, so this structure increases the fringing part of CC besides CG. Therefore, the crosstalk noise improvement degrades for larger wires distances. This improvement goes to negative values for the very large wires distances and Gra structure shows bad performance rather than Fix one. Nevertheless, the crosstalk amplitude between two far wires is very low. Also, this may be a good feature for increasing the integrated circuits density. It means that smaller wires distances have larger S21 improvement. S21 improvement variation versus substrate dielectric constant (kSubstrate) is illustrated in Fig. 11. As expected, when the dielectric constant of substrate decreases the substrate capacitance part of CG and so total of it decreases. Therefore, any change in dielectric layer capacitance part of CG and so increasing the ground capacitance of wires by the Gra structure has more effect on the S21 improvement. Fig. 11 nearly, verifies this expectation. Figs. 12 and 13 introduce the S21 improvement versus substrate thickness with two different conductivity, ssub ¼ 5 S/m (Fig. 12), and ssub ¼ 0 S/m (Fig. 13). When the substrate thickness decreases the substrate capacitance part of CG and so total of it increases. But, the substrate inductance is changed by the thickness, too. As the result, S21 improvement variations are not similar to the Fig. 11
Fig. 15. S41 comparison of original Fix structure and extracted RLC model, D ¼ 0.25 mm.
Fig. 16. S41 comparison of original Fix structure and extracted RLC model, D ¼ 5 mm.
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and some unknown behaviors are observed. It is noticeable that in all substrate thicknesses Gra structure keeps its better performance with respect to Fix one. Fig. 14 illustrates S21 improvement versus the substrate conductivity. Increment of the substrate conductivity decreases the substrate vertical resistance, so the substrate capacitance part of the CG seems to be short circuit. Therefore, any changing and
increasing of the dielectric layers capacitance part of CG has more effect on S21 improvement. This reasoning adapts with Fig. 14.
4. Time domain simulation results 4.1. Model extraction and simulation setting A couple of Fix and Gra structures with the same dimensions as the previous structures are constructed in the IE3D environment. Table 2 Extracted RLC model parameters values Structure Fix
Fig. 17. S41 comparison of original Gra structure and extracted RLC model, D ¼ 0.25 mm.
Gra
D Element
0.25 mm
5 mm
0.25 mm
5 mm
C1_1 (pF) L1_1 (nH) RL1_1 (O) C2_2 (pF) L2_2 (nH) RL2_2 (O) C1_2 (pF) RC1_2 (O) K1_2
0.0159174 1.23888 11.2596 0.0159166 1.23887 11.2596 0.107156 103789 0.87643
0.021814 1.22944 11.4034 0.021814 1.22944 11.4034 0.00965309 96718.2 0.582172
0.0202901 1.28703 11.6656 0.0202893 1.28702 11.6656 0.110058 136801 0.878999
0.0282909 1.27395 11.9419 0.0282912 1.27396 11.942 0.00974783 54076.3 0.581019
1.2
Fix NEN
1 800m
Gra NEN
Voltages (V)
600m 400m 200m 0 -200m -400m -600m -800m 100m Fig. 18. S41 comparison of original Gra structure and extracted RLC model, D ¼ 5 mm.
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 20. NEN of Fix and Gra structures, D ¼ 0.25 mm.
Fig. 19. Extracted RLC circuit model of aggressor and victim wires, with driver’s resistance and loads capacitance effects.
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400m
Fix FEN
350m
Gra FEN
300m 200m
Voltages (V)
Voltages (V)
250m 150m 100m 50m 0 -50m -100m -150m 100n
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 21. FEN of Fix and Gra structures, D ¼ 0.25 mm.
Gra FEN
Fix FEN
100n
100.2n
100.4n 100.6n Time (S)
100.8n
Fig. 23. FEN of Fix and Gra structures, D ¼ 5 mm.
the ground (C1_1 and C2_2) and coupling capacitance (C1_2) values in the Fix and Gra structure for the two cases of D ¼ 0.25 and 5 mm is interesting. In the former case, Gra structure decreases the C1_2/C1_1 ratio from 6.73 to 5.42 and reduces crosstalk, while in the later case that C1_1 is larger than C1_2 in the Fix structure, the new one increases C1_1/C1_2 ratio from 2.26 to only 2.9 and does not increase crosstalk, significantly.
800m 600m Gra NEN Voltages (V)
240m 220m 200m 180m 160m 140m 120m 100m 80m 60m 40m 20m 0 -20m -40m
1759
400m Fix NEN 200m
4.2. Time domain simulation results
0 -200m -400m 100n
100.2n
100.4n
100.6n
100.8n
Time (S) Fig. 22. NEN of Fix and Gra structures, D ¼ 5 mm.
In these new structures, D (the wires distances) is set to 0.25 and 5 mm, and moreover TSubstrate (the substrate thickness) is set to 100 mm. After filed simulation, RLC models of the Fix and Gra structures have been extracted under two circumstances (D ¼ 0.25 and 5 mm). Consequently, the extracted RLC models have been simulated in the IE3D, too, and their S-parameters have been compared to of the original structures for verification. Since for RLC extraction in IE3D, even number of ports is required, the crosstalk metric in these cases is S41, instead of S21. Figs. 15–18 illustrate the comparison of S41 in the original structures and extracted RLC models. Obviously, they are matched well, especially in the lower frequencies. Fig. 19 shows the extracted model circuit with driver resistance and load capacitance values. The driver resistance is 10 O for the switching transistor (the aggressor line driver) and 20 kO for the off transistor (the victim line driver). The switching frequency is 2 GHz, rise and fall time are set at 1 fs, load capacitances value is 0.5 pf and VDD is 1.5 V. The extracted RLC model has been simulated in HSPICE and the crosstalk NEN and FEN of victim wire for Fix and Gra structures have been achieved. Table 2 includes the extracted model parameters values. Comparison of
Figs. 20–23 show NEN and FEN of Fix and Gra structures for D ¼ 0.25 and 5 mm. For D ¼ 0.25 mm, Gra structure reduces NEN and FEN considerably (45.2% for NEN and 15% for FEN). However for D ¼ 5 mm, as mentioned in Section 3.2, the Gra structure causes a small increase in NEN and FEN because of larger fringing part of coupling capacitance. Nevertheless, since the crosstalk noise in larger wire distances is small enough to be neglected, it is not a considerable disadvantage. Figs. 22 and 23 show this fact. The increased FEN of victim line in the Gra structure for D ¼ 5 mm is lower that the decreased FEN for D ¼ 0.25 mm. Table 3 includes the results of the time domain simulations. According to the table, increasing of wires delay is negligible.
5. Conclusions The new dielectric structure for giga scale integration, called gradually low-K structure, has been proposed as a solution for crosstalk noise and delay uncertainty problems. According to the frequency domain simulations, the crosstalk measure, S21, has been reduced by 1 dB in the frequency range of 1–35 GHz for simulated structures with respect to the traditional low-K one. Moreover according to the time domain simulations, this structure reduces the crosstalk NEN and FEN, 45.2% and 15% in the test structure, respectively. The crosstalk reduction gained by the gradually low-K structure will improve for the very long and near wires. In contrary, it is decreased by increasing wires thickness and decreasing wires height to the ground plane. Wires width growth has considerable positive effect on the crosstalk reduction improvement. It has also shown an upper limit, while its trend becomes inverse for very wide wires.
ARTICLE IN PRESS 1760
S.A. Moghaddam, N. Masoumi / Microelectronics Journal 39 (2008) 1751–1760
Table 3 Fix and Gra structures time domain simulation results
Fix D ¼ 0.25 mm Gra D ¼ 0.25 mm Fix D ¼ 5 mm Gra D ¼ 5 mm
Max (AGGOUT) (V)
AGG DELAY (ns)
MAX (VICIN) NEN (V)
TNEN (ns)
MAX (VICOUT) FEN (V)
TFEN (ns)
2.15 1.95 1.88 1.91
100.055100.036 ¼ 0.019 100.055100.036 ¼ 0.019 100.06100.036 ¼ 0.024 100.063100.036 ¼ 0.027
1.21 0.663 0.384 0.468
100.04 100.04 100.04 100.04
0.374 0.319 0.153 0.231
100.08 100.0122 100.14 100.13
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