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Analysis and validation of wavelet transform based DC fault detection in HVDC system
Accepted Manuscript Title: Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System Author: Yew Ming Yeap Nagesh Geddada Abhisek Ukil PII: DOI: Reference:
S1568-4946(17)30459-3 http://dx.doi.org/doi:10.1016/j.asoc.2017.07.039 ASOC 4367
To appear in:
Applied Soft Computing
Received date: Revised date: Accepted date:
18-1-2016 3-7-2017 18-7-2017
Please cite this article as: Yew Ming Yeap, Nagesh Geddada, Abhisek Ukil, Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System, (2017), http://dx.doi.org/10.1016/j.asoc.2017.07.039 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Yew Ming Yeapa , Nagesh Geddadaa , Abhisek Ukila
of Electrical and Electronic Engineering, Nanyang Technological University, SINGAPORE
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Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System
Abstract
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Fault detection plays an important role in both conventional AC and upcoming DC power systems. This paper aims to study the application of discrete wavelet transform (WT) for detecting the DC fault in the high voltage DC (HVDC) system. The methods of choosing the mother wavelet suited for DC fault is presented, based on degree of correlation to the fault pattern and the time delay. The wavelet analysis is performed on a multi-terminal HVDC system, built in PSCAD/EMTDC software. Its performance is judged for critical parameter like the fault location, resistance and distance. The analysis is further extended to validation using results from experiment, which is obtained from a lab-scale DC hardware setup. Load change, one of the transient disturbances in power system, is carried out to understand the effectiveness of the wavelet transform to differentiate it from the DC fault. The noise in the experimental result gives rise to non-zero wavelet coefficient during the steady-state. This can be improved by removing the unwanted noise using right filter while still retaining the faultinduced transient. The wavelet transform is compared with short-time Fourier transform to highlight the issue with window size and noise. Keywords: DC fault, wavelet transform, multi-terminal HVDC, modular multi-level converter, PSCAD/EMTDC, DC system experiment, time-frequency analysis, fault detection
1. Introduction
High voltage direct current system (HVDC) is one of the important technologies that have taken the conventional power system in a new direction. While a lot of research efforts are put into the design of controller and control strategy of the HVDC system, it is equally important to address the protection issue in the system so that the damage caused by the fault is brought down to minimum. I The work was supported by the Start-Up Grant (M4081547.040), Nanyang Technological University, Singapore. Email addresses: [email protected] (Yew Ming Yeap), [email protected] (Nagesh Geddada), [email protected] (Abhisek Ukil)
Preprint submitted to Applied Soft Computing
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The traditional high voltage AC circuit breaker (CB) takes advantage of current zero crossing which enables it to be tripped in a safe manner. Such phenomenon, however, is not seen in the DC current. The absence of current zero means that the mechanism of the breaker in the DC system should be completely different. Due to lack of such technology, most of the present HVDC systems are restricted to point-to-point connection, where the AC CB is adequate for protection. The interest was renewed when ABB [1] and Alstom [2] proposed the hybrid DC CB. It is arguably one of the key enabling technologies that will potentially pave the way for the deployment of HVDC system with increasing connections, towards a multi-terminal DC (MTDC) grid. Development in power electronics converter technology has been critical for the advancement of the HVDC system. In comparison with the current source converter (CSC), the voltage source converter (VSC) is relatively more vulnerable to the fault on the DC side due to low DC-side inductance. Rapidly increasing DC current can damage the devices if the fault is not treated immediately. ABB’s hybrid DC CB [3] is capable of isolating the fault within 5 ms, this poses a challenge to the design of protection algorithm to meet such a stringent requirement. In addition, as the HVDC system is moving towards the scale of multi-terminal, locating the faulted line has become another important aspect of the protection system. In recent times, DC fault detection methods have gained a significant research attention in the HVDC system. Traveling wave is well established methid in conventional AC power system for its effectiveness in locating the fault point. Its application on the HVDC system had been studied extensively [4]. This technique, however, requires high sampling rate for data collection in order to accurately capture the wave-front arrival time. Fault detection based on the DC current measurement was proposed in the works [5, 6], whereby the rate of change of DC current (di/dt) forms the basis of fault criterion. While it is simple and computationally efficient, it has difficulty determining the faulted section independently as the system becomes highly meshed. DC fault can be also detected by pattern recognition, in which the measured voltage is compared with already known signal and the degree of similarity is measured by Pearson correlation coefficient [7]. However, such method might lack generality. Zheng et al. [8] reported that DC fault transient in CSC-HVDC system resulted in generation of certain harmonics, which could be leveraged to form a fault basis. Due to different operating conditions between CSC and VSC, its application on the latter remains to be investigated. The wavelet transform (WT) can be regarded as one of suitable techniques for processing the non-stationary fault signals [9, 10]. This signal processing technique is capable of interpreting the signal in time and frequency domain. WT has also been applied to detect disturbance in conventional AC power system [11–16]. One of the benefits of using the WT is that it is able to discriminatingly identify the DC fault against non-concerned disturbances (AC fault and load change) [17]. Using the WT, the faulted line can be determined in a meshed network without the need of communication channel, hence substantially reducing the detection time [18]. Abu-Elanien [19] in their work showed 2
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that this technique is able to withstand the influence of fault location and fault resistance to certain extent. This paper presents a detailed analysis of the wavelet-based method for detecting and locating fault in DC system, with software and hardware validations. Protection strategy is not of major focus. Rather, this paper attempts to thoroughly evaluate the performance of the WT using real fault signals. The influences of fault location, resistance and distance in the modular multilevel converter-based (MMC) HVDC system, modeled in PSCAD/EMTDC, are studied. The inter-terminal communication is opted out, as the wavelet detection scheme only requires the DC current signal which is locally available in each terminal. The influences of fault resistance and distance are also validated, using the experimental results obtained from the point-to-point hardware DC system operating at lab-scale voltage level. This paper also presents how capable is the wavelet transform when it comes to differentiating DC fault from load change, which is carried out experimentally. The improvement of the smoothened experimental result using properly designed filter will be discussed. Lastly, the performance comparison between the wavelet transform and the short-time Fourier transform (STFT) will be presented. The remainder of the paper is structured in the following manner. In Section 2, the background of DC fault is presented, followed by brief introduction of the wavelet transform and selection of mother wavelet in Section 3. The simulation and experimental results are covered in Section 4 and 5, respectively. Finally, the conclusions are given in Section 5.
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2. DC fault in HVDC System
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This section briefly explains the DC fault analysis in the MMC-based HVDC system. The DC fault can be divided into following types: pole capacitor unbalance, pole-to-ground (PG) and pole-to-pole (PP) fault. DC cable is relatively more vulnerable to the PG fault caused by insulation breakdown than PP fault [10]. Due to direct exposure to air, the DC overhead line is prone to the occurrence of these two faults. PP fault has the potential to result in extremely destructive damage to the HVDC system. Therefore, it is always considered as the most representative DC fault in literatures [20], as well as in this paper. Modeling of MMC and two-level VSC are fundamentally same, in which the converter station can be represented as DC current source in the DC side. The combined submodular capacitance Ce is described in (1), under the balanced condition, and the derivation can be found in [21, 22]. Ce =
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The DC side equivalent circuit of single MMC is represented in Fig. 1, at the instant of PP fault occurrence. Icv is the total current injected to the DC side. The Ldc and Rdc are the π-model equivalent inductance and resistance of the positive and negative poles. The fault resistance is denoted by Rf . Immediately
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Figure 1: Equivalent circuit of MMC DC side during DC fault. (a) Stage 1: DC capacitor discharge stage, (b) Diode freewheeling stage
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as the fault current exceeds the threshold, the IGBTs in the submodule will be blocked. Then, the current flow switches to the freewheeling diodes, which is shown in Fig. 1(b). By this time, it is important to clear the fault fast enough before the current reaches beyond the I 2 t capacity of diodes. The fault analysis can be divided into three stages: 1) DC capacitor discharge stage, 2) diode freewheeling stage, 3) AC infeed stage. The discharge of capacitor (Icap ) dominates the fault current in the first few time-instant of fault. When the DC voltage drops to zero, the AC side will continue supplying current to the fault point [23, 24]. The fault analysis here only focuses on stage 1 and 2, as these periods are critical for wavelet transform to make fault decision and dispatch IGBT block signal, preferably within 2 ms. The circuit in Fig. 1(a) can be represented by (2). (2)
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d2 Idc Re dIdc 1 + + Idc = 0 dt2 Le dt Le Ce
where Re = 2(Rdc /2) + Rf and Le = 2(Ldc /2). The under-damped response is met on the condition Re2 < (Le /Ce )1/2 . Assuming that the PP fault happens at t0 with the initial conditions of Vdc (t0 ) = V0 and Idc (t0 ) = I0 , the solution of the second-order RLC differential equation is given as, " # V0 Le − δI0 −δt Idc (t) = e I0 cos(ωt) + sin(ωt) , (3) ω " # I0 δV − 0 C e Vdc (t) = e−δt V0 cos(ωt) + sin(ωt) . (4) ω where δ = Re /2Le and ω = (1/Le Ce − (Re /2Le )2 )1/2 . The DC voltage (Vdc ) reaches zero when the DC capacitor (Ce ) gets dis0 charged. Now, the fault current (Idc ) is freewheeling within the three-phase diodes as the corresponding IGBTs are already blocked, depicted in Fig. 1(b). The line inductor (Ldc ) disallows sudden change of current, therefore the initial 4
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0 current for this stage is Idc (t1 ) = Idc (t1 ) = I00 . The circuit is now reduced to a RL circuit, so the expression of the fault current is given as:
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3. Wavelet Transform
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3.1. Theory
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Wavelet transform (WT) is used for fault detection instead of Short Time Fourier Transform (STFT). While both signal processing techniques are able to analyze non-stationary signal in time and frequency domain, the window size of the STFT is fixed. A longer window yields good frequency resolution at the expense of time resolution, and vice versa. A convenient solution to this dilemma is the WT, as it automatically changes the window size in response to the dynamics of the signal. It is able to capture the high frequency abrupt change, which is specially needed for detecting the fault. The WT breaks up a signal into the shifted and the scaled versions of the original (or mother) wavelet, allowing for simultaneous time and frequency analysis. The continuous wavelet transform (CWT) is defined as the sum over all time of the signal multiplied by the scaled and shifted versions of the wavelet function. Z +∞ ∗ CW T (a, b) = x(t)ψa,b (t)dt. (8) −∞
t−b ). (9) a ψ(t) is the mother wavelet, the asterisk in (8) denotes a complex conjugate, and a, b ∈ R, a 6= 0 (R is the real continuous number system) are the scaling and the shifting parameters, respectively. The discrete wavelet transform (DWT) −m/2 in (10) is given by choosing a = a− b0 , t = kT in (8) and (9), 0 m/2, b = na0 where T = 1.0, and k, m, n ∈ Z, (Z is the set of positive integers). ∗ ψa,b (t) = |a|−1/2 ψ(
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DW T (m, n) = a0
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We apply the multiresolution signal decomposition (MSD) [25, 26] technique to decompose a given signal into detailed and smoothed versions. Let x[n] be a 5
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discrete-time signal, then the MSD technique decomposes the signal in the form of wavelet coefficient at scale 1 into C1 [n], the smoothed (time-domain view) and D1 [n], the detailed (frequency-domain view) coefficients. The decomposition process can be iterated, with successive approximations being decomposed in turn, so that the original signal is broken down into many lower resolution components. This is called the wavelet decomposition tree [25, 26], shown in 2. MSD technique can be realized with the cascaded quadrature mirror filter (QMF) banks [27, 28]. So, for example, using 4-scale decomposition, the original signal s can be represented as: x[n] = C4 [n] + D4 [n] + D3 [n] + D2 [n] + D1 [n].
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Figure 2: Multiresolution signal decomposition.
3.2. Wavelet Selection
The wavelet coefficient is the cross-correlation of the signal and the mother wavelet; the higher the wavelet coefficient, the closer the signal matches with the chosen mother wavelet. Thus, a suitable wavelet should be selected such that it presents closest match to the pattern of the fault signal. Ma et al. [29] presented a method to facilitate the wavelet selection by using the Pearson product-moment correlation coefficient, as represented in (12). Pn ¯ i − Y¯ ) (Xi − X)(Y r = qPi=1 (12) n ¯ 2 (Yi − Y¯ )2 (X − X) i i=1 where Xi and Yi are the data sets of the fault signal and the wavelet respectively, ¯ and Y¯ . their corresponding averages being X In this case, Xi is the fault signal as depicted in Fig. 3, while Yi corresponds to the chosen Daubechies mother wavelet. 6
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Figure 4: Correlation coefficient between fault signal and Daubechies wavelet of order 2-9. The correlation coefficients between the fault signal and the Daubechies mother wavelet of varying order (db2 − db9) are computed and depicted in Fig. 4. It is found that db3 provides the best match among these candidates for the given fault pattern. 3.3. Mother wavelet and time delay Besides having adequate sensitivity to the transient caused by the DC fault, it is equally important to choose the right mother wavelet that yields high-speed fault detection. Fig. 5 shows the performance of Haar, Daubechies and Coiflet mother wavelets for providing the maximum wavelet coefficient and corresponding time delay.
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Figure 5: Time delay introduced by different mother wavelets. sf is the time the DC fault-induced transient begins to appear. It is noticed that compact wavelets work well to localize high frequency components in the transient with minimum time delay. In this case, Haar and db2-3 are the ideal mother wavelets because they produce the maximum wavelet coefficients with no delay. For the Daubechies wavelet family, db5 begins to show delay by one sample. Coiflet wavelet is inappropriate for DC fault detection as far as speed is concerned. The analysis here agrees with the finding in Santoso’s work [30], which reported that db4 and db6 are suitable for fast transient in conventional AC system. 4. Performance evaluation of wavelet transform - simulation result Fig. 6 shows the MMC HVDC model consisting of four terminals (MMCi, i =1, 2, 3, 4) developed in PSCAD/EMTDC. Four strong AC systems (ACi ) are connected with ring and monopole DC network. The DC lines (Lij, i, j = 1, 2,
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Figure 6: 4-terminal MMC HVDC model.
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Table 1: System data
Values 600 MVA 50 Hz 10 100 1000 µF 50 mH 180 Hz 100 km 200 km
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Parameters Rated power AC frequency AC system short circuit ratio Number of submodules per arm Module capacitor Arm inductor Switching frequency Length L12, L13, L34, L24 Length L23
3, 4), consisting of positive and negative poles, are represented as single line in the figure. The MMC adopts the detailed equivalent modeling (DEM) [31], with MMC1 working as fixed DC voltage control and the rest as fixed active power control. Its corresponding functional control structure will not be elaborated here, the detail can be found in [21, 32]. The full system data is given in Table 1. The DC currents (Idcij, i, j = 1, 2, 3, 4) are measured at each terminal (MMCi ). The IGBTs will not be blocked in the simulation as the focus is to identify the signature associated with fault in the DC current signal. The signals are exported to MATLAB and post-processed with discrete wavelet transform algorithm to generate the wavelet coefficients. The fault location (df ) is the distance from the fault to the monitoring terminal. The fault simulated here is the PP fault, with the fault resistance denoted as Rf . The sampling rate (fs ) is selected based on the available frequency range offered by digital fault recorder [33]. The mother wavelets to be adopted is db3, since it has been shown in Section 3 that it presents the closest similarity with 9
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fault pattern. The application of wavelet transform on the fault identification in the multi-terminal system is evaluated by considering the three cases below:
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• To study the influence of DC fault location: PP fault on Lij (i, j = 1, 2, 3, 4), Rf = 0.01Ω, df = 50km, fs = 15360Hz, using db3.
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• To study the influence of DC fault resistance: PP fault on L12, 0.01 < Rf < 500Ω, df = 50km, fs = 15360Hz, using db3.
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Figure 7: Detailed wavelet coefficient for each DC line current in different PP fault location. a) L12, b) L13, c) L34, d) L24, e) L23.
4.1. Influence of DC fault location Fig. 7 shows the wavelet coefficient obtained from the PP fault simulated on the DC lines in the multi-terminal HVDC system. The PP fault is initiated by shorting the positive and the negative DC lines through a fault resistance. Therefore, only the wavelet coefficient for positive pole DC current is presented here. The wavelet coefficient remains low during the steady-state, approximating to zero. The occurrence of fault on a DC line is detected when the DC current of 10
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the faulted line generates a high wavelet coefficient abruptly. To illustrate, PP fault on L13 (see Fig. 7(b)) generates large overcurrent in fault current between MMC1 and MMC3, resulting in high wavelet coefficients for Idc13 and Idc31 . Similar pattern is observed in other cases. With the high wavelet coefficient obtained at 243th sample, the fault is detected with a time delay of 1.09 ms. Additionally, the wavelet transform allows the healthy terminals to recognize that the fault is outside their protection zone, since the wavelet coefficients of their currents remain consistently low. The discriminative nature of wavelet transform has been validated. It is a reliable method for each terminal to independently identify the fault by just monitoring the DC current.
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Figure 8: Effect of PP fault resistance on detailed wavelet coefficient for each DC line current.
4.2. Influence of DC fault resistance This subsection studies the robustness of the WT to detect the high resistance fault in a multi-terminal HVDC system. Fig. 8 shows the trend of the wavelet coefficients of DC currents as the fault resistance on L12 is increased from 0.01 Ω to 500 Ω. The wavelet coefficient appears to be constantly high for the PP fault resistance ranging from 0.01 Ω to 5 Ω. Beyond that, however, the value begins to show downward trend. This can be explained by the fact that fault induced transient has been dampened by large fault resistor. As a consequence, the wavelet coefficient decreases with increasing fault resistance. Nevertheless, the wavelet coefficient of fault current remains vastly above that of healthy DC current by large margin. 4.3. Influence of DC fault distance The fault-induced transient is the function of fault location. If a DC fault happens in close proximity to a terminal, the DC current of that terminal will experience bigger frequency change and higher magnitude. Fig. 9 shows the 11
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wavelet coefficients of Idc12 and Idc21 as the location of PP fault (df ) is adjusted from 15 km to 85 km away from MMC1 along L12. Fig. 9(a)&(b) illustrates the relationship between the change of DC current and fault location. The current magnitude decreases and the transient becomes dampened as the fault point increases. This phenomenon is reflected in their wavelet coefficients. For example, the fault at df =85km yields the wavelet coefficient about -0.2342 for Idc12 and -1.389 for Idc21 . Despite diminished sensitivity, the fault can be successfully detected for all distances evaluated. 5. Performance evaluation of wavelet transform - experimental result
Laboratory DC system experiment setup is developed to study DC fault with variation of fault parameters. The schematic block diagram of the setup is shown in Fig. 10 and various parameters, ratings are given in Table 2. Experimental studies are performed at input voltage of 85 V (line rms). Three phase, 30 kVA, (0-450) V, variable transformer was used to set the desired input voltage of 85 V. Converters (VSC1, VSC2 ) at the DC side are rated at 30 kVA, 415 V. The voltage and current quantities at power level are converted to signal level using hall effect voltage (± 500 V to ± 15 V) and current (± 10 A to ± 4 V) transducers. These signals are fed to the dSPACE 1103 controller through 12
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Laboratory Three phase Supply Side
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Table 2: Experiment Setup Parameters
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Parameters Supply voltage 3φ AC Protection Board 3φ Variable Transformer Converters (VSC1, VSC2) DC Capacitor DC Line Paramters DC MCB Interface Filter Parameters Linear Load Variable Power Resistor DC Solid State Relay
Values 3φ, 85 Vrms , 50 Hz 40 A, B Type, TP MCB with Shunt trip 30 kV A, (0-415) V 30 kV A, 400 V Cdc = 2350 µF , Ld = 1.5 mH,Rd = 0.03 Ω C60H-DC, C 4 A Rf = 0.1 Ω, Lf = 10 mH Rl = 20 Ω 5000 W , (1-16) Ω D2D40, 200 V , 40 A
analog to digital channels (ADCH) ports. The control algorithm is developed in MATLAB/Similink and converted for the dSPACE hardware interface by
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the means of Real Time Interface (RTI) toolbox. The pulse-width modulation (PWM) gating pulses generated by the controller are fetched to the VSCs for switching.
Figure 11: (a)Experimental result for 2 Ω DC fault; (b)Wavelet coefficients for Idc12 and Idc21 .
Direct short-circuit across the DC line is not viable as the large fault current could trigger the tripping of main circuit breaker in the laboratory. In order to limit the magnitude of the fault current, a power resistor is inserted between upper and bottom DC line and the connection is controlled by a DC solid-state relay. During the startup of experiment, the relay remains open. When the system has achieved steady-state, the relay will be closed to electrically establish a connection across DC line via power resistor. The value of the resistance is adjustable from 1 Ω to 16 Ω. Fig. 11 shows the measurements of Iac1 , Vdc1 , Idc12 and Idc21 , in that or14
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der on LeCroy Wavesurfer 3024 oscilloscope, for 2 Ω DC fault. The sampling frequency used in the measurement is 10 kHz. The signals of interest here are Idc12 and Idc21 . The segment in dashed box is zoomed in to better visualize the fault-induced transient. The corresponding wavelet analysis using db3 is presented in the same figure. One can immediately notice that the steady state DC currents essentially do not yield zero wavelet coefficient as seen in the simulation results. The value falls between [w1,w2 ], marked by the dashed line. For now we take [w1,w2 ] as threshold, it will be discussed in subsection later how removing the noise in the signal can reduce the steady state wavelet coefficient. As expected, abrupt increase of current caused by the DC fault registers high wavelet coefficients for both currents. The fault inception time (3s) is translated to 1877th sample at 4th level of decomposition. The highest wavelet coefficient is obtained by one sample delay. Even with the delay introduced by filtering, the detection time would still be reasonably short.
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5.1. Influence of DC fault resistance
Figure 12: Wavelet coefficient for DC fault of varying fault resistance (a) 4 Ω; (b) 6 Ω; (c) 8 Ω; (d) 10 Ω; (e) 12 Ω; (f) 14 Ω. Similar to the Section 4.2, repeated experiments are carried out to evaluate the performance of wavelet transform for different fault resistance, ranging from 4 Ω to 14 Ω. Fig. 12 depicts the result of wavelet analysis on the DC currents (Idc12 & Idc21 ). 15
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The faults are detected for all fault resistances evaluated. The highest wavelet coefficient is observed around sample number 1878 (equivalent to 3.0016 s). Despite the presence of noise in the signal, the wavelet coefficients are kept within the presumed threshold, marked by the dashed line in the figures, during steady-state. The wavelet coefficient shows downward trend when increasing the fault resistance. Nevertheless, a reasonably big margin between the threshold and the wavelet coefficient still justifies the effectiveness of the WT in detecting the DC fault.
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5.2. Influence of DC line length
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Figure 13: DC line represented by RL circuit in experiment and different line length to be investigated.
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Similar to the Section 4.3, our interest is to study the effect of fault distance on the WT at experimental level. Besides the fault location, the frequency content of the transient is also a function of the DC line length. Three tests with different combination of inductance representing different fault location and DC line length are carried out, as shown in Fig. 13. The DC currents are analyzed with the WT and the result is shown in Fig. 14. The WT successfully detects the DC fault with the wavelet coefficient exceeding the threshold by large margin. One can observe that the terminal closer to the fault has current yielding the higher wavelet coefficient than its counterpart. For example, in Test 3, smaller L2 and L4 implicates the fault to be closer to the VSC2, and the fault at this location results in higher wavelet coefficient for Idc21 compared to Idc12 . Nevertheless, the two terminals are able to recognize the occurrence of DC fault as their maximum wavelet coefficients are consistently higher than threshold for all fault locations evaluated.
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Figure 14: Wavelet coefficient for DC fault of varying fault location (a) Test 1; (b) Test 2; (c) Test 3. 5.3. Influence of other type of power system disturbance
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Figure 15: Experimental result and wavelet analysis for (a) DC fault; (b) Load change.
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Load change in power system results in current increase that could be mistaken for DC fault. This subsection aims to study the feasibility of the WT in differentiating between DC fault and load change. To reproduce this phenomenon at experimental level, the resistive load at receiving end is reduced abruptly such that it generates a transient that reaches the same peak as faultinduced transient. The results from the experiment and the corresponding wavelet coefficients are shown in Fig. 15. As expected, the Idc12 in DC fault produces high wavelet coefficient. Although the load change causes transient in the DC current, its wavelet coefficient appears to increase not very much, barely crossing the presumed threshold. Thus, it is now clear that the DC fault can be differentiated from the load change using the WT.
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5.4. Influence of signal noise
Figure 16: (a) Raw and denoised signal for DC fault at 14 Ω; (b) Wavelet coefficient for denoised signal.
The signal measured directly from the experiment contains the noise amounting to 11.421 dB signal-to-noise ratio (SNR). The noise gives rise to non-zero wavelet coefficient during steady state. However, the wavelet coefficient appears to stay within the presumed threshold in all the studies so far. This subsection investigates on filtering the noise. The Idc12 for DC fault at 14 Ω is smoothened with bandstop filter so as to retain the fault-induced transient which is of high frequency and critically needed 18
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5.5. Comparison with short-time Fourier transform method
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for detection. The denoised signal now has 27.658 dB SNR during steady-state. Fig. 16 depicts the difference between raw and denoised signal. When analyzed with the WT, it is noticed that the steady-state wavelet coefficient has decreased substantially (see Fig. 16(b)), compared to that in Fig. 12(f). Furthermore, the maximum wavelet coefficient does not deviate much as a result of filtering, proving that the fault transient in the denoised signal is still preserved. Hence, an appropriate filtering is highly recommended if one wants to keep the steady-state wavelet coefficient as low as possible.
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Figure 17: Frequency spectrum of experimental fault current for window length (a) 16, (b) 32 and (c) 64. Zero-crossing frequency bin is marked by dash line.
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The problem with choosing the window size for STFT has been discussed in Section 3. For the purpose of fast fault detection, small window is preferable at the expense of frequency resolution. The STFT analysis of high frequency components in transient signals was reported in [34]. During steady-state, the frequency spectrum of constant DC current should resemble a sinc function, with the main-lobe concentrated at 0 Hz, with side-lobes uniformly distributed. A key feature in the frequency spectrum is the zero-crossing frequency bin. Considering n as window size in term of sample number, the zero-crossing frequency bin appears at 2fs /n, 3fs /n, 4fs /n and so on. When the DC fault happens, the high-frequency transient will have its signal energy leak into other frequencies, causing visible distortion across the side-lobes. Based on this phenomenon, the fault can be detected by tracking the magnitude of zero-crossing frequency bin, which will increase under the fault condition. The frequency spectra of experimental fault current (Idc12 ) for 16, 32 and 64-sample window lengths using Hanning window are shown in Fig. 17. 1. 16-sample: The first zero-crossing frequency bin for this window is 1250 Hz. It can be seen that the side-lobes has already experienced slight distortion caused by signal noise even before the fault occurrence. The zero-crossing frequency bin increases above 0 dB (threshold) at 0.8 ms after the fault inception. At which time, the fault is successfully detected.
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2. 32-sample: The influence of noise is comparatively less significant for this window size, given that the side-lobes retain equiripple-like pattern during pre-fault. The first zero-crossing frequency bin (625 Hz) exceeds the threshold with a time delay of 1.6 ms. 3. 64-sample: Similar to 16-sample window, the side-lobes are heavily distorted by the noise during pre-fault. The fault is detected when the first zero-crossing frequency bin (312.5 Hz) increases above threshold after 3.2 ms.
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It is observed that the detection time is very much dependent on the window size. 16-sample window provides the fastest detection. However, the signal noise can cause significant distortion making the tracking of frequency difficult. The influence of noise is also observable in 64-sample window while 32-sample window is minimally affected. The STFT is met with the difficulty of choosing the window size. The wavelet transform, on the other hand, can adjust the window size automatically to suit the fault signal. In addition, as part of the process of cascaded filtering, the wavelet transform is able to preserve the critical signal while eliminating noise, but this cannot be done by the STFT. 6. Conclusion
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The application of the wavelet transform to detect and identify the DC fault in HVDC system has been analyzed and validated using simulation and experimental results. db3 is adopted in the wavelet analysis as it presents the closest match to the fault pattern and is able to detect fault with minimal delay. The simulation result shows that the wavelet transform is able to independently detect the faulted line in a 4-terminal HVDC system, only using the wavelet coefficient for the DC line current at each terminal as criterion. The detection time is approximately 1 ms. The value of the wavelet coefficient decreases as the fault resistance and the fault distance are increased, however it is still well above the threshold by large margin. From the experimental results, it can be inferred that the wavelet transform also presents reasonable robustness to the influence of fault resistance and distance. It is not sensitive to the transient caused by load change, allowing to classify the DC fault from other types of disturbances. The inherent noise in the experimental result yields a non-zero wavelet coefficient, thus the threshold needs to be set above that so as to avoid wrong detection. The steady-state wavelet coefficient can be vastly reduced by smoothening the raw signal. The filter has to be properly designed so that only the unwanted noise is removed while the fault-induced transient, which is of high frequency, is still preserved. Compared to the short-time Fourier transform (STFT), the wavelet transform provides better flexibility when it comes to selecting window size and tolerance against noise.
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[1] M. Callavik, A. Blomberg, J. H¨afner, B. Jacobson, The hybrid hvdc breaker, ABB Grid Systems Technical Paper.
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[9] R. Keswani, Identification of fault in hvdc converters using wavelet based multi-resolution analysis, in: 2008 First International Conference on Emerging Trends in Engineering and Technology, 2008, pp. 954–959. doi:10.1109/ICETET.2008.150.
[10] S. Niaki, H. Karegar, M. G. Monfared, A novel fault detection method for vsc-hvdc transmission system of offshore wind farm, International Journal of Electrical Power & Energy Systems 73 (2015) 475 – 483. [11] H. Fathabadi, Two novel proposed discrete wavelet transform and filter based approaches for short-circuit faults detection in power transmission lines, Applied Soft Computing 36 (2015) 375 – 382. [12] M. Jamil, A. Kalam, A. Ansari, M. Rizwan, Generalized neural network and wavelet transform based approach for fault location estimation of a transmission line, Applied Soft Computing 19 (2014) 322 – 332. [13] M. Suganyadevi, C. Babulal, Support vector regression model for the prediction of loadability margin of a power system, Applied Soft Computing 24 (2014) 304 – 315.
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[17] Y. Yeap, A. Ukil, Wavelet based fault analysis in hvdc system, in: IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 2472–2478.
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[21] S. Liu, Z. Xu, W. Hua, G. Tang, Y. Xue, Electromechanical transient modeling of modular multilevel converter based multi-terminal hvdc systems, IEEE Transactions on Power Systems 29 (1) (2014) 72–83. [22] J. Peralta, H. Saad, S. Denneti`ere, J. Mahseredjian, S. Nguefeu, Detailed and averaged models for a 401-level mmc hvdc system, IEEE Transactions on Power Delivery 27 (3) (2012) 1501–1508. [23] M. Bucher, C. Franck, Contribution of fault current sources in multiterminal hvdc cable networks, IEEE Transactions on Power Delivery 28 (3) (2013) 1796–1803. [24] M. Bucher, C. Franck, Analysis of transient fault currents in multi-terminal hvdc networks during pole-to-ground faults, in: Proc. International Conference on Power Systems Transients (IPST), Vancouver, Canada, 2013. [25] S. Mallat, A theory for multiresolution signal decomposition: the wavelet representation, IEEE Transactions on Pattern Analysis and Machine Intelligence 11 (7) (1989) 674–693. [26] S. Mallat, A wavelet tour of signal processing, Academic press, 1999. 22
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[27] A. Ukil, R. Zivanovic, Automated analysis of power systems disturbance records: Smart grid big data perspective, in: 2014 IEEE Innovative Smart Grid Technologies - Asia (ISGT ASIA), 2014, pp. 126–131.
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[30] S. Santoso, E. Powers, W. Grady, P. Hofmann, Power quality assessment via wavelet transform analysis, IEEE Transactions on Power Delivery 11 (2) (1996) 924–930.
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[31] U. N. Gnanarathna, A. M. Gole, R. P. Jayasinghe, Efficient modeling of modular multilevel hvdc converters (mmc) on electromagnetic transient simulation programs, IEEE Transactions on Power Delivery 26 (1) (2011) 316–324.
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[32] J. Beerten, S. Cole, R. Belmans, Modeling of multi-terminal vsc hvdc systems with distributed dc voltage control, IEEE Transactions on Power Systems 29 (1) (2014) 34–42.
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[33] A. Ukil, B. Deck, V. Shah, Current-only directional overcurrent protection for distribution automation: Challenges and solutions, IEEE Transactions on Smart Grid 3 (4) (2012) 1687–1694.
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[34] Y. M. Yeap, A. Ukil, N. Geddada, Stft analysis of high frequency components in transient signals in multi-terminal hvdc system, in: IECON 2016 42nd Annual Conference of the IEEE Industrial Electronics Society, 2016, pp. 4008–4013.
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Paper: Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System
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Authors: Yew Ming Yeap, Nagesh Geddada, Abhisek Ukil
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Highlights
High voltage direct current system (HVDC) is one of the important power transmission
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technologies.
Protection of HVDC system is a must for safe and reliable power transfer, but it is not
Protection of the DC system is not as mature as AC system due to lack of devices and
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logic.
Simulation of multi-terminal HVDC system with DC fault are performed using the
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PSCAD/EMTDC.
Wavelet transform based fast detection of fault in HVDC system is described in details.
Lab-scale DC transmission setup is made, and experimental results are presented to
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substantiate the wavelet transform based method.
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S1568-4946(17)30459-3 http://dx.doi.org/doi:10.1016/j.asoc.2017.07.039 ASOC 4367
To appear in:
Applied Soft Computing
Received date: Revised date: Accepted date:
18-1-2016 3-7-2017 18-7-2017
Please cite this article as: Yew Ming Yeap, Nagesh Geddada, Abhisek Ukil, Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System, (2017), http://dx.doi.org/10.1016/j.asoc.2017.07.039 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Yew Ming Yeapa , Nagesh Geddadaa , Abhisek Ukila
of Electrical and Electronic Engineering, Nanyang Technological University, SINGAPORE
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Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System
Abstract
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Fault detection plays an important role in both conventional AC and upcoming DC power systems. This paper aims to study the application of discrete wavelet transform (WT) for detecting the DC fault in the high voltage DC (HVDC) system. The methods of choosing the mother wavelet suited for DC fault is presented, based on degree of correlation to the fault pattern and the time delay. The wavelet analysis is performed on a multi-terminal HVDC system, built in PSCAD/EMTDC software. Its performance is judged for critical parameter like the fault location, resistance and distance. The analysis is further extended to validation using results from experiment, which is obtained from a lab-scale DC hardware setup. Load change, one of the transient disturbances in power system, is carried out to understand the effectiveness of the wavelet transform to differentiate it from the DC fault. The noise in the experimental result gives rise to non-zero wavelet coefficient during the steady-state. This can be improved by removing the unwanted noise using right filter while still retaining the faultinduced transient. The wavelet transform is compared with short-time Fourier transform to highlight the issue with window size and noise. Keywords: DC fault, wavelet transform, multi-terminal HVDC, modular multi-level converter, PSCAD/EMTDC, DC system experiment, time-frequency analysis, fault detection
1. Introduction
High voltage direct current system (HVDC) is one of the important technologies that have taken the conventional power system in a new direction. While a lot of research efforts are put into the design of controller and control strategy of the HVDC system, it is equally important to address the protection issue in the system so that the damage caused by the fault is brought down to minimum. I The work was supported by the Start-Up Grant (M4081547.040), Nanyang Technological University, Singapore. Email addresses: [email protected] (Yew Ming Yeap), [email protected] (Nagesh Geddada), [email protected] (Abhisek Ukil)
Preprint submitted to Applied Soft Computing
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The traditional high voltage AC circuit breaker (CB) takes advantage of current zero crossing which enables it to be tripped in a safe manner. Such phenomenon, however, is not seen in the DC current. The absence of current zero means that the mechanism of the breaker in the DC system should be completely different. Due to lack of such technology, most of the present HVDC systems are restricted to point-to-point connection, where the AC CB is adequate for protection. The interest was renewed when ABB [1] and Alstom [2] proposed the hybrid DC CB. It is arguably one of the key enabling technologies that will potentially pave the way for the deployment of HVDC system with increasing connections, towards a multi-terminal DC (MTDC) grid. Development in power electronics converter technology has been critical for the advancement of the HVDC system. In comparison with the current source converter (CSC), the voltage source converter (VSC) is relatively more vulnerable to the fault on the DC side due to low DC-side inductance. Rapidly increasing DC current can damage the devices if the fault is not treated immediately. ABB’s hybrid DC CB [3] is capable of isolating the fault within 5 ms, this poses a challenge to the design of protection algorithm to meet such a stringent requirement. In addition, as the HVDC system is moving towards the scale of multi-terminal, locating the faulted line has become another important aspect of the protection system. In recent times, DC fault detection methods have gained a significant research attention in the HVDC system. Traveling wave is well established methid in conventional AC power system for its effectiveness in locating the fault point. Its application on the HVDC system had been studied extensively [4]. This technique, however, requires high sampling rate for data collection in order to accurately capture the wave-front arrival time. Fault detection based on the DC current measurement was proposed in the works [5, 6], whereby the rate of change of DC current (di/dt) forms the basis of fault criterion. While it is simple and computationally efficient, it has difficulty determining the faulted section independently as the system becomes highly meshed. DC fault can be also detected by pattern recognition, in which the measured voltage is compared with already known signal and the degree of similarity is measured by Pearson correlation coefficient [7]. However, such method might lack generality. Zheng et al. [8] reported that DC fault transient in CSC-HVDC system resulted in generation of certain harmonics, which could be leveraged to form a fault basis. Due to different operating conditions between CSC and VSC, its application on the latter remains to be investigated. The wavelet transform (WT) can be regarded as one of suitable techniques for processing the non-stationary fault signals [9, 10]. This signal processing technique is capable of interpreting the signal in time and frequency domain. WT has also been applied to detect disturbance in conventional AC power system [11–16]. One of the benefits of using the WT is that it is able to discriminatingly identify the DC fault against non-concerned disturbances (AC fault and load change) [17]. Using the WT, the faulted line can be determined in a meshed network without the need of communication channel, hence substantially reducing the detection time [18]. Abu-Elanien [19] in their work showed 2
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that this technique is able to withstand the influence of fault location and fault resistance to certain extent. This paper presents a detailed analysis of the wavelet-based method for detecting and locating fault in DC system, with software and hardware validations. Protection strategy is not of major focus. Rather, this paper attempts to thoroughly evaluate the performance of the WT using real fault signals. The influences of fault location, resistance and distance in the modular multilevel converter-based (MMC) HVDC system, modeled in PSCAD/EMTDC, are studied. The inter-terminal communication is opted out, as the wavelet detection scheme only requires the DC current signal which is locally available in each terminal. The influences of fault resistance and distance are also validated, using the experimental results obtained from the point-to-point hardware DC system operating at lab-scale voltage level. This paper also presents how capable is the wavelet transform when it comes to differentiating DC fault from load change, which is carried out experimentally. The improvement of the smoothened experimental result using properly designed filter will be discussed. Lastly, the performance comparison between the wavelet transform and the short-time Fourier transform (STFT) will be presented. The remainder of the paper is structured in the following manner. In Section 2, the background of DC fault is presented, followed by brief introduction of the wavelet transform and selection of mother wavelet in Section 3. The simulation and experimental results are covered in Section 4 and 5, respectively. Finally, the conclusions are given in Section 5.
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2. DC fault in HVDC System
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This section briefly explains the DC fault analysis in the MMC-based HVDC system. The DC fault can be divided into following types: pole capacitor unbalance, pole-to-ground (PG) and pole-to-pole (PP) fault. DC cable is relatively more vulnerable to the PG fault caused by insulation breakdown than PP fault [10]. Due to direct exposure to air, the DC overhead line is prone to the occurrence of these two faults. PP fault has the potential to result in extremely destructive damage to the HVDC system. Therefore, it is always considered as the most representative DC fault in literatures [20], as well as in this paper. Modeling of MMC and two-level VSC are fundamentally same, in which the converter station can be represented as DC current source in the DC side. The combined submodular capacitance Ce is described in (1), under the balanced condition, and the derivation can be found in [21, 22]. Ce =
6C . n
(1)
The DC side equivalent circuit of single MMC is represented in Fig. 1, at the instant of PP fault occurrence. Icv is the total current injected to the DC side. The Ldc and Rdc are the π-model equivalent inductance and resistance of the positive and negative poles. The fault resistance is denoted by Rf . Immediately
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Figure 1: Equivalent circuit of MMC DC side during DC fault. (a) Stage 1: DC capacitor discharge stage, (b) Diode freewheeling stage
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as the fault current exceeds the threshold, the IGBTs in the submodule will be blocked. Then, the current flow switches to the freewheeling diodes, which is shown in Fig. 1(b). By this time, it is important to clear the fault fast enough before the current reaches beyond the I 2 t capacity of diodes. The fault analysis can be divided into three stages: 1) DC capacitor discharge stage, 2) diode freewheeling stage, 3) AC infeed stage. The discharge of capacitor (Icap ) dominates the fault current in the first few time-instant of fault. When the DC voltage drops to zero, the AC side will continue supplying current to the fault point [23, 24]. The fault analysis here only focuses on stage 1 and 2, as these periods are critical for wavelet transform to make fault decision and dispatch IGBT block signal, preferably within 2 ms. The circuit in Fig. 1(a) can be represented by (2). (2)
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d2 Idc Re dIdc 1 + + Idc = 0 dt2 Le dt Le Ce
where Re = 2(Rdc /2) + Rf and Le = 2(Ldc /2). The under-damped response is met on the condition Re2 < (Le /Ce )1/2 . Assuming that the PP fault happens at t0 with the initial conditions of Vdc (t0 ) = V0 and Idc (t0 ) = I0 , the solution of the second-order RLC differential equation is given as, " # V0 Le − δI0 −δt Idc (t) = e I0 cos(ωt) + sin(ωt) , (3) ω " # I0 δV − 0 C e Vdc (t) = e−δt V0 cos(ωt) + sin(ωt) . (4) ω where δ = Re /2Le and ω = (1/Le Ce − (Re /2Le )2 )1/2 . The DC voltage (Vdc ) reaches zero when the DC capacitor (Ce ) gets dis0 charged. Now, the fault current (Idc ) is freewheeling within the three-phase diodes as the corresponding IGBTs are already blocked, depicted in Fig. 1(b). The line inductor (Ldc ) disallows sudden change of current, therefore the initial 4
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0 current for this stage is Idc (t1 ) = Idc (t1 ) = I00 . The circuit is now reduced to a RL circuit, so the expression of the fault current is given as:
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0 dIdc 0 + Rdc Idc = 0. dt The first order differential equation is solved:
Ldc
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(6)
is equally distributed in three-phase diodes:
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(5)
0 ID1 (t) = ID2 (t) = ID3 (t) = Idc (t)/3.
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3. Wavelet Transform
(7)
3.1. Theory
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Wavelet transform (WT) is used for fault detection instead of Short Time Fourier Transform (STFT). While both signal processing techniques are able to analyze non-stationary signal in time and frequency domain, the window size of the STFT is fixed. A longer window yields good frequency resolution at the expense of time resolution, and vice versa. A convenient solution to this dilemma is the WT, as it automatically changes the window size in response to the dynamics of the signal. It is able to capture the high frequency abrupt change, which is specially needed for detecting the fault. The WT breaks up a signal into the shifted and the scaled versions of the original (or mother) wavelet, allowing for simultaneous time and frequency analysis. The continuous wavelet transform (CWT) is defined as the sum over all time of the signal multiplied by the scaled and shifted versions of the wavelet function. Z +∞ ∗ CW T (a, b) = x(t)ψa,b (t)dt. (8) −∞
t−b ). (9) a ψ(t) is the mother wavelet, the asterisk in (8) denotes a complex conjugate, and a, b ∈ R, a 6= 0 (R is the real continuous number system) are the scaling and the shifting parameters, respectively. The discrete wavelet transform (DWT) −m/2 in (10) is given by choosing a = a− b0 , t = kT in (8) and (9), 0 m/2, b = na0 where T = 1.0, and k, m, n ∈ Z, (Z is the set of positive integers). ∗ ψa,b (t) = |a|−1/2 ψ(
−m/2
DW T (m, n) = a0
−m/2 X k − na0 b0 ( x[k]ψ ∗ [ ]). m a0
(10)
We apply the multiresolution signal decomposition (MSD) [25, 26] technique to decompose a given signal into detailed and smoothed versions. Let x[n] be a 5
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discrete-time signal, then the MSD technique decomposes the signal in the form of wavelet coefficient at scale 1 into C1 [n], the smoothed (time-domain view) and D1 [n], the detailed (frequency-domain view) coefficients. The decomposition process can be iterated, with successive approximations being decomposed in turn, so that the original signal is broken down into many lower resolution components. This is called the wavelet decomposition tree [25, 26], shown in 2. MSD technique can be realized with the cascaded quadrature mirror filter (QMF) banks [27, 28]. So, for example, using 4-scale decomposition, the original signal s can be represented as: x[n] = C4 [n] + D4 [n] + D3 [n] + D2 [n] + D1 [n].
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Cj[n]
Dj[n]
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Figure 2: Multiresolution signal decomposition.
3.2. Wavelet Selection
The wavelet coefficient is the cross-correlation of the signal and the mother wavelet; the higher the wavelet coefficient, the closer the signal matches with the chosen mother wavelet. Thus, a suitable wavelet should be selected such that it presents closest match to the pattern of the fault signal. Ma et al. [29] presented a method to facilitate the wavelet selection by using the Pearson product-moment correlation coefficient, as represented in (12). Pn ¯ i − Y¯ ) (Xi − X)(Y r = qPi=1 (12) n ¯ 2 (Yi − Y¯ )2 (X − X) i i=1 where Xi and Yi are the data sets of the fault signal and the wavelet respectively, ¯ and Y¯ . their corresponding averages being X In this case, Xi is the fault signal as depicted in Fig. 3, while Yi corresponds to the chosen Daubechies mother wavelet. 6
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Figure 4: Correlation coefficient between fault signal and Daubechies wavelet of order 2-9. The correlation coefficients between the fault signal and the Daubechies mother wavelet of varying order (db2 − db9) are computed and depicted in Fig. 4. It is found that db3 provides the best match among these candidates for the given fault pattern. 3.3. Mother wavelet and time delay Besides having adequate sensitivity to the transient caused by the DC fault, it is equally important to choose the right mother wavelet that yields high-speed fault detection. Fig. 5 shows the performance of Haar, Daubechies and Coiflet mother wavelets for providing the maximum wavelet coefficient and corresponding time delay.
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Figure 5: Time delay introduced by different mother wavelets. sf is the time the DC fault-induced transient begins to appear. It is noticed that compact wavelets work well to localize high frequency components in the transient with minimum time delay. In this case, Haar and db2-3 are the ideal mother wavelets because they produce the maximum wavelet coefficients with no delay. For the Daubechies wavelet family, db5 begins to show delay by one sample. Coiflet wavelet is inappropriate for DC fault detection as far as speed is concerned. The analysis here agrees with the finding in Santoso’s work [30], which reported that db4 and db6 are suitable for fast transient in conventional AC system. 4. Performance evaluation of wavelet transform - simulation result Fig. 6 shows the MMC HVDC model consisting of four terminals (MMCi, i =1, 2, 3, 4) developed in PSCAD/EMTDC. Four strong AC systems (ACi ) are connected with ring and monopole DC network. The DC lines (Lij, i, j = 1, 2,
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Figure 6: 4-terminal MMC HVDC model.
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Table 1: System data
Values 600 MVA 50 Hz 10 100 1000 µF 50 mH 180 Hz 100 km 200 km
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Parameters Rated power AC frequency AC system short circuit ratio Number of submodules per arm Module capacitor Arm inductor Switching frequency Length L12, L13, L34, L24 Length L23
3, 4), consisting of positive and negative poles, are represented as single line in the figure. The MMC adopts the detailed equivalent modeling (DEM) [31], with MMC1 working as fixed DC voltage control and the rest as fixed active power control. Its corresponding functional control structure will not be elaborated here, the detail can be found in [21, 32]. The full system data is given in Table 1. The DC currents (Idcij, i, j = 1, 2, 3, 4) are measured at each terminal (MMCi ). The IGBTs will not be blocked in the simulation as the focus is to identify the signature associated with fault in the DC current signal. The signals are exported to MATLAB and post-processed with discrete wavelet transform algorithm to generate the wavelet coefficients. The fault location (df ) is the distance from the fault to the monitoring terminal. The fault simulated here is the PP fault, with the fault resistance denoted as Rf . The sampling rate (fs ) is selected based on the available frequency range offered by digital fault recorder [33]. The mother wavelets to be adopted is db3, since it has been shown in Section 3 that it presents the closest similarity with 9
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fault pattern. The application of wavelet transform on the fault identification in the multi-terminal system is evaluated by considering the three cases below:
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• To study the influence of DC fault location: PP fault on Lij (i, j = 1, 2, 3, 4), Rf = 0.01Ω, df = 50km, fs = 15360Hz, using db3.
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• To study the influence of DC fault resistance: PP fault on L12, 0.01 < Rf < 500Ω, df = 50km, fs = 15360Hz, using db3.
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Figure 7: Detailed wavelet coefficient for each DC line current in different PP fault location. a) L12, b) L13, c) L34, d) L24, e) L23.
4.1. Influence of DC fault location Fig. 7 shows the wavelet coefficient obtained from the PP fault simulated on the DC lines in the multi-terminal HVDC system. The PP fault is initiated by shorting the positive and the negative DC lines through a fault resistance. Therefore, only the wavelet coefficient for positive pole DC current is presented here. The wavelet coefficient remains low during the steady-state, approximating to zero. The occurrence of fault on a DC line is detected when the DC current of 10
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the faulted line generates a high wavelet coefficient abruptly. To illustrate, PP fault on L13 (see Fig. 7(b)) generates large overcurrent in fault current between MMC1 and MMC3, resulting in high wavelet coefficients for Idc13 and Idc31 . Similar pattern is observed in other cases. With the high wavelet coefficient obtained at 243th sample, the fault is detected with a time delay of 1.09 ms. Additionally, the wavelet transform allows the healthy terminals to recognize that the fault is outside their protection zone, since the wavelet coefficients of their currents remain consistently low. The discriminative nature of wavelet transform has been validated. It is a reliable method for each terminal to independently identify the fault by just monitoring the DC current.
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Figure 8: Effect of PP fault resistance on detailed wavelet coefficient for each DC line current.
4.2. Influence of DC fault resistance This subsection studies the robustness of the WT to detect the high resistance fault in a multi-terminal HVDC system. Fig. 8 shows the trend of the wavelet coefficients of DC currents as the fault resistance on L12 is increased from 0.01 Ω to 500 Ω. The wavelet coefficient appears to be constantly high for the PP fault resistance ranging from 0.01 Ω to 5 Ω. Beyond that, however, the value begins to show downward trend. This can be explained by the fact that fault induced transient has been dampened by large fault resistor. As a consequence, the wavelet coefficient decreases with increasing fault resistance. Nevertheless, the wavelet coefficient of fault current remains vastly above that of healthy DC current by large margin. 4.3. Influence of DC fault distance The fault-induced transient is the function of fault location. If a DC fault happens in close proximity to a terminal, the DC current of that terminal will experience bigger frequency change and higher magnitude. Fig. 9 shows the 11
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Figure 9: Line current (a) Idc12 , (b) Idc21 and their corresponding detailed wavelet coefficient (c), (d) under the influence of fault distance. df =15km and df =85km are represented by black line and red dashed line, respectively.
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wavelet coefficients of Idc12 and Idc21 as the location of PP fault (df ) is adjusted from 15 km to 85 km away from MMC1 along L12. Fig. 9(a)&(b) illustrates the relationship between the change of DC current and fault location. The current magnitude decreases and the transient becomes dampened as the fault point increases. This phenomenon is reflected in their wavelet coefficients. For example, the fault at df =85km yields the wavelet coefficient about -0.2342 for Idc12 and -1.389 for Idc21 . Despite diminished sensitivity, the fault can be successfully detected for all distances evaluated. 5. Performance evaluation of wavelet transform - experimental result
Laboratory DC system experiment setup is developed to study DC fault with variation of fault parameters. The schematic block diagram of the setup is shown in Fig. 10 and various parameters, ratings are given in Table 2. Experimental studies are performed at input voltage of 85 V (line rms). Three phase, 30 kVA, (0-450) V, variable transformer was used to set the desired input voltage of 85 V. Converters (VSC1, VSC2 ) at the DC side are rated at 30 kVA, 415 V. The voltage and current quantities at power level are converted to signal level using hall effect voltage (± 500 V to ± 15 V) and current (± 10 A to ± 4 V) transducers. These signals are fed to the dSPACE 1103 controller through 12
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Laboratory Three phase Supply Side
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Table 2: Experiment Setup Parameters
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Parameters Supply voltage 3φ AC Protection Board 3φ Variable Transformer Converters (VSC1, VSC2) DC Capacitor DC Line Paramters DC MCB Interface Filter Parameters Linear Load Variable Power Resistor DC Solid State Relay
Values 3φ, 85 Vrms , 50 Hz 40 A, B Type, TP MCB with Shunt trip 30 kV A, (0-415) V 30 kV A, 400 V Cdc = 2350 µF , Ld = 1.5 mH,Rd = 0.03 Ω C60H-DC, C 4 A Rf = 0.1 Ω, Lf = 10 mH Rl = 20 Ω 5000 W , (1-16) Ω D2D40, 200 V , 40 A
analog to digital channels (ADCH) ports. The control algorithm is developed in MATLAB/Similink and converted for the dSPACE hardware interface by
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the means of Real Time Interface (RTI) toolbox. The pulse-width modulation (PWM) gating pulses generated by the controller are fetched to the VSCs for switching.
Figure 11: (a)Experimental result for 2 Ω DC fault; (b)Wavelet coefficients for Idc12 and Idc21 .
Direct short-circuit across the DC line is not viable as the large fault current could trigger the tripping of main circuit breaker in the laboratory. In order to limit the magnitude of the fault current, a power resistor is inserted between upper and bottom DC line and the connection is controlled by a DC solid-state relay. During the startup of experiment, the relay remains open. When the system has achieved steady-state, the relay will be closed to electrically establish a connection across DC line via power resistor. The value of the resistance is adjustable from 1 Ω to 16 Ω. Fig. 11 shows the measurements of Iac1 , Vdc1 , Idc12 and Idc21 , in that or14
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der on LeCroy Wavesurfer 3024 oscilloscope, for 2 Ω DC fault. The sampling frequency used in the measurement is 10 kHz. The signals of interest here are Idc12 and Idc21 . The segment in dashed box is zoomed in to better visualize the fault-induced transient. The corresponding wavelet analysis using db3 is presented in the same figure. One can immediately notice that the steady state DC currents essentially do not yield zero wavelet coefficient as seen in the simulation results. The value falls between [w1,w2 ], marked by the dashed line. For now we take [w1,w2 ] as threshold, it will be discussed in subsection later how removing the noise in the signal can reduce the steady state wavelet coefficient. As expected, abrupt increase of current caused by the DC fault registers high wavelet coefficients for both currents. The fault inception time (3s) is translated to 1877th sample at 4th level of decomposition. The highest wavelet coefficient is obtained by one sample delay. Even with the delay introduced by filtering, the detection time would still be reasonably short.
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5.1. Influence of DC fault resistance
Figure 12: Wavelet coefficient for DC fault of varying fault resistance (a) 4 Ω; (b) 6 Ω; (c) 8 Ω; (d) 10 Ω; (e) 12 Ω; (f) 14 Ω. Similar to the Section 4.2, repeated experiments are carried out to evaluate the performance of wavelet transform for different fault resistance, ranging from 4 Ω to 14 Ω. Fig. 12 depicts the result of wavelet analysis on the DC currents (Idc12 & Idc21 ). 15
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The faults are detected for all fault resistances evaluated. The highest wavelet coefficient is observed around sample number 1878 (equivalent to 3.0016 s). Despite the presence of noise in the signal, the wavelet coefficients are kept within the presumed threshold, marked by the dashed line in the figures, during steady-state. The wavelet coefficient shows downward trend when increasing the fault resistance. Nevertheless, a reasonably big margin between the threshold and the wavelet coefficient still justifies the effectiveness of the WT in detecting the DC fault.
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5.2. Influence of DC line length
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Figure 13: DC line represented by RL circuit in experiment and different line length to be investigated.
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Similar to the Section 4.3, our interest is to study the effect of fault distance on the WT at experimental level. Besides the fault location, the frequency content of the transient is also a function of the DC line length. Three tests with different combination of inductance representing different fault location and DC line length are carried out, as shown in Fig. 13. The DC currents are analyzed with the WT and the result is shown in Fig. 14. The WT successfully detects the DC fault with the wavelet coefficient exceeding the threshold by large margin. One can observe that the terminal closer to the fault has current yielding the higher wavelet coefficient than its counterpart. For example, in Test 3, smaller L2 and L4 implicates the fault to be closer to the VSC2, and the fault at this location results in higher wavelet coefficient for Idc21 compared to Idc12 . Nevertheless, the two terminals are able to recognize the occurrence of DC fault as their maximum wavelet coefficients are consistently higher than threshold for all fault locations evaluated.
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Figure 14: Wavelet coefficient for DC fault of varying fault location (a) Test 1; (b) Test 2; (c) Test 3. 5.3. Influence of other type of power system disturbance
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Figure 15: Experimental result and wavelet analysis for (a) DC fault; (b) Load change.
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Load change in power system results in current increase that could be mistaken for DC fault. This subsection aims to study the feasibility of the WT in differentiating between DC fault and load change. To reproduce this phenomenon at experimental level, the resistive load at receiving end is reduced abruptly such that it generates a transient that reaches the same peak as faultinduced transient. The results from the experiment and the corresponding wavelet coefficients are shown in Fig. 15. As expected, the Idc12 in DC fault produces high wavelet coefficient. Although the load change causes transient in the DC current, its wavelet coefficient appears to increase not very much, barely crossing the presumed threshold. Thus, it is now clear that the DC fault can be differentiated from the load change using the WT.
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Figure 16: (a) Raw and denoised signal for DC fault at 14 Ω; (b) Wavelet coefficient for denoised signal.
The signal measured directly from the experiment contains the noise amounting to 11.421 dB signal-to-noise ratio (SNR). The noise gives rise to non-zero wavelet coefficient during steady state. However, the wavelet coefficient appears to stay within the presumed threshold in all the studies so far. This subsection investigates on filtering the noise. The Idc12 for DC fault at 14 Ω is smoothened with bandstop filter so as to retain the fault-induced transient which is of high frequency and critically needed 18
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5.5. Comparison with short-time Fourier transform method
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for detection. The denoised signal now has 27.658 dB SNR during steady-state. Fig. 16 depicts the difference between raw and denoised signal. When analyzed with the WT, it is noticed that the steady-state wavelet coefficient has decreased substantially (see Fig. 16(b)), compared to that in Fig. 12(f). Furthermore, the maximum wavelet coefficient does not deviate much as a result of filtering, proving that the fault transient in the denoised signal is still preserved. Hence, an appropriate filtering is highly recommended if one wants to keep the steady-state wavelet coefficient as low as possible.
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Figure 17: Frequency spectrum of experimental fault current for window length (a) 16, (b) 32 and (c) 64. Zero-crossing frequency bin is marked by dash line.
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The problem with choosing the window size for STFT has been discussed in Section 3. For the purpose of fast fault detection, small window is preferable at the expense of frequency resolution. The STFT analysis of high frequency components in transient signals was reported in [34]. During steady-state, the frequency spectrum of constant DC current should resemble a sinc function, with the main-lobe concentrated at 0 Hz, with side-lobes uniformly distributed. A key feature in the frequency spectrum is the zero-crossing frequency bin. Considering n as window size in term of sample number, the zero-crossing frequency bin appears at 2fs /n, 3fs /n, 4fs /n and so on. When the DC fault happens, the high-frequency transient will have its signal energy leak into other frequencies, causing visible distortion across the side-lobes. Based on this phenomenon, the fault can be detected by tracking the magnitude of zero-crossing frequency bin, which will increase under the fault condition. The frequency spectra of experimental fault current (Idc12 ) for 16, 32 and 64-sample window lengths using Hanning window are shown in Fig. 17. 1. 16-sample: The first zero-crossing frequency bin for this window is 1250 Hz. It can be seen that the side-lobes has already experienced slight distortion caused by signal noise even before the fault occurrence. The zero-crossing frequency bin increases above 0 dB (threshold) at 0.8 ms after the fault inception. At which time, the fault is successfully detected.
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2. 32-sample: The influence of noise is comparatively less significant for this window size, given that the side-lobes retain equiripple-like pattern during pre-fault. The first zero-crossing frequency bin (625 Hz) exceeds the threshold with a time delay of 1.6 ms. 3. 64-sample: Similar to 16-sample window, the side-lobes are heavily distorted by the noise during pre-fault. The fault is detected when the first zero-crossing frequency bin (312.5 Hz) increases above threshold after 3.2 ms.
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It is observed that the detection time is very much dependent on the window size. 16-sample window provides the fastest detection. However, the signal noise can cause significant distortion making the tracking of frequency difficult. The influence of noise is also observable in 64-sample window while 32-sample window is minimally affected. The STFT is met with the difficulty of choosing the window size. The wavelet transform, on the other hand, can adjust the window size automatically to suit the fault signal. In addition, as part of the process of cascaded filtering, the wavelet transform is able to preserve the critical signal while eliminating noise, but this cannot be done by the STFT. 6. Conclusion
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The application of the wavelet transform to detect and identify the DC fault in HVDC system has been analyzed and validated using simulation and experimental results. db3 is adopted in the wavelet analysis as it presents the closest match to the fault pattern and is able to detect fault with minimal delay. The simulation result shows that the wavelet transform is able to independently detect the faulted line in a 4-terminal HVDC system, only using the wavelet coefficient for the DC line current at each terminal as criterion. The detection time is approximately 1 ms. The value of the wavelet coefficient decreases as the fault resistance and the fault distance are increased, however it is still well above the threshold by large margin. From the experimental results, it can be inferred that the wavelet transform also presents reasonable robustness to the influence of fault resistance and distance. It is not sensitive to the transient caused by load change, allowing to classify the DC fault from other types of disturbances. The inherent noise in the experimental result yields a non-zero wavelet coefficient, thus the threshold needs to be set above that so as to avoid wrong detection. The steady-state wavelet coefficient can be vastly reduced by smoothening the raw signal. The filter has to be properly designed so that only the unwanted noise is removed while the fault-induced transient, which is of high frequency, is still preserved. Compared to the short-time Fourier transform (STFT), the wavelet transform provides better flexibility when it comes to selecting window size and tolerance against noise.
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[31] U. N. Gnanarathna, A. M. Gole, R. P. Jayasinghe, Efficient modeling of modular multilevel hvdc converters (mmc) on electromagnetic transient simulation programs, IEEE Transactions on Power Delivery 26 (1) (2011) 316–324.
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[32] J. Beerten, S. Cole, R. Belmans, Modeling of multi-terminal vsc hvdc systems with distributed dc voltage control, IEEE Transactions on Power Systems 29 (1) (2014) 34–42.
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[33] A. Ukil, B. Deck, V. Shah, Current-only directional overcurrent protection for distribution automation: Challenges and solutions, IEEE Transactions on Smart Grid 3 (4) (2012) 1687–1694.
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[34] Y. M. Yeap, A. Ukil, N. Geddada, Stft analysis of high frequency components in transient signals in multi-terminal hvdc system, in: IECON 2016 42nd Annual Conference of the IEEE Industrial Electronics Society, 2016, pp. 4008–4013.
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Paper: Analysis and Validation of Wavelet Transform Based DC Fault Detection in HVDC System
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Authors: Yew Ming Yeap, Nagesh Geddada, Abhisek Ukil
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Highlights
High voltage direct current system (HVDC) is one of the important power transmission
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technologies.
Protection of HVDC system is a must for safe and reliable power transfer, but it is not
Protection of the DC system is not as mature as AC system due to lack of devices and
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Simulation of multi-terminal HVDC system with DC fault are performed using the
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PSCAD/EMTDC.
Wavelet transform based fast detection of fault in HVDC system is described in details.
Lab-scale DC transmission setup is made, and experimental results are presented to
Ac ce p
te
substantiate the wavelet transform based method.
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