Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability

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Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability Liang Wen a,n, Zhikui Duan b, Yi Li a, Xiaoyang Zeng a a b

State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China School of Information Science and Technology, Sun Yet-sen University, Guangzhou 510000, China

art ic l e i nf o

a b s t r a c t

Article history: Received 10 October 2013 Received in revised form 24 February 2014 Accepted 26 February 2014

In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40
higher that of 6T cell at 1.0 V, and 8.16
higher at 0.3 V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0 V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty. & 2014 Elsevier Ltd. All rights reserved.

Keywords: Disturb-free SRAM 9T SRAM Bit-interleaving Loop-cutting

1. Introduction Low-power and robust SRAM designs have drawn great research attention in the last decades. Especially the explosion of the mobile devices and portable electronic market extremely urges the increasing requirements of less power-hungry architecture. The adoption of supply voltage scaling has been proved to be the highest effectiveness in energy saving since it can reduce the dynamic power quadratically and leakage current exponentially [1]. However, with the miniaturization of devices, the variability of SRAMs in process parameters and threshold voltage together with Ion–Ioff ratio increase severely, which degrades the Static Noise Margin (SNM) dramatically [2]. Furthermore, the SNMs are linearly dependent on the supply voltage, scaling down which to save power has exerted an adverse influence on the cell stability. So, how to maintain the cell stability and simultaneously keep an ultra-low power consumption become the main themes of SRAM designs in this scenario that voltage reduction along with device scaling are associated with decreasing signal charge. In conventional 6-Transistors (6T) SRAM design, the conflicting requirements of read stability and write ability make the cell prone to unstablity and limit the minimum operating voltage (Vmin) of the cell, which is becoming a catastrophic bottleneck for a

n

Corresponding author. Tel.: þ 86 136 2169 1973. E-mail addresses: [email protected], [email protected] (L. Wen).

6T SRAM. With increased process variations and lower Vmin constraint, it is extremely difficult to balance the read stability and write ability requirements of a cell by delicate transistor sizing. To solve the aforementioned conflict in SRAM design, many other more-than-6T SRAM cells have been proposed in [3–16]. These SRAM cells isolated the read port and write port and hence the read stability and write ability could be optimized individually without affecting each other. However, most of them can only be implemented in a word-line sharing structure, but do not support bit-interleaving (or column-selection) which is always preferred to improve the SRAM's soft error immunity. As far as the soft error is concerned, it becomes more critical with the reduction in supply voltage. As reported in [17], the soft error rate increases by 18% for every 10% supply voltage reduction. Especially in advanced technology, the capacitance of storage nodes becomes less, which makes the SRAM's poorer resistance to soft error pronounced. The bit-interleaving scheme can provide the SRAM's soft error protection effectively since it can spatially separate bits of a word in the row and only simple single-bit error correction coding (ECC) is required. In the above-mention SRAMs, the stored data of unselected cells would potentially be upset during the write operation when bit-interleaving configuration is used, which we called half-selected disturbance. Of course, some other SRAM cells with bit-interleaving have been presented in [18–22] in the past. Nonetheless, these cells introduce write performance degradation, largely area overhead, or additional peripheral circuits to support their operations.

http://dx.doi.org/10.1016/j.mejo.2014.02.020 0026-2692/& 2014 Elsevier Ltd. All rights reserved.

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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In this paper, we present a new read disturb-free 9T SRAM cell with bit-interleaving capability. It exploits a column-aware feedback-cutoff scheme to perform write operation, resulting in write margin improvement and non-destructive bit-interleaving configuration. In addition, a dynamic read disturb-free scheme is employed in the cell, which results that the cell has a robust read operation and larger read current without read margin sacrificed. Experimental results show that our proposed design exhibits considerable improvement in write ability, read robustness, write and leakage energy consumption, as well as better process variation tolerance. An overview of this paper is constructed as follows. Section 2 elaborates the circuit design and operation principles of the proposed cell, and an extensive discussion of cell stability and performance, including simulation results, is described in Section 3. Section 4 summarizes the paper.

WL M0 M2

LWL M1

M3

Long-Channel Transistor

Q M6 M7

CBL BL CBLB

2

M4

QB

Normal-Channel Transistor

M5

M8

RWL Fig. 2. Schematic of the proposed 9T SRAM cell RWL: read WL, BL: bit-line, CBL: column BL, CBL: CBL bar, and LWL: local WL.

Write '1'

2. Proposed 9T SRAM cell

1

Shared word-line (WL) architecture is commonly used to arrange array in SRAM designs due to its simplicity and compactness. However, the multi-bit soft error is very high since the adjacent bits share a WL each other, which has a detrimental impact on the yield of the chip. Certainly, a hierarchical WL scheme can be used to choose only one local WL in a low by an AND gate, but this introduces a large area overhead. Bit-interleaving is a preferable alternative to provide soft error protection in combination with single-bit ECC, whereas the traditional 6T SRAM suffers halfselected disturbance seriously, especially in the advanced process and lower voltage, making it less for the first consideration. To address the problem of half-selection, a differential 8T SRAM cell has been proposed in [22] recently, as shown in Fig. 1. A special inverter with the function of AND logic operation is utilized to activate the local word-line (LWL), the supply power of which is controlled by column select signal (CS). When the CS is enabled, only the selected LWL is driven to high, eliminating the half-selected disturbance. Unfortunately, the fundamental stability problem still occurs in 8T cell when performing read activity because of the voltage dividing between the access and pull-down transistors, as it implements read and write functionality essentially identical with the standard 6T SRAM cell. Therefore, the cell-VDD-boosted scheme is adopted to enhance read stability in [22]. As a result, the introduced large area overhead becomes intolerable. The schematic of our proposed single-ended 9T SRAM cell is depicted in Fig. 2, the bit-interleaving idea of which originates from the differential 8T SRAM cell. The single-ended 9T cell uses one bit-line (BL) but has to provide one extra word-line (RWL) for read. A NMOStype transistor (M7) controlled by CBLB signal embeds in the left inverter to assist read and write operations. In addition, two long

0

Read '1'

Write '0'

Read '0'

Standby

WL

WL

1

0 1

RWL

CBLB

Cload=30ff

CBL

BL

Cload=5ff

0 1

0

QB

Floating

Q

Time(ns) Fig. 3. Waveforms of the 9T cell at different operating modes.

channel PMOS-type transistors (M2 and M3) are employed to deliver benefits of saving leakage current and enlarging SNMs. The proposed 9T cell has the same bit-interleaving configuration as the differential 8T cell. Nonetheless, it achieves better operating stability, lower power consumption, higher process variation tolerance, and less area overhead due to its special operating schemes. All these merits of the proposed 9T cell will be discussed in Section 3. Fig. 3 describes the signal waveforms of the 9T cell at each operating scenarios. As we can see, at standby mode, the signals WL, BL and CBLB stay high while CBL and RWL maintained low. When WL turns low and CBL is activated to ‘1’, it enables a write operation. Then, the asserted RWL initiates a read operation. Next, we will introduce the operating principles of our proposed 9T cell in detail. 2.1. Standby mode

M0

LWL M1

M2

M3

Q M6

QB M5

M7

BLB

CS BL

M4

Fig. 1. Schematic of differential 8T SRAM cell in [22].

During the hold mode, WL signal is pre-charged to high while RWL signal is switched to low, resulting in the evaluated transistors (M6 and M8) turn-off to prevent any active disturbances from bit-line, as illustrated in Fig. 4. Concurrently, corresponding complementary signal of CBL (CBLB) is set to high, ensuring the M7 turned on. As a consequence, the data retention is afforded by the back-to-back cross-coupled inverter pair. The leakage current of the 9T cell at standby has strong correlation to the stored data, which is the so-called data-dependent leakage current. The leakage problem is accentuated when a data ‘0’ is stored in the cell, where three leakage paths exist, encompassing one from bit-line, and the others coming through M2 and M5 respectively (see Fig. 4). Apparently, the leakage issue with the

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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3

WL=0

WL=1

M0

M0 M2

LWL=0

Q=0

M1

M6 M7

M7

M5

M8

Fig. 5. Schematic illustration of write operation.

Fig. 4. Schematic illustration of hold mode.

First and foremost, the BL is pre-charged to high. Then, the assertion of RWL signal initiates a read operation. If the corresponding cell is accessed, the CBL turns to high and the CBLB is discharged to low while the WL remains at ‘1’. Fig. 7 illustrates the read progress of the 9T cell. The read operation is executed by the dynamic M5/M8 buffer, and an opposite data of the cell is read out. In addition, the switched-off M7 is to isolate the read current from the storage nodes, reducing the impact of process variation and enhancing reliability. In the standard 6T cell, the access transistors and pull-down devices form a resistor–voltage divider between the bit-line and the storage elements during the read operation. This causes the stored ‘0’ node of the cell to bump up to some intermediate voltage due to the noise, which subsequently provides a direct path to ground or increases sub-threshold leakage for the stored ‘1’ node in the cell and then induces discharge of the ‘1’ node,

Voltage(V)

QB

Conventional SE SRAM cell

Write '1' failure Q 0 Time(ns) write '0'

write '1'

0.5

Q

9T cell

QB

0

Time(ns) Fig. 6. Write ‘1’ waveforms of SRAM cells.

WL=1 M0 M2

LWL=0 M1

CBL=1 BL=1 CBLB=0

2.3. Dynamic read-decoupled assist

0.5

Voltage(V)

A write operation starts by pulling down the WL signal and enabling the CBL signal. Then, the LWL signal is pre-charged to ‘1’. Consequently, the written data is transferred from bit-line to storage nodes through M6. Conventional single-ended (SE) SRAM cell [23] suffers write ‘1’ failure without assist techniques owing to the voltage dividing between access and pull-down transistors, especially in the lowvoltage regions. To solve this problem, a column-aware feedbackcutoff write scheme is presented here. As described in Fig. 5, the CBLB is disabled during the write operation, resulting in the M7 switch-off. Thus, the feedback loop comprised the cross-coupled inverter pair is cut off by M7, making the pull-down power toward node ‘Q’ disappeared. As a result, a success write ‘1’ operation is facilitated by our proposed loop-cutting assist scheme. Fig. 6 shows the write ‘1’ waveforms of the SRAM cells at 0.5 V; it can be seen that the write ‘1’ operation is successfully performed with write delay penalty in the proposed 9T cell while conventional SE SRAM cell fails the write ‘1’ operation. Continuing on to the write ‘0’ operation, the proposed 9T cell can afford strong write ‘0’ ability since the NMOS transistor offers strong transfer ‘0’ characteristic and the long-length PMOS transistor is employed to weak the pull-up capability.

M5

RWL=0

RWL=0

2.2. Column-aware feedback-cutoff write scheme

QB=1

M4

M8

proposed 9T cell is analogous to that with the standard 6T cell, but a considerable leakage reduction in the 9T cell is achieved due to the long-length transistor (M2) and downsized transistor (M5).

M3

Q=0

M6

QB=1

M4

M2

LWL=1

CBL=1 BL=1 CLBB=0

CBL=0 BL=1 CBLB=1

M1

M3

M3

Q=1 M6 M7 M4

QB=0 M5

M8

RWL=1 Fig. 7. Schematic illustration of read operation.

thereby destabilizing it. But in our proposed 9T cell, an embedded transistor is used to assist read-out. When performing a read ‘1’ operation, the ‘QB’ node may attain some uncertain voltage transiently even higher than the threshold of the M4. Fortunately,

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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4

loop-cutting scheme impedes the noise from disturbing the storage elements, therewith ensuring a robust read operation. Even though a large read current is incurred in the cell, making the SNMo0 of node ‘QB’, but it is not capable of destroying the stored data in ‘Q’ node. Subsequently, after a read operation, the CBLB goes to high, making the cell entering into hold mode and then perserveing the data. Therefore, the cell overcomes the interdependence between stability and read current, and the threshold of transistors in read buffer could be lower to improve read performance with no noise immunity loss. However, the proposed 9T cell is sensitive to the leakage due to the process variations during a read ‘0’ operation. At this moment, the ‘Q’ node is floating and charged by the leakage current through M6 and M2. If the accumulated charge on the ‘Q’ node is higher than the switching threshold of the right inverter, then the data of the cell may be flipped after read operation. For the accessed cell, this can be solved perfectly since the node ‘QB’ would be connected to BL to maintain the high voltage level. But for the half-selected cells in a column, their high voltage level of QBs is kept by M3. So, the QBs are susceptible to the voltage value of the Qs. In a word, the dynamic retention issue of ‘Q’ ¼0 becomes severely in half-selected cells. Luckily, the CBLB unactivated time is so short that the accumulated charge on the ‘Q’ node is not sufficient to perturb the state nodes of the cell, as elaborated in Section 3. Accordingly, for ‘Q’¼ 0, even if the SNM is less than 0 as well, the contents of the cell would not be corrupted as long as the aggregated voltage is not high enough to turn on the right inverter.

the read-disturbance and much more active power consumption for half-selected cells. Fig. 8 shows a 2
2 bit-interleaving architecture of the 9T cell. It is assumed that the row-0 and column-0 are selected. The access cell performs the write operation successfully as depicted above, and the half-selected cell in a row entirely does not undergo any half-selected disturbance. However, the loop-cutting imparts a negative influence on the stability of the half-selected cell in a column since it is also susceptible to the leakage current as the read ‘0’ operation. Fortunately, the negative pulse width of the CBLB is narrow enough to inhibit the leakage current from upsetting the read ‘0’ and half-selected cells, and also wide enough to ensure the normal functional operations.

3. Cell performance analysis In this section, cell properties such as area, SNM, speed, power consumption, etc. are discussed in comparison with the existing designs, namely the standard 6T cell. Because the differential 8T cell in [22] has the same operating functionality as the standard 6T cell except bit-interleaving and more transistors, thereby we do not discuss it here. In addition, the analytical SRAM cells are based on TSMC 65 nm logic rule design and HSPICE simulator is used. Moreover, the strength ratio of pull-down and access transistor is set to 3 in the 6T cell while other transistors have the minimum dimensions (150 nm/60 nm). In our proposed 9T cell, the length of pull-up devices is set to 75 nm while that of other devices is 60 nm, and all the transistors have the minimal width (150 nm) except the read buffer.

2.4. Non-destruction bit-interleaving 3.1. Area Bit-interleaving is very commonly used in SRAM designs, not only to provide SER protection but also to ease the pitch of the overall layout on both the cell array and periphery circuits, enabling area efficient utilization and wiring of the macro. So, support column selection in write operation is preferable in the state of the art design as process and voltage scale down. In standard 6T cell, the half-selected cells in a row need to experience a read operation during a write operation, which incurs Selected Column

WL<0>= 0

Half-Selected Column

The layout areas of discussed SRAM cells are evaluated in Fig. 9. In proposed 9T cell, an L shape poly is used to achieve layout compactness together with wider read buffer for larger read current (0.3 um and 0.25 um). The layout area of 9 T cell is 2.0234 um2 while that of 6T cell is 1.476 um2, exhibiting 37.1% overhead. If the 6T employs smaller pull-down transistors, the corresponding area overhead of the proposed design becomes larger. However, we can weaken the read buffer to obtain smaller area. When the widths of read buffer decrease to 0.15 um, the area overhead is commensurately reduced by 26.6%, assuming the same logic design rule.

Half-Selected Cell

Accessed Cell ‘0’

‘1’

NW BL

VDD

0.615um

WL GND

BLB

VDD

RWL<0>=0

2.4um

Half-Selected Cell

Non-Selected Cell

WL VDD

GND ‘0’

‘0’

‘1’

Fig. 8. The 2
2 bit-interleaving architecture of the 9T cell.

CL

GND

RWL

RWL<1>= 0

BL

1.035um

CBL<1 > BL<1> CBLB<1>

CBL<0 > BL<0> CBLB<0>

NW

‘0’

‘0’

CLB

WL<1>= 1

‘1’

GND

WL

VDD

1.955um

BL

Fig. 9. Layout views of SRAM cells. (a) 6T and (b) 9T.

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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3.3. Write performance

1.0 SNFP corner T=125°C VDD=0.9V MC=3000 Sigma=3

0.8

Conventionally, a single-ended write scheme has comparative degradation in write ability compared with the traditional write pattern using complementary bit-line pair. Nevertheless a columnaware loop-cutting write scheme is explored to enhanced write ability effectively in our proposed design, but this comes at the expense of write speed trade-off. Therefore, the write performance including write SNM (WSNM) and write delay of SRAM cells will be discussed here.

0.6

0.4

0.2

WSNM

The SNM is a critical criterion to indicate the data operating ability of a cell; the higher the SNM the better the stability. Fig. 10 shows the SNM comparisons of SRAM cells at hold mode. All parameters with Gaussian statistical distributions and 3s variations of 10% are used to investigate the SNM of the SRAM cells with 3000 point Monte Carlo (MC) simulations. The cell's SNM defined as the size of the largest square that can fit into the eyes of the statistical butterfly curves [25]. In the 9T cell, the butterfly curves appear asymmetrical due to the asymmetrical stored structure. Accordingly, the hold SNM (HSNM) equals to the smaller one of the two maximum squares. Fig. 11 shows the HSNM comparisons of SRAM cells with voltage scales down. The normalized HSNMs of SRAM cells culminate at roughly 0.6 V. In addition, our proposed design exhibits slightly degraded SNM curves due to the stacked NMOS and longer-channel PMOS. In other words, the proposed 9T cell is inferior to the 6T cell in terms of data retention ability.

Fig. 12 shows the statistical butterfly curves of SRAM cells during the write operation with 3000 samples MC simulations at the worst scenario (SNFP corner, 125 1C). For a correct write operation, two voltage transfer curves (VTCs) could only have one intersection. In other words, the cell is at its mono-stable state. Write SNM (WSNM) is defined as the length of the maximum squared embedded the VTCs, which gives an indication how strong the noise is required to destroy the mono-stability. Notice that the VTC diagram of write ‘0’ in presented circuit is completely different from that of write ‘1’ because of the single-ended

QB(Q)(V)

3.2. Hold stability

5

0.0 0.0

0.2

0.4

0.6

0.8

1.0

Q(QB)(V)

1.0 Standard 6T Proposed 9T SNFP corner T=125°C VDD=0.9V MC=3000 Sigma=3

SNM of 9T

QB(Q)(V)

0.6

0.8

QB(Q)(V)

0.8

0.4

0.6

0.4

0.2

SNM of 6T

0.2

SNFP corner T=125°C VDD=0.9V MC=3000 Sigma=3

SNM for write "0"

0.0 0.0

0.0 0.0

0.2

0.4

0.6

0.2

0.8

0.4

0.6

0.8

1.0

0.8

1.0

Q(QB)(V)

Q(QB)(V) Fig. 10. Statistical butterfly curves at standby mode.

1.0

Standard 6T

SNM for write "1"

0.36

0.8

Q(QB)(V)

HSNM / Voltage

0.34

0.32

Proposed 9T

0.30

0.6

0.4 SNFP corner T=125 °C VDD=0.9V MC=3000 Sigma=3

Degraded SNM curve 0.28

0.2

0.26

0.0 0.0 0.2

0.4

0.6

0.8

1.0

Voltage(V) Fig. 11. HSNM/VDD ratio comparisons of each cell at different voltages.

0.2

0.4

0.6

QB(Q)(V) Fig. 12. Statistical write butterfly curves of SRAM cells. (a) 6T; (b) write ‘0’ for 9T; (b write ‘1’ for 9T.

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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3.4. Read analysis In this section, the read stability and read current of SRAM cells are discussed. Figs. 15 and 16 plot the statistical butterfly curves of the analyzed SRAM cells at the worst read scenarios (FNSP corner, 125 1C). The standard 6T cell obtains a pair of extremely mirrored VTCs due to the entirely symmetric cell structure but a 0.5

WSNM / Voltage

0.4 1.40X improvement 0.3 8.16X improvement 0.2

0.1

Proposed 9T(write '1') Proposed 9T(write '0') Standard 6T

0.0 0.2

0.4

0.6

0.8

Voltage(V) Fig. 13. WSNM/VDD ratios against voltage.

1.0

10-8 Standard 6T Proposed 9T

Write Delay(s)

loop-cutting write scheme. During a write ‘0’ operation, the access device only needs to overcome the pull-up strength of M2 to transfer data. Consequently, the VTC of the right inverter is extremely shaped and essentially equal to the standby mode VTC. In addition, an N-type access transistor provides a strong transfer ‘0’ characteristic and long-channel P-type device gives a weak pull-up strength, making write ‘0’ successful easily. On the other hand, for a write ‘1’ operation, it hardly suffers any impediment from pull-up or pull-down networks benefiting from the cut-off loop, except the weak transfer ‘1’ characteristic of the NMOS themselves, hence exhibiting a sharp VTC for ‘QB’ and a constant VTC for ‘Q’. It is noteworthy to mention that the SNM of write ‘1’ is equal to the switching threshold of the right inverter. Apparently, we can observe that the 9T cell provides more ample noise margin for write ‘1’ while slightly higher for write ‘0’ as compared to 6T cell. The scaled voltage is the main restriction of single-ended SRAM structure. It is reported that the cell fails to write when VDD is reduced to 0.7 V in traditional SE 5T SRAM [23] while 0.6 V in standard 6T SRAM at 65 nm technology node [24]. To qualify the write ability of SRAM cells at lower supply power, the WSNM description for each design with voltage scaling is charted in Fig. 13. These experimental results are obtained at the worst write scenario (SNFP corner, 125 1C) with 3000 samples MC simulations. Obviously, the proposed design provides slightly improvement in write ‘0’ SNM compared with standard 6T cell, but offers more ample write ‘1’ SNM as much as 1.40
improvement at 1.0 V while up to 8.16
improvement at 0.3 V, thereby indicating a superior write ability at each voltage. However, the proposed design sacrifices write speed to obtain remarkably enhancement for write margin. As shown in Fig. 14, the standard 6T cell outperforms the proposed 9T cell noticeably in write delay. Even approximately one order of magnitude speed performance discrepancy is achieved between two SRAM cells when the voltage is reduced down to beyond 0.5 V. Fortunately, the write delays of the high-voltage regions do not exert an adverse effect on functionality and operating frequency in the proposed design, while the speed performance is a secondary consideration in the low-voltage regions since the voltage is mainly the primary consideration in this environment.

10-9

10-10

≈1 order of magnitude

10-11 0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Voltage(V) Fig. 14. Mean write time analysis for SRAM cells.

FNSP corner T=125°C VDD=0.9V MC=3000 Sigma=3

0.8

SNM

QB(Q)(V)

6

0.6

0.4

0.2

0.0 0.0

0.2

0.4

0.6

0.8

Q(QB)(V) Fig. 15. Statistical read butterfly curves of standard 6T cell.

degradation of read SNM (RSNM) resulting from the internal contention between access and pull-down transistors. On the other hand, the utmost asymmetric VTCs appear in the proposed 9T cell, leading to a severely feeble read margin. Unlike other SRAM cells [4–7], [11–13] which enable a disturb-free read by isolating the read current from storage elements to obtain ample noise margin equal to hold SNM, our proposed design accomplishes a non-destructive read by cutting off the feedback loop, Thus, storage node Q is decoupled from read current. Even storage node QB arrives a certain voltage far higher than the switching threshold of M4 during a read ‘1’, the voltage value at node Q would not be affected absolutely by node QB due to the turn-off M7. However, lacking pull-down network makes node Q floating and achieving a distorted read VTC depicted in Fig. 15 while a ‘0’ storing at node Q, resulting in a degraded read SNM. As shown in Fig. 17, the proposed 9T cell has a lower read margin before voltage reducing by 0.7 V as compared to 6T cell and an upgraded RSNM is achieved in 9T with voltage continuing to scale. This is because leakage current decreases exponentially with the reducing voltage, which lessens the negative impact on stability of node Q, thereby achieving an upgraded RSNM at low supply voltage. By that as it may, the 9T’s SNM of read is much smaller than that of standby and write state, which results in the cell having not ample resilience to overcome noise. Seemingly, the proposed design compared unfavorably with standard 6T cell and has not sufficient capability in terms of read margin. However, a loop-cutting transistor protects storage nodes

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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7

100

Asymmetric VTCs SNM of 'Q'

0.8

80

Proposed 9T

RNM(mV)

60

QB(Q)(V)

0.6

SNM of 'QB' 0.4

FNSP corner T=125°C VDD=0.9V MC=3000 Sigma=3

0.2

40

Standard 6T

20 0 -20

10

-40

8

2 6

4

Irea

d(u

0.0 0.0

0.2

0.4

0.6

0.8

Q(QB)(V)

A)

4

6

(

W

2

8

)

um

/L(

) um

Fig. 18. RSNM variations as a function of read current of SRAM cells.

Fig. 16. Statistical read butterfly curves of proposed design.

Duration for 'Q'=0

30

Proposed 9T Standard 6T

100

20 Degraded RSNM Upgraded RSNM

60

Time(ns)

RSNM(mv)

80

Feasible zone 10

40

0

20

-10

Min. pluse width of CLB for read Min. pluse width of CLB for write

0.2

0 0.2

0.4

0.6

0.8

1.0

Voltage(V) Fig. 17. RSNM comparisons at different voltages.

from disturbing in 9T cell as the preceding discussion. Even the SNM is less than zero, the cell still substantially ensures a nonintrusive read operation, as illustrated in Section 2.3. In addition, the read current has little respect of read stability in 9T cell while that is restricted by RSNM in 6T cell. As shown in Fig. 18, the Iread is increased by enlarging the W/L ratios of devices. In 6T cell, the RSNM diminishes rapidly with read current strengthening, whereas the 9T cell still maintains their original RSNM value, indicating the independency between stability and read current. Accordingly, we can lower the threshold voltage of read buffer in our proposed design to attain a large read speed performance on the premise that additional area and cell stability are not sacrificed, notwithstanding the leakage current penalty. Overall speaking, our proposed design has excellent advantage in read performance over the traditional 6T cell.

3.5. Half-selected analysis As the preceding discussions, regardless of read or write, the half-selected cells stored ‘0’ data in a column are susceptible to leakage current in the proposed 9T cell. In the case in which node ‘Q's are ‘0’, while the SRAM cell is being accessed, the other cells will suffer leakage disturbance. If the evaluation phase lasts too long, the ‘0’ node of the column-selection cells may bump up to some uncertain voltage which subsequently devastates it. Nonetheless, the accessed cell will fail to perform a success operation if the access time is too short. So, the requirement of evaluated time falls in a dilemma. It should be long enough to prevent

0.3

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0.8

0.9

1.0

Supply Voltage(V) Fig. 19. Simulated duration requirements for read and write under stored ‘0’ in bit-interleaving.

malfunction and at the same time short sufficient to guarantee satisfactions to column-selection cells. Fig. 19 presents the duration requirements for each operation under Q ¼0 in bit-interleaving. There is no doubt that the proposed design has sufficient competence to tune the pulse widths of word-lines and bit-lines to appease all the cells in a column. The overlapping zone besmeared with tilted dashed line describes the feasible pulse width range, in which the SRAM can assure the functionalities of read, write and half-selected operations effectively. 3.6. Process variation sensitivity To quantify the robustness of the proposed design under process variation, the SNM sensitivity analysis for device parameter variations such as W, L and VTH is done. Small variations in these parameters were made to identify the sensitivities of these parameters, in which device, and how much variation a design can tolerate to determine the parametric yield in SRAM. These parameters are assumed to have percentage change, namely, the parameter variations are calculated as nW/W, nL/L and nVTH/ VTH. In addition, the SNM sensitivity to a device parameter is defined as the variation in SNM (nSNM) to primal SNM, that is nSNM /SNM. Figs. 20, 21 and 22 show the relationships between various SNM and percentage variations in W, L and VTH for standard 6T and proposed 9T cell at 0.9 V, respectively. The variations of these parameters are supposed to range from  10% to 10%. In both the SRAM cells, RSNM is more sensitive to variations than the other

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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Fig. 20. HSNM variations of SRAM cells by varying the device parameters: (a) change percentage in W, (b) change percentage in L, and (c) change percentage in VTH.

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Vth Variation(%) Fig. 21. WSNM variations of SRAM cells by varying the device parameters: (a) change percentage in W, (b) change percentage in L, and (c) change percentage in VTH.

SNMs since it is more susceptible to inner contention of the cell. Moreover, in the standard 6T cell, SNMs have less resilience to VTH variation followed by L and W variant. Especially for RSNM, 20% variation in VTH even can give rise to up to 44.7% variation in SNM, because the fluctuated VTH leads to large variations in switching threshold voltage of inverters, and also introduces deleterious read current disturbance which is capable of inducing SNM degradation severely. On the other hand, the HSNM and WSNM of the proposed 9T cell shows less tolerance in VTH while the SNM is more sensitive to L variation. It indicates that the pronounced short channel effect of drain-induced barrier lowering (DIBL) significantly deteriorates SNM as it reduces inverter gain. In a word, the variations in these parameters exert less influence on SNM variations in the proposed 9T cell. As a result, our proposed design offers more robustness to process variation and may have better parametric yield. 3.7. Failure probabilities SRAM is vulnerable to interdie as well as intradie process variations, limiting the minimum operating voltage. The combined effect of the lower supply voltage along with the increased process variations may render SRAM more prone to failures involving read failure, write failure and hold failure. To estimate these failure probabilities, MC simulations with 6-sigma under process variations including W, L and VTH at their worst case scenarios are done, and each parameter is assumed to have a Gaussian distribution. Read failure, write failure and hold failure are estimated as follows: P read  fail ; P hold_fail ¼ Prob UðRSNM; HSNM o kTÞ

P write  fail ¼ Prob UðWSNM o 0Þ Generally, kT is the thermal voltage (typically, kT¼26 mV at room temperature). Fig. 23 plots the failure probabilities versus supply voltages for SRAM cells. As observed, the proposed design compares favorably with standard 6T cell in terms of read and write failure probabilities. Although the 9T cell has not an improvement so notably in write ‘0’ failure probability, it provides several orders of magnitude improvement in read failure while exceeding a factor of 10 in write ‘1’ failure reduction. As opposed to the read and write failure probabilities, it is found that our proposed 9T cell exhibits a slightly higher hold failure probability compared with the traditional 6T cell since the stacked NMOS devices of the left inverter in 9T cell degrades the HSNM. In contrast, hold failure probability is several orders of magnitude less than read and write failure probabilities. Hence, this inferior hold failure probability is completely acceptable for 9T cell. In other words, the proposed 9T cell can tolerate a lower Vmin than the 6T cell. 3.8. Energy consumption In traditional 6T SRAM, an accessed cell is performing a write operation while the half-selected cells in a line are undergoing a read operation, which incurs much more energy budget. But in the proposed 9T SRAM, the additional energy waste issue is addressed effectively during a write operation by a column-aware feedbackcutoff write scheme. Fig. 24 compares the energy consumption of

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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9

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Fig. 24. Energy consumption comparisons of SRAM cells at different column multiplexers. -15

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1.13X 1.32X 1.65X

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standard 6T and proposed 9T SRAMs. The experimental results are simulated by varying column selection number at the constant 32
32 bit array. Namely, the two arrays comprised of 6T and 9T cells have identical number in word-lines and outputs (or bitlines). When the column number changes by 2k, the output number reduces by 2k. For example, if the column number is 2, then the output number is 16; if the column number is 4, then the output number is 8; the rest can be deduced by analogy. The average energy dissipation of the 32
32 bit array (precluding the peripheral circuits) is used to identify the energy characteristic of SRAMs, and the clock frequency is assumed to 1 GHz. In addition,

0.0 1V

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Fig. 25. Leakage energy consumption comparisons of SRAM cells at different voltages.

each word-line has the same switching frequency. Ideally, if the column number increases by 2, then the output number reduces by 2; thus the energy consumption would be saved by 2, when ignoring the word-line and bit-line capacitances. Actually, for the 6T array, additional 2
half-selected cells are required to perform read operation if the column number changes by 2, consuming additional read energy. By contrast, half-selected cells in the 9T SRAM are absolutely turned off thanks to the bit-interleaving capability, and the additional energy consumption is introduced resulting from the increased word-line capacitance loading. From the view of Fig. 24, the energy consumption of the 6T SRAM decreases smoothly while that of the 9T SRAM reduces precipitously with the column number increasing. At first, the 9T array dissipates more energy than the 6T array since it has higher activity frequency. Nonetheless, as the column number increases, the additional read energy dominates the energy consumption in the 6T array. Finally, when the column number is 32, the 9T array can achieve as much as 5
improvement compared with the 6T array. From the preceding analysis, in other words, the energy consumption per bit of the 6T array is larger than that of the 9T array during a write operation when performing a bit-interleaving structure (MUX 44). Also, the leakage energy consumption comparisons during the standby mode are discussed here. As illustrated in Fig. 25, the proposed 9T SRAM offers 1.13
improvement in energy saving compared with standard 6T SRAM when supply voltage is 1.0 V, and 2.12
improvement is provided as voltage scales down to 0.4 V. In a word, our proposed design excels standard 6T cell noticeably in energy consumption.

Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i

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4. Conclusions A novel read disturb-free 9T SRAM cell with bit-interleaving capability is proposed in this paper. The column-aware feedbackcutoff write scheme is exploited in the cell to facilitate the write scheme, achieving significantly enhancement in write ability. Also, dynamic read-decoupled assist is utilized to isolate the read path from the cell core, enabling a non-penetrative read operation. In addition, the bit-interleaving configuration of the proposed design frees the half-selected problem completely. As compared to standard 6T cell, our proposed 9T cell provides even up to 8.16
improvement extremely in write ability with 3000 occurrences MC simulation using 65 nm process, and excellent read robustness as well. Moreover, better process variation tolerance, lower write and leakage energy consumption are achieved, notwithstanding sacrificing 37.1% area overhead and write speed performance loss but affordable.

[9]

[10] [11]

[12] [13]

[14]

[15] [16] [17]

Acknowledgment [18]

This work was partly supported by the National Natural Science Foundation of China (No. 61234002).

[19]

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Please cite this article as: L. Wen, et al., Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.020i